1.3 A Branch Delay Slot is (always advantageous / always disadvantageous / depends on compiler s ability to fill the slot) Explain

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2 ee57_mt_sp2.fm Spring 2 EE57 Instructor: Gandhi Puvvada Midterm Exam (2%) Date: //2, Friday Time: :M - 2:2PM in THH2 Name: Total points: 28 Perfect score: 9 / 28 ( 23 points) 5 min. Pipelining I.F.R.F (Internally Forwarding Register File): I.F.R.F is (useful/useless but harmless/harmful) in a pipelined CPU. I.F.R.F is (useful/useless but harmless/harmful) in a multicycle CPU (st ed.). I.F.R.F is (useful/useless but harmless/harmful) in a multicycle CPU (2nd ed.). I.F.R.F is (useful/useless but harmless/harmful) in a single cycle CPU. If you marked harmful for any one, explain why it is harmful..2 If all the above four designs of the CPU (the single cycle CPU, the two multicycle CPUs, and the 5- stage pipelined CPU) are operated at the same (clock) frequency, best performance is provided by Explain..3 Branch Delay Slot is (always advantageous / always disadvantageous / depends on compiler s ability to fill the slot) Explain. If the original 5-stage CPU of first edition did not have a delay slot for the load-word instruction, it means, we (need / do not need) to have a Hazard Detection Unit (HDU) to stall an instruction in the delay slot, which is dependent on the load word. March 3, 2 : am EE57 Midterm Exam - Spring 2 Page - / 9 C Copyright 2 Gandhi Puvvada

9 ee57_mt_sp2.fm 2 ( = 8 points) 7 min. Pipelining (Modified Lab 7 part 3): In the Fall 2 midterm exam, we have an unit in each of the two EX stages, EX and EX2. Here, those two stages, EX and EX2, are merged into EX2. So DD8 needs an extra clock in EX2 as it has to go through the second also. Instruction Operation Opcode MSD 32-bit instruction in hex BZ DD8 D=Destination, S=Source NOP DS $R, $X; ($R) <= ($X) 8 8DS SUB3 $R, $X; ($R) <= ($X) - 3 DS BZ $X, JJJJ; (PC) <= JJJJ if ($X) = 2 JJJJDS $R, $X; ($R) <= ($X) + 2 2DS DD8 $R, $X; ($R) <= ($X) + 8 DS Further we introduced a BZ (Branch if Zero) instruction. It uses the opcode previously allocated to the SUB3 instruction. The instructions are 32-bits but the addresses are only 6-bit. PC is 6-bit wide and is incremented by a "". The JJJJ in the BZ $X, JJJJ stands for a 6-bit (-digit hex) absolute branch address. If the source register $X is a zero then branch to JJJJ takes place [ (PC) <= JJJJ if ($X) = ]. The "D" in "JJJJDS" is a random hex digit and should not be treated as a valid destination, similar to the "DS" in "DS" for a NOP instruction. BZ executes from the ID stage. You need to complete the early branch mechanism (dependency stalls, branch execution by causing PC to be changed to JJJJ and flushing the IF stage instruction, avoiding spurious branch execution during stalling, etc.) Complete the design on the page next to next (on page ). 2.2 In you lab 7 Part 3 Subpart 2 (EX and EX2 merged case), you used the left side circuit to stall for clock. Complete the design to show the STLL signal. Suppose you are given a flipflop with an asynchronous set as shown in the right side below (instead of the FF with an asynchronous clear as shown on the left). Redesign your stall circuit with this FF and show the STLL signal. DD D Q CLK CLK CLR CLK SET D Q CLK 2.3 When STLL_DD8 is active, you stall the entire pipeline. True / False When STLL_BR is active, you stall the entire pipeline. True / False IF_Flush mechanism here is (the same as / different from) the wrist-band mechanism used in our pipelined CPU design. March 3, 2 : am EE57 Midterm Exam - Spring 2 Page - 2 / 9 C Copyright 2 Gandhi Puvvada

10 ee57_mt_sp2.fm 2. In this design we have implemented an early branch. Would a medium branch from EX2 be better? Yes / No / It depends. Explain. Is it possible to postpone executing the BZ instruction all the way into the WB stage (WB!, not EX2)? Not Possible / possible but undesirable / possible and desirable. Explain 2.5 Combining EX and EX2 into one EX2 stage (as done here) is (always better / always worse / depends on the instruction sequence in the program). Explain. 2.6 How come, we carried (PC + ) to the ID stage in the text book design, but we do not carry (PC+) to the ID stage here? 2.7 Complete the following "Single Cycle CPU" kind of a design for the pipelined design on the next page. Complete the control unit also. PCSource Single Cycle CPU 6 6 PC_EN PC I-MEM Branch ddress JJJJ CU Reg. File RD R-Write RegWrite _ZERO + R_Mux SKIP + R2_Mux SKIP2 DD8 BZ complete this Branch pril, 2 2:9 pm EE57 Midterm Exam - Spring 2 Page - 3 / 9 C Copyright 2 Gandhi Puvvada

11 ee57_mt_sp2.fm 2. In this design we have implemented an early branch. Would a medium branch from EX2 be better? Yes / No / It depends. Explain. Is it possible to postpone executing the BZ instruction all the way into the WB stage (WB!, not EX2)? Not Possible / possible but undesirable / possible and desirable. Explain 2.5 Combining EX and EX2 into one EX2 stage (as done here) is (always better / always worse / depends on the instruction sequence in the program). Explain. 2.6 How come, we carried (PC + ) to the ID stage in the text book design, but we do not carry (PC+) to the ID stage here? 2.7 Complete the following "Single Cycle CPU" kind of a design for the pipelined design on the next page. Complete the control unit also. PCSource Single Cycle CPU 6 6 PC_EN PC I-MEM Branch ddress JJJJ CU Reg. File RD R-Write RegWrite _ZERO + R_Mux SKIP + R2_Mux SKIP2 DD8 BZ complete this Branch March 3, 2 : am EE57 Midterm Exam - Spring 2 Page - 3 / 9 C Copyright 2 Gandhi Puvvada

12 pril, 2 2:9 pm EE57 Midterm Exam - Spring 2 Page - / 9 PCSource 6 PC EN 6 + IF 6 6 I-MEM IF_Flush JJJJ BZ DD8 EN ID Comp Station in ID Stage ID_XMEX2 HDU_BR Branch ddress Reg. File ID_ ID_BZ ID_ ID_DD8 RD R-Write STLL_BR _ZERO XMEX2 DD8 EN EX2_XMEX2 X_Mux FORW FU + R_Mux SKIP EX2 + EX2_ EX2_ EX2_DD8 EX2_ WB EN R2_Mux WB_RD RD SKIP2 EX2_Write Write WB_Write WB_ ee57_mt_sp2.fm C Copyright 2 Gandhi Puvvada Comp Station in ID Stage ID_ Matched with EX2_ ID_XMEX2 P=Q P Q ID_ EX2_. Complete all missing connections to D Q CLK CLK CLR 2. Complete the STLL_DD8 logic in EX2 and STLL_BR logic in ID stage. 3. Complete all four enable (EN) controls on the pipeline registers (including PC).. Draw the logic to produce PCSource, IF_Flush, FORW, SKIP, SKIP2 on this page itsef. Modified LB 7 Part 3 Block Diagram STLL_DD8 Q#2

13 March 3, 2 : am EE57 Midterm Exam - Spring 2 Page - / 9 PCSource 6 PC EN 6 + IF 6 6 I-MEM IF_Flush JJJJ BZ DD8 EN ID Comp Station in ID Stage ID_XMEX2 HDU_BR Branch ddress Reg. File ID_ ID_BZ ID_ ID_DD8 RD R-Write STLL_BR _ZERO XMEX2 DD8 EN EX2_XMEX2 X_Mux FORW FU + R_Mux SKIP EX2 + EX2_ EX2_ EX2_DD8 EX2_ WB EN R2_Mux WB_RD RD SKIP2 EX2_Write Write WB_Write WB_ ee57_mt_sp2.fm C Copyright 2 Gandhi Puvvada Comp Station in ID Stage ID_ Matched with EX2_ ID_XMEX2 P=Q P Q ID_ EX2_. Complete all missing connections to D Q CLK CLK CLR 2. Complete the STLL_DD8 logic in EX2 and STLL_BR logic in ID stage. 3. Complete all four enable (EN) controls on the pipeline registers (including PC).. Draw the logic to produce PCSource, IF_Flush, FORW, SKIP, SKIP2 on this page itsef. Modified LB 7 Part 3 Block Diagram STLL_DD8 Q#2

14 ee57_mt_sp2.fm 2.8 Now let us try to build a multi-cycle version for the design on the previous page. It is proposed that, we go for a single LU, which can add a selected constant, ( for PC and for or DD8). DD8 uses the LU twice to add two times. This multi-cycle datapath is similar to the st edition design except that here the LU is built using dynamic logic (like in the 2nd edition). There is an LUOut register like in the 2nd edition. You need to carefully decide when to take (tap) data from the upstream of the LUOut register and when to take (tap) data from the downstream of the LUOut register. We have an IR register (Instruction Register) to hold the instruction at the end of the first state(s). IR is needed as PC is incremented using the LU in the very first state. We need to support a NOP instruction here besides,, DD8, and BZ Complete the datapath and the state diagram for control unit on the next two pages. To some extent, our state diagram resembles the 2nd edition state diagram reproduced below for your reference. We are doing a MOORE kind of state diagram and may be a wasting a few clocks. March 3, 2 : am EE57 Midterm Exam - Spring 2 Page - 5 / 9 C Copyright 2 Gandhi Puvvada

15 pril, 2 2:9 pm EE57 Midterm Exam - Spring 2 Page - 6 / 9 C Copyright 2 Gandhi Puvvada 6 PCSource PC_EN PC We (need / do not need) an LUOut_write control signal. I-MEM IRWrite 6 6 IR Branch ddress JJJJ DD8 BZ CU PCWrite PCWriteCond 6 lower 6 of the Strip 6 H R_Mux SKIP CU Concatenate Reg. File RD R-Write RegWrite Multi Cycle CPU 32 _ZERO PCWriteCond PCWrite PCSource ONE/FOUR Source[:] SKIP X_Mux Source[] C_Mux In_Mux Source[] ONE/FOUR LU B +B LUOut ee57_mt_sp2.fm

16 March 3, 2 : am EE57 Midterm Exam - Spring 2 Page - 6 / 9 C Copyright 2 Gandhi Puvvada 6 PCSource PC_EN PC We (need / do not need) an LUOut_write control signal. I-MEM IRWrite 6 6 IR Branch ddress JJJJ DD8 BZ CU PCWrite PCWriteCond 6 lower 6 of the Strip 6 H R_Mux SKIP Concatenate Reg. File RD R-Write RegWrite PCWriteCond PCWrite ONE/FOUR Source[:] SKIP Branch Multi Cycle CPU 32 _ZERO X_Mux Source[] C_Mux In_Mux Source[] ONE/FOUR LU B +B LUOut ee57_mt_sp2.fm

17 ee57_mt_sp2.fm NOP (= DD8 BZ) S S PCSource= Source[:]= ONE/FOUR = No RTL needed. No signal list. or DD8 BZ S2 S3 S6 DD8 S S Mr. Trojan says that, we can easily improve the above state machine by combining states S, S2, and S6 into one mealy state S26. Complete the S26 state on the side and also write the new state transition condition from S26 to S. To S S26 pril, 2 2:9 pm EE57 Midterm Exam - Spring 2 Page - 7 / 9 C Copyright 2 Gandhi Puvvada

18 ee57_mt_sp2.fm NOP (= DD8 BZ) S S PCSource= Source[:]= ONE/FOUR = No RTL needed. No signal list. or DD8 BZ S2 S3 S6 DD8 S S Mr. Trojan says that, we can easily improve the above state machine by combining states S, S2, and S6 into one mealy state S26. Complete the S26 state on the side and also write the new state transition condition from S26 to S. To S S26 March 3, 2 : am EE57 Midterm Exam - Spring 2 Page - 7 / 9 C Copyright 2 Gandhi Puvvada

1 ( 23 points) 15 min.

1 ( 23 points) 15 min. ee57_mt_sp2.fm Spring 2 EE57 Instructor: Gandhi Puvvada Midterm Exam (2%) Date: //2, Friday Time: :M - 2:2PM in THH2 Name: Total points: 28 Perfect score: 9 / 28 ( 23 points) 5 min. Pipelining 5 5 3. I.F.R.F