Part III Multiplication

Transcription

1 Prt III Multiliction Prts Chters I. Number Reresenttion.... Numbers nd Arithmetic Reresenting Signed Numbers Redundnt Number Systems Residue Number Systems Elementry Oertions II. III. IV. Addition / Subtrction Multiliction Division Bsic Addition nd Counting Crry-Lookhed Adders Vritions in Fst Adders Multioernd Addition Bsic Multiliction Schemes High-Rdi Multiliers Tree nd Arry Multiliers Vritions in Multiliers Bsic Division Schemes High-Rdi Dividers Vritions in Dividers Division by Convergence V. Rel Arithmetic Floting-Point Reeresenttions Floting-Point Oertions Errors nd Error Control Precise nd Certifible Arithmetic VI. Function Evlution.... Squre-Rooting Methods The CORDIC Algorithms Vritions in Function Evlution Arithmetic by Tble Looku VII. Imlementtion Toics 5. High-Throughut Arithmetic 6. Low-Power Arithmetic 7. Fult-Tolernt Arithmetic 8. Pst, Reconfigurble Present, nd Arithmetic Future Aendi: Pst, Present, nd Future Ar. Comuter Arithmetic, Multiliction Slide

2 About This Presenttion This resenttion is intended to suort the use of the tetbook Comuter Arithmetic: Algorithms nd Hrdwre Designs (Oford U. Press, nd ed.,, ISBN ). It is udted regulrly by the uthor s rt of his teching of the grdute course ECE 5B, Comuter Arithmetic, t the University of Cliforni, Snt Brbr. Instructors cn use these slides freely in clssroom teching nd for other eductionl uroses. Unuthorized uses re strictly rohibited. Behrooz Prhmi Edition Relesed Revised Revised Revised Revised First Jn. Se. Se. Oct. 5 My 7 Ar. 8 Ar. 9 Second Ar. Ar. Ar. Comuter Arithmetic, Multiliction Slide

3 III Multiliction Review multiliction schemes nd vrious seedu methods Multiliction is hevily used (in rith & rry indeing) Division = reciroction + multiliction Multiliction seedu: high-rdi, tree, recursive Bit-seril, modulr, nd rry multiliers Toics in This Prt Chter 9 Bsic Multiliction Schemes Chter High-Rdi Multiliers Chter Tree nd Arry Multiliers Chter Vritions in Multiliers Ar. Comuter Arithmetic, Multiliction Slide

4 Well, well, for rbbit, you re not very good t multilying, re you? Ar. Comuter Arithmetic, Multiliction Slide

5 9 Bsic Multiliction Schemes Chter Gols Study shift/dd or bit-t--time multiliers nd set the stge for fster methods nd vritions to be covered in Chters - Chter Highlights Multiliction = multioernd ddition Hrdwre, firmwre, softwre lgorithms Multilying s-comlement numbers The secil cse of one constnt oernd Ar. Comuter Arithmetic, Multiliction Slide 5

6 Bsic Multiliction Schemes: Toics Toics in This Chter 9. Shift/Add Multiliction Algorithms 9. Progrmmed Multiliction 9. Bsic Hrdwre Multiliers 9. Multiliction of Signed Numbers 9.5 Multiliction by Constnts 9.6 Preview of Fst Multiliers Ar. Comuter Arithmetic, Multiliction Slide 6

7 9. Shift/Add Multiliction Algorithms Nottion for our discussion of multiliction lgorithms: Multilicnd k k... Multilier k k... Product ( ) k k... Initilly, we ssume unsigned oernds Multilicnd Multilier Prtil roducts bit-mtri Product Fig. 9. Multiliction of two -bit unsigned binry numbers in dot nottion. Ar. Comuter Arithmetic, Multiliction Slide 7

8 Multiliction Recurrence Fig. 9. Multilicnd Multilier Prtil roducts bit-mtri Product Preferred Multiliction with right shifts: to-to-bottom ccumultion (j+) =( (j) + j k ) with () = nd dd (k) = = + () k shift right Multiliction with left shifts: bottom-to-to ccumultion (j+) = (j) + k j with () = nd shift (k) = = + () k dd Ar. Comuter Arithmetic, Multiliction Slide 8

9 Emles of Bsic Multiliction Right-shift lgorithm Left-shift lgorithm ======================== ======================= ======================== ======================= () () + () + () () () + () + () () () + () + (j+) = ( (j) + j k ) () dd () () shift right + () + () () () ======================== ======================= Fig. 9. Emles of sequentil multiliction with right nd left shifts. Check: = = Ar. Comuter Arithmetic, Multiliction Slide 9

10 Emles of Bsic Multiliction (Continued) Right-shift lgorithm Left-shift lgorithm ======================== ======================= ======================== ======================= () () + () + () () () + () + () () () + (j+) = (j) + () k j shift + () () dd () + () + () () () ======================== ======================= Fig. 9. Emles of sequentil multiliction with right nd left shifts. Check: = = Ar. Comuter Arithmetic, Multiliction Slide

11 9. Progrmmed Multiliction {Using right shifts, multily unsigned m_cnd nd m_ier, storing the resultnt k-bit roduct in _high nd _low. Registers: R holds Rc for counter R Rc Counter R for m_cnd R for m_ier R for _high Rq for _low} R Multilicnd R Multilier {Lod oernds into registers R nd R} R Product, high Rq Product, low mult: lod R with m_cnd lod R with m_ier {Initilize rtil roduct nd counter} coy R into R coy R into Rq lod k into Rc {Begin multiliction loo} m_loo: shift R right {LSB moves to crry flg} brnch no_dd if crry = dd R to R {crry flg is set to cout} no_dd: rotte R right {crry to MSB, LSB to crry} rotte Rq right {crry to MSB, LSB to crry} decr Rc {decrement counter by } brnch m_loo if Rc {Store the roduct} store R into _high store Rq into _low m_done:... Fig. 9. Progrmmed multiliction (right-shift lgorithm). Ar. Comuter Arithmetic, Multiliction Slide

12 Time Comleity of Progrmmed Multiliction Assume k-bit words k itertions of the min loo 6-7 instructions er itertion, deending on the multilier bit Thus, 6k + to 7k + mchine instructions, ignoring oernd lods nd result store k = imlies + instructions on verge This is too slow for mny modern lictions! Microrogrmmed multily would be somewht better Ar. Comuter Arithmetic, Multiliction Slide

13 9. Bsic Hrdwre Multiliers Shift Multilier Doublewidth rtil roduct Shift (j) Multilicnd Mu k j c out j k (j+) = ( (j) + j k ) Adder k dd shift right Fig. 9. Hrdwre reliztion of the sequentil multiliction lgorithm with dditions nd right shifts. Ar. Comuter Arithmetic, Multiliction Slide

14 Emle of Hrdwre Multiliction Shift Multilier (j) Doublewidth rtil roduct Shift () ten () ten Multilicnd Mu k j () ten c out j k Adder k (j+) = ( (j) + j k ) dd shift right Fig. 9. Hrdwre reliztion of the sequentil multiliction lgorithm with dditions nd right shifts. Ar. Comuter Arithmetic, Multiliction Slide

15 Performing Add nd Shift in One Clock Cycle Adder s crry-out Adder s sum k k Unused rt of the multilier Prtil roduct (j) k k To dder To mu control Fig. 9.5 Combining the loding nd shifting of the double-width register holding the rtil roduct nd the rtilly used multilier. Ar. Comuter Arithmetic, Multiliction Slide 5

16 Sequentil Multiliction with Left Shifts Shift Multilier Doublewidth rtil roduct Shift (j) k-j- k Multilicnd Mu k-j- k c out k-bit dder k Fig. 9.b Hrdwre reliztion of the sequentil multiliction lgorithm with left shifts nd dditions. Ar. Comuter Arithmetic, Multiliction Slide 6

17 9. Multiliction of Signed Numbers Fig. 9.6 Sequentil multiliction of s-comlement numbers with right shifts (ositive multilier). Negtive multilicnd, ositive multilier: No chnge, other thn looking out for roer sign etension ============================ ============================ () + () () + () () + () () + () () + (5) (5) ============================ Check: = = Ar. Comuter Arithmetic, Multiliction Slide 7

18 The Cse of Negtive Multilier Fig. 9.7 Sequentil multiliction of s-comlement numbers with right shifts (negtive multilier). Negtive multilicnd, negtive multilier: In lst ste (the sign bit), subtrct rther thn dd ============================ ============================ () + Check: = = () () + () () + () () + () () +( ) (5) (5) ============================ Ar. Comuter Arithmetic, Multiliction Slide 8

19 Signed s-comlement Hrdwre Multilier Multilier Prtil roduct k + Multilicnd Mu k + Enble Select c out Adder k +, ecet in lst cycle Fig. 9.8 The s-comlement sequentil hrdwre multilier. c in Ar. Comuter Arithmetic, Multiliction Slide 9

20 Booth s Recoding Tble 9. Rdi- Booth s recoding i i y i Elntion No string of s in sight End of string of s in Beginning of string of s in Continution of string of s in Emle Oernd () Recoded version y Justifiction j + j i+ + i = j+ i Ar. Comuter Arithmetic, Multiliction Slide

21 Emle Multiliction with Booth s Recoding Fig. 9.9 Sequentil multiliction of s-comlement numbers with right shifts by mens of Booth s recoding. i i y i ============================ Multilier y Booth-recoded ============================ () Check: +y () () +y = = () () +y () () +y () () y (5) (5) ============================ Ar. Comuter Arithmetic, Multiliction Slide

22 9.5 Multiliction by Constnts Elicit, e.g. y := + Imlicit, e.g. A[i, j] := A[i, j] + B[i, j] Address of A[i, j] = bse + n i + j... m... n Row i Softwre sects: Otimizing comilers relce multilictions by shifts/dds/subs Produce efficient code using s few registers s ossible Find the best code by time/sce-efficient lgorithm Hrdwre sects: Column j Synthesize secil-urose units such s filters y[t] = [t] + [t ] + [t ] + b y[t ] + b y[t ] Ar. Comuter Arithmetic, Multiliction Slide

23 Multiliction Using Binry Ension Emle: Multily R by the constnt = ( ) two R R shift-left R R + R R6 R shift-left R7 R6 + R R R7 shift-left R R + R Shift, dd Shift Ri: Register tht contins i times (R) This nottion is for clrity; only one register other thn R is needed Shorter sequence using shift-nd-dd instructions R R shift-left + R R7 R shift-left + R R R7 shift-left + R Ar. Comuter Arithmetic, Multiliction Slide

24 Multiliction vi Recoding Emle: Multily R by = ( ) two = ( ) two R8 R shift-left R7 R8 R R R7 shift-left R R + R Shift, dd Shift Shift, subtrct Shorter sequence using shift-nd-dd/subtrct instructions R7 R shift-left R R R7 shift-left + R 6 shift or dd ( shift-nd-dd) instructions needed without recoding Ar. Comuter Arithmetic, Multiliction Slide

25 Multiliction vi Fctoriztion Emle: Multily R by 9 = 7 7 = (8 ) (6 + ) R8 R shift-left R7 R8 R R R7 shift-left R9 R + R7 Shorter sequence using shift-nd-dd/subtrct instructions R7 R shift-left R R9 R7 shift-left + R7 Requires scrtch register for holding the 7 multile 9 = ( ) two = ( ) two More instructions my be needed without fctoriztion Ar. Comuter Arithmetic, Multiliction Slide 5

26 9.6 Preview of Fst Multiliers Viewing multiliction s multioernd ddition roblem, there re but two wys to seed it u. Reducing the number of oernds to be dded: Hndling more thn one multilier bit t time (high-rdi multiliers, Chter ) b. Adding the oernds fster: Prllel/ielined multioernd ddition (tree nd rry multiliers, Chter ) In Chter, we cover ll remining multiliction toics: Bit-seril multiliers Modulr multiliers Multily-dd units Squring s secil cse Ar. Comuter Arithmetic, Multiliction Slide 6

27 High-Rdi Multiliers Chter Gols Study techniques tht llow us to hndle more thn one multilier bit in ech cycle (two bits in rdi, three in rdi 8,...) Chter Highlights High rdi gives rise to difficult multiles Recoding (chnge of digit-set) s remedy Crry-sve ddition reduces cycle time Imlementtion nd otimiztion methods Ar. Comuter Arithmetic, Multiliction Slide 7

28 High-Rdi Multiliers: Toics Toics in This Chter. Rdi- Multiliction. Modified Booth s Recoding. Using Crry-Sve Adders. Rdi-8 nd Rdi-6 Multiliers.5 Multibet Multiliers.6 VLSI Comleity Issues Ar. Comuter Arithmetic, Multiliction Slide 8

29 . Rdi- Multiliction Fig. 9. (modified) r r r r Multilicnd Multilier Prtil roducts bit-mtri Product Preferred Multiliction with right shifts in rdi r : to-to-bottom ccumultion (j+) =( (j) + j r k ) r with () = nd dd (k) = = + () r k shift right Multiliction with left shifts in rdi r : bottom-to-to ccumultion (j+) = r (j) + k j with () = nd shift (k) = = + () r k dd Ar. Comuter Arithmetic, Multiliction Slide 9

30 Rdi- Multiliction in Dot Nottion Multilicnd Multilier Fig. 9. Prtil roducts bit-mtri Product Fig.. Rdi-, or two-bit-t--time, multiliction in dot nottion Number of cycles is hlved, but now the difficult multile must be delt with ( ) two ( ) two Multilicnd Multilier Product Ar. Comuter Arithmetic, Multiliction Slide

31 A Possible Design for Rdi- Multilier Precomuted vi shift-nd-dd ( = + ) Multilier -bit shifts k/ + cycles, rther thn k One etr cycle over k/ not too bd, but we would like to void it if ossible Solving this roblem for rdi my lso hel when deling with even higher rdices Mu To the dder i+ Fig.. The multile genertion rt of rdi- multilier with recomuttion of. i Ar. Comuter Arithmetic, Multiliction Slide

32 Emle Rdi- Multiliction Using ================================ ================================ () +( ) two () () +( ) two () () ================================ Fig.. Emle of rdi- multiliction using the multile. ( ) ( ) Ar. Comuter Arithmetic, Multiliction Slide

33 Mu A Second Design for Rdi- Multilier To the dder -bit shifts Multilier i+ i c i+ i +c c Crry mod FF c i c Fig.. The multile genertion rt of rdi- multilier bsed on relcing with (crry into net higher rdi- multilier digit) nd. Set if i+ = i = or i+ ( if i c) = c = i+ i+ i c Mu control Set crry Ar. Comuter Arithmetic, Multiliction Slide

34 . Modified Booth s Recoding Tble. Rdi- Booth s recoding yielding (z k/... z z ) four i+ i i y i+ y i z i/ Elntion No string of s in sight End of string of s Isolted End of string of s Beginning of string of s End string, begin new one Beginning of string of s Continution of string of s Recoded Contet Rdi- digit rdi- digits Emle Oernd () Recoded version y () Rdi- version z Ar. Comuter Arithmetic, Multiliction Slide

35 Emle Multiliction vi Modified Booth s Recoding ================================ z Rdi- ================================ () +z () () +z () () ================================ Fig..5 Emle of rdi- multiliction with modified Booth s recoding of the scomlement multilier. ( ) ( ) Ar. Comuter Arithmetic, Multiliction Slide 5

36 Multile Genertion with Rdi- Booth s Recoding Multilier Init. Multilicnd Could hve nmed this signl one/two -bit shift neg i+ i i two Recoding Logic non Sign of Enble Mu Select k+ k,, or ---- Encoding ---- Digit neg two non Add/subtrct control z i/ To dder inut Fig..6 The multile genertion rt of rdi- multilier bsed on Booth s recoding. Ar. Comuter Arithmetic, Multiliction Slide 6

37 . Using Crry-Sve Adders Old Cumultive Prtil Product Mu Mu Multilier i+ i CSA Adder New Cumultive Prtil Product Fig..7 Rdi- multiliction with crry-sve dder used to combine the cumultive rtil roduct, i, nd i+ into two numbers. Ar. Comuter Arithmetic, Multiliction Slide 7

38 Keeing the Prtil Product in Crry-Sve Form Mu Multilier Sum Crry Prtil Product k Multilicnd k Sum Crry Right shift Mu k-bit CSA Crry k k Sum k-bit Adder () Multilier block digrm Uer hlf of PP Lower hlf of PP (b) Oertion in tyicl cycle Fig..8 Rdi- multiliction with the uer hlf of the cumultive rtil roduct ket in stored-crry form. Ar. Comuter Arithmetic, Multiliction Slide 8

39 Crry-Sve Multilier with Rdi- Booth s Recoding Multilier i+ i i- Booth recoder nd selector Old cumultive rtil roduct z i/ New cumultive rtil roduct CSA Adder FF -bit Adder Etr dot To the lower hlf of rtil roduct Fig..9 Rdi- multiliction with CSA used to combine the stored-crry cumultive rtil roduct nd z i/ into two numbers. Ar. Comuter Arithmetic, Multiliction Slide 9

40 Rdi- Booth s Recoding for Prllel Multiliction i+ i+ i i i Recoding Logic neg two non Fig.. Booth recoding nd multile selection logic for high-rdi or rllel multiliction. Enble Mu Select k+ Selective Comlement k+,, or,,,, or Etr "Dot" for Column i z i/ Ar. Comuter Arithmetic, Multiliction Slide

41 Yet Another Design for Rdi- Multiliction New Cumultive Prtil Product Old Cumultive Prtil Product CSA Mu CSA Mu Multilier i+ i Fig.. Rdi- multiliction, with the cumultive rtil roduct, i, nd i+ combined into two numbers by two CSAs. Adder FF -Bit Adder To the Lower Hlf of Prtil Product Ar. Comuter Arithmetic, Multiliction Slide

42 . Rdi-8 nd Rdi-6 Multiliers -bit right shift -Bit Shift 8 Mu Mu Mu Mu Multilier i+ i+ i+ i CSA CSA Fig.. Rdi-6 multiliction with the uer hlf of the cumultive rtil roduct in crry-sve form. CSA CSA Sum Crry Prtil Product (Uer Hlf) -Bit FF Adder To the Lower Hlf of Prtil Product Ar. Comuter Arithmetic, Multiliction Slide

43 Remove this mu & CSA nd relce the -bit shift (dder) with -bit shift (dder) to get rdi-8 multilier (cycle time will remin the sme, though) Other High-Rdi Multiliers -Bit Shift 8 Mu Mu Mu Mu Multilier i+ i+ i+ i CSA CSA A rdi-6 multilier design becomes rdi-56 multilier if rdi- Booth s recoding is lied first (the mues re relced by Booth recoding nd multile selection logic) CSA CSA Sum Crry Prtil Product (Uer Hlf) Fig.. -Bit FF Adder To the Lower Hlf of Prtil Product Ar. Comuter Arithmetic, Multiliction Slide

44 A Sectrum of Multilier Design Choices Adder Net multile Prtil roduct Severl multiles... Smll CSA tree Prtil roduct All multiles... Full CSA tree Adder Adder Bsic binry Seed u High-rdi or rtil tree Economize Full tree Fig.. High-rdi multiliers s intermedite between sequentil rdi- nd full-tree multiliers. Ar. Comuter Arithmetic, Multiliction Slide

45 .5 Multibet Multiliers Inuts Present stte Stte fli-flos Net-stte logic CLK Net-stte ecittion () Sequentil mchine with FFs Inuts Stte ltches Net-stte logic PH PH Net-stte logic Stte ltches Inuts (b) Sequentil mchine with ltches nd -hse clock Fig..5 Two-hse clocking for sequentil logic. Begin chnging FF contents Chnge becomes visible t FF outut Once cycle Observtion: Hlf of the clock cycle goes to wste Ar. Comuter Arithmetic, Multiliction Slide 5

46 Twin-Bet nd Three-Bet Multiliers Twin Multilier Registers This rdi-6 multilier runs t the clock rte of rdi-8 design (X seed) Pielined Rdi-8 Booth Recoder & Selector Pielined Rdi-8 Booth Recoder & Selector Node Bet- Inut CSA Sum CSA Sum Bet- Inut Node Crry Crry 5 6 Adder Fig.. Twin-bet multilier with rdi-8 Booth s recoding. FF 6-Bit Adder 6 To the Lower Hlf of Prtil Product Node Bet- Inut Fig..6 Concetul view of three-bet multilier. Ar. Comuter Arithmetic, Multiliction Slide 6

47 .6 VLSI Comleity Issues A rdi- b multilier requires: bk two-inut AND gtes to form the rtil roducts bit-mtri O(bk) re for the CSA tree At lest Θ(k) re for the finl crry-rogte dder Totl re: A = O(bk) Ltency: T = O((k/b) log b + log k) Any VLSI circuit comuting the roduct of two k-bit integers must stisfy the following constrints: AT grows t lest s fst s k / AT is t lest roortionl to k The receding rdi- b imlementtions re subotiml, becuse: AT = O(k log b + bk log k) AT = O((k /b) log b) Ar. Comuter Arithmetic, Multiliction Slide 7

48 Comring High- nd Low-Rdi Multiliers AT = O(k log b + bk log k) AT = O((k /b) log b) Low-Cost b = O() High Seed b = O(k) AT- or AT - Otiml AT O(k ) O(k log k) O(k / ) AT O(k ) O(k log k) O(k ) Intermedite designs do not yield better AT or AT vlues; The multiliers remin symtoticlly subotiml for ny b By the AT mesure (indictor of cost-effectiveness), slower rdi- multiliers re better thn high-rdi or tree multiliers Thus, when n liction requires mny indeendent multilictions, it is more cost-effective to use lrge number of slower multiliers High-rdi multilier ltency cn be reduced from O((k/b) log b + log k) to O(k/b + log k) through more effective ielining (Chter ) Ar. Comuter Arithmetic, Multiliction Slide 8

49 Tree nd Arry Multiliers Chter Gols Study the design of multiliers for highest ossible erformnce (seed, throughut) Chter Highlights Tree multilier = reduction tree + redundnt-to-binry converter Avoiding full sign etension in multilying signed numbers Arry multilier = one-sided reduction tree + rile-crry dder Ar. Comuter Arithmetic, Multiliction Slide 9

50 Tree nd Arry Multiliers: Toics Toics in This Chter.. Full-Tree Multiliers.. Alterntive Reduction Trees.. Tree Multiliers for Signed Numbers.. Prtil-Tree nd Truncted Multiliers.5. Arry Multiliers.6. Pielined Tree nd Arry Multiliers Ar. Comuter Arithmetic, Multiliction Slide 5

51 Adder Net multile. Full-Tree Multiliers Severl multiles... Smll CSA tree All multiles... Full CSA tree Multile- Forming Circuits Multilier... Prtil roduct Prtil roduct... Bsic binry Seed u Adder High-rdi or rtil tree Economize Adder Full tree Fig.. High-rdi multiliers s intermedite between sequentil rdi- nd full-tree multiliers. Redundnt result Prtil-Products Reduction Tree (Multi-Oernd Addition Tree) Redundnt-to-Binry Converter Higher-order roduct bits Some lower-order roduct bits re generted directly Fig.. Generl structure of full-tree multilier. Ar. Comuter Arithmetic, Multiliction Slide 5

52 Full-Tree versus Prtil-Tree Multilier All rtil roducts... Lrge tree of crry-sve dders Severl rtil roducts... Smll tree of crry-sve dders Adder Logdeth Logdeth Adder Product Product Schemtic digrms for full-tree nd rtil-tree multiliers. Ar. Comuter Arithmetic, Multiliction Slide 5

53 Vritions in Full-Tree Multilier Design Designs re distinguished by vritions in three elements:. Multile-forming circuits Multile- Forming Circuits... Multilier.... Prtil roducts reduction tree Prtil-Products Reduction Tree (Multi-Oernd Addition Tree). Redundnt-to-binry converter Redundnt result Redundnt-to-Binry Converter Higher-order roduct bits Fig.. Some lower-order roduct bits re generted directly Ar. Comuter Arithmetic, Multiliction Slide 5

54 Emle of Vritions in CSA Tree Design Wllce Multilicnd Tree (5 FAs Multilier + HAs + -Bit Adder) Prtil roducts bit-mtri FA FA FA HA Product FA HA FA HA Bit Adder Ddd Tree ( FAs + HAs + 6-Bit Adder) FA FA FA HA HA FA Bit Adder Fig.. Two different binry tree multiliers. Ar. Comuter Arithmetic, Multiliction Slide 5

55 Detils of CSA Tree Fig.. Possible CSA tree for 7 7 tree multilier. [, 6] [, 6] [, 7] 7-bit CSA [, 8] [, 8] [,8] [5, ] [, 9] [, ] 7-bit CSA [6, ] [5, ] [, ] 7-bit CSA [, ] [6, ] CSA trees re quite irregulr, cusing some difficulties in VLSI reliztion Thus, our motivtion to emine lternte methods for rtil roducts reduction The inde ir [i, j] mens tht bit ositions from i u to j re involved. [, 8] 7-bit CSA [,9] [,] [,] -bit CSA [,] [,] [,] -bit CPA Ignore [, ] Ar. Comuter Arithmetic, Multiliction Slide 55

56 . Alterntive Reduction Trees FA FA FA FA Inuts FA Level Level- crries FA + ψ = ψ + Therefore, ψ = 8 crries re needed Fig.. A slice of blnced-dely tree for inuts. FA FA FA FA FA FA Level- crries Level- crries Level- crry FA FA FA FA FA Level Level Level Oututs FA Level 5 Ar. Comuter Arithmetic, Multiliction Slide 56

57 Binry Tree of -to- Reduction Modules -to- -to- -to- -to- -to- comressor -to- -to- FA -to- () Binry tree of (; )-counters FA c s (b) Reliztion with FAs c s (c) A fster reliztion Fig..5 Tree multilier with more regulr structure bsed on -to- reduction modules. Due to its recursive structure, binry tree is more regulr thn -to- reduction tree when lid out in VLSI Ar. Comuter Arithmetic, Multiliction Slide 57

58 Emle Multilier with -to- Reduction Tree Even if -to- reduction is imlemented using two CSA levels, design regulrity otentilly mkes u for the lrger number of logic levels Similrly, using Booth s recoding my not yield ny dvntge, becuse it introduces irregulrity Multile genertion circuits Redundnt-to-binry converter M u l t i l i c n d... M u l t i l e s e l e c t i o n s i g n l s Fig..6 Lyout of rtil-roducts reduction tree comosed of -to- reduction modules. Ech solid rrow reresents two numbers. Ar. Comuter Arithmetic, Multiliction Slide 58

59 . Tree Multiliers for Signed Numbers Etended ositions Sign Mgnitude ositions k k k k k k k k k... y k y k y k y k y k y k y k y k y k... z z z z z z z z z... k k k k k k k k k α β γ From Fig. 8.9 Sign etension in multioernd ddition. α β γ Sign etensions α β γ α β γ α β γ α β γ α β α Signs The difference in multiliction is the shifting sign ositions Five redundnt coies removed FA FA FA FA FA αβγ FA Fig..7 Shring of full dders to reduce the CSA width in signed tree multilier. Ar. Comuter Arithmetic, Multiliction Slide 59

60 Using the Negtive-Weight Proerty of the Sign Bit Sign etension is wy of converting negtively weighted bits (negbits) to ositively weighted bits (osibits) to fcilitte reduction, but there re other methods of ccomlishing the sme without introducing lot of etr bits Bugh nd Wooley hve contributed two such methods Fig..8 Bugh-Wooley s-comlement multiliction Unsigned b. 's-comlement c. Bugh-Wooley d. Modified B-W Ar. Comuter Arithmetic, Multiliction Slide 6

61 Fig The Bugh-Wooley Method nd Its Modified Form = ( ) = In net column = ( ) = ( ) ( ) In net column c. Bugh-Wooley d. Modified B-W Ar. Comuter Arithmetic, Multiliction Slide 6

62 Alternte Views of the Bugh-Wooley Methods Unsigned b. 's-comlement c. Bugh-Wooley d. Modified B-W Ar. Comuter Arithmetic, Multiliction Slide 6

63 . Prtil-Tree nd Truncted Multiliers High-rdi versus rtil-tree multiliers: The difference is quntittive, not qulittive For smll h, sy 8 bits, we view the multilier of Fig..9 s high-rdi h inuts... CSA Tree Uer rt of the cumultive rtil roduct (stored-crry) When h is significnt frction of k, sy k/ or k/, then we tend to view it s rtil-tree multilier Better design through ielining to be covered in Section.6 Sum Crry Adder FF h-bit Adder Fig..9 Generl structure of rtil-tree multilier. Lower rt of the cumultive rtil roduct Ar. Comuter Arithmetic, Multiliction Slide 6

64 Why Truncted Multiliers? Nerly hlf of the hrdwre in rry/tree multiliers is there to get the lst bit right ( dot = one FPGA cell) ul. k-by-k frctionl. multiliction M error = 8/ + 7/ + 6/8 + 5/6 + / + /6 + /8 + /56 = 7. ul Men error =.75 ul Fig.. The ide of truncted multilier with 8-bit frctionl oernds. Ar. Comuter Arithmetic, Multiliction Slide 6

65 Truncted Multiliers with Error Comenstion We cn introduce dditionl dots on the left-hnd side to comenste for the removl of dots from the right-hnd side Constnt comenstion Vrible comenstion. o o o o o o o. o o o o o o o. o o o o o o. o o o o o o. o o o o o. o o o o o. o o o o. o o o o. o o o. o o o. o o. o o. o. - o.. y - Constnt nd vrible error comenstion for truncted multiliers. M error = + ul M error ul Men error =? ul M error = +? ul M error? ul Men error =? ul Ar. Comuter Arithmetic, Multiliction Slide 65

66 .5 Arry Multiliers CSA CSA Rile-Crry Adder CSA CSA Fig.. A bsic rry multilier uses one-sided CSA tree nd rile-crry dder Fig.. Detils of 5 5 rry multilier using FA blocks. Ar. Comuter Arithmetic, Multiliction Slide 66

67 Signed ( s-comlement) Arry Multilier Fig.. Modifictions in 5 5 rry multilier to del with s-comlement inuts using the Bugh-Wooley method or to shorten the criticl th Ar. Comuter Arithmetic, Multiliction Slide 67

68 Arry Multilier Built of Modified Full-Adder Cells Fig.. Design of 5 5 rry multilier with two dditive inuts nd full-dder blocks tht include AND gtes. FA Ar. Comuter Arithmetic, Multiliction Slide 68

69 Arry Multilier without Finl Crry-Progte Adder Fig..5 Concetul view of modified rry multilier tht does not need finl crry-rogte dder.... Mu Fig..6 Crry-sve ddition, erformed in level i, etends the conditionlly comuted bits of the finl roduct. i i i+ i Mu i i+ Mu... B i B i+ Level i i Conditionl bits B i Dots in row i k Mu k k i + Conditionl bits of the finl roduct B i+ Dots in row i + [k, k ] k i+ i i All remining bits of the finl roduct roduced only gte levels fter k Ar. Comuter Arithmetic, Multiliction Slide 69

70 .6 Pielined Tree nd Arry Multiliers h inuts... CSA Tree Uer rt of the cumultive rtil roduct (stored-crry) h inuts... Pielined CSA Tree Ltches Ltches Ltches (h + )-inut CSA tree CSA Ltch Sum CSA Crry Adder FF h-bit Adder Lower rt of the cumultive rtil roduct Sum Crry Adder FF h-bit Adder Lower rt of the cumultive rtil roduct Fig..9 Generl structure of rtil-tree multilier. Fig..7 Efficiently ielined rtil-tree multilier. Ar. Comuter Arithmetic, Multiliction Slide 7

71 Pielined Arry Multiliers With ltches fter every FA level, the mimum throughut is chieved Ltches my be inserted fter every h FA levels for n intermedite design Emle: -stge ieline Fig..8 Pielined 5 5 rry multilier using ltched FA blocks. The smll shded boes re ltches. Ltched FA with AND gte Ltch Ar. Comuter Arithmetic, Multiliction Slide 7 FA FA FA FA

72 Vritions in Multiliers Chter Gols Lern dditionl methods for synthesizing fst multiliers s well s other tyes of multiliers (bit-seril, modulr, etc.) Chter Highlights Building multilier from smller units Performing multily-dd s one oertion Bit-seril nd (semi)systolic multiliers Using multilier for squring is wsteful Ar. Comuter Arithmetic, Multiliction Slide 7

73 Vritions in Multiliers: Toics Toics in This Chter. Divide-nd-Conquer Designs. Additive Multily Modules. Bit-Seril Multiliers. Modulr Multiliers.5 The Secil Cse of Squring.6 Combined Multily-Add Units Ar. Comuter Arithmetic, Multiliction Slide 7

74 . Divide-nd-Conquer Designs Building wide multilier from nrrower ones HH LH H L H L H L LL Rerrnged rtil roducts in b-by-b multiliction b bits b bits HH b bits H L LH LL Fig.. Divide-nd-conquer (recursive) strtegy for synthesizing b b multilier from b b multiliers. Ar. Comuter Arithmetic, Multiliction Slide 7

75 Generl Structure of Recursive Multilier b b b b b b use (; )-counters use (5; )-counters use (7; )-counters b b b b b b b b Fig.. Using b b multiliers to synthesize b b, b b, nd b b multiliers. Ar. Comuter Arithmetic, Multiliction Slide 75

76 Using b c, rther thn b b Building Blocks b b b b b b b b b c b c gb hc use b c multiliers nd (; )-counters use b c multiliers nd (5?; )-counters use b c multiliers nd (?; )-counters Ar. Comuter Arithmetic, Multiliction Slide 76

77 Wide Multilier Built of Nrrow Multiliers nd Adders Fig.. Using multiliers nd -bit dders to synthesize n 8 8 multilier. H H L H H L L L [, 7] [, 7] [, ] [, 7] [, 7] [, ] [, ] [, ] Multily Multily Multily Multily [,5] [8,] [8,] [, 7] [8,] [, 7] [, 7] [, ] 8 Add [, 7] Add [8,] 8 Add [, 7] Add [8,] Add [,5] [,5] [8,] [, 7] [, ] Ar. Comuter Arithmetic, Multiliction Slide 77

78 Krtsub Multiliction b b multiliction requires four b b multilictions: ( b H + L ) ( b H + L ) = b H H + b ( H L + L H ) + L L Krtsub noted tht one of the four multilictions cn be removed t the eense of introducing few dditions: ( b H + L ) ( b H + L ) = b bits b H H + b [( H + L ) ( H + L ) H H L L ] + L L H L Mult Mult Mult H L Benefit is quite significnt for etremely wide oernds Ar. Comuter Arithmetic, Multiliction Slide 78

79 . Additive Multily Modules y z y z = + y + z -bit dder c in () Block digrm (b) Dot nottion Fig.. Additive multily module with multilier () lus -bit nd -bit dditive inuts (y nd z). b c AMM b-bit nd c-bit multilictive inuts b-bit nd c-bit dditive inuts (b + c)-bit outut ( b ) ( c ) + ( b ) + ( c ) = b+c Ar. Comuter Arithmetic, Multiliction Slide 79

80 Multilier Built of AMMs Legend: bits [, ] bits [, ] Understnding [, ] [, 5] * * * [, ] [, ] [, 7] [, ] [, ] [6, 9] [, 5] * [,7] [, ] [, 5] [, 7] [, ] [,5] [8, ] [6, 7] [6, 9] [, 7] [, 7] [,] [,5] [8, 9] [,] [, ] [, 5] [8, 9] [6, 7] * * [,] [8, 9] [8, ] [6, 7] [,5] [6, 7] [, ] [, ] [6, 7] Fig..5 An 8 8 multilier built of AMMs. Inuts mrked with n sterisk crry s. n 8 8 multilier built of AMMs using dot nottion Ar. Comuter Arithmetic, Multiliction Slide 8

81 * Multilier Built of AMMs: Alternte Design [, 7] [,] * * * [, ] [, ] This design is more regulr thn tht in Fig..5 nd is esily endble to lrger configurtions; its ltency, however, is greter * [, 5] * [6, 7] [,5] Legend: bits bits [,] [, ] [, ] [,5] [6, 7] [8, 9] Fig..6 Alternte 8 8 multilier design bsed on AMMs. Inuts mrked with n sterisk crry s. Ar. Comuter Arithmetic, Multiliction Slide 8

82 . Bit-Seril Multiliers Bit-seril dder (LSB first) y y y FF FA s s s Bit-seril multilier (Must follow the k-bit inuts with k s; lterntively, view the roduct s being only k bits wide)? Wht goes inside the bo to mke bit-seril multilier? Cn the circuit be designed to suort high clock rte? Ar. Comuter Arithmetic, Multiliction Slide 8

83 Semisystolic Seril-Prllel Multilier Multilicnd (rllel in) Multilier (seril in) LSB-first Crry FA Sum FA FA FA Product (seril out) Fig..7 Semi-systolic circuit for multiliction in 8 clock cycles. This is clled semisystolic becuse it hs lrge signl fn-out of k (k-wy brodcsting) nd long wire snning ll k ositions Ar. Comuter Arithmetic, Multiliction Slide 8

84 Systolic Retiming s Design Tool A semisystolic circuit cn be converted to systolic circuit vi retiming, which involves dvncing nd retrding signls by mens of dely removl nd dely insertion in such wy tht the reltive timings of vrious rts re unffected Cut CL CR CL C R g h e f +d g d h d e+d f+d d Originl delys d Adjusted delys +d Fig..8 Emle of retiming by delying the inuts to C L nd dvncing the oututs from C L by d units Ar. Comuter Arithmetic, Multiliction Slide 8

85 Alternte Elntion of Systolic Retiming t t t+d d t t + d d t++d +d t++d d t++d +d Trnsferring dely from the oututs of subsystem to its inuts does not chnge the behvior of the overll system Ar. Comuter Arithmetic, Multiliction Slide 85

86 A First Attemt t Retiming Crry Multilicnd (rllel in) FA Sum FA FA FA Multilier (seril in) LSB-first Product (seril out) Fig..7 Multilicnd (rllel in) Multilier (seril in) LSB-first Crry FA Sum FA FA FA Product (seril out) Cut Cut Cut Fig..9 A retimed version of our semi-systolic multilier. Ar. Comuter Arithmetic, Multiliction Slide 86

87 Deriving Fully Systolic Multilier Crry Multilicnd (rllel in) FA Sum FA FA FA Multilier (seril in) LSB-first Product (seril out) Fig..7 Multilicnd (rllel in) Multilier (seril in) LSB-first Crry FA Sum FA FA FA Product (seril out) Fig.. Systolic circuit for multiliction in 5 cycles. Ar. Comuter Arithmetic, Multiliction Slide 87

88 t out A Direct Design for Bit-Seril Multilier (i ) i i t in i i (i - ) (i - ) c out s in (5; )-counter Fig.. Building block for ltency-free bit-seril multilier. i i Mu c s in out i i i (i - ) i (i - ) Alredy outut () Structure of the bit-mtri Alredy ccumulted into three numbers Fig.. The cellulr structure of the bit-seril multilier bsed on the cell in Fig... t c s out out in s t in c in out i i LSB i i i (i - ) (b) Reduction fter ech inut bit Fig.. Bit-seril multilier design in dot nottion. i i (i ) (i - ) (i - ) Shift right to obtin (i ) Ar. Comuter Arithmetic, Multiliction Slide 88

89 . Modulr Multiliers FA FA... FA FA FA Fig.. Modulo-( b ) crry-sve dder. Mod-5 CSA Divide by 6 Mod-5 CSA Fig..5 Design of modulo-5 multilier. Mod-5 CPA Ar. Comuter Arithmetic, Multiliction Slide 89

90 Other Emles of Modulr Multiliction Fig..6 One wy to design of modulo- multilier. Address n inuts... Tble... CSA Tree Dt Fig..7 A method for modulr multioernd ddition. -inut Modulo-m Adder sum mod m Ar. Comuter Arithmetic, Multiliction Slide 9

91 .5 The Secil Cse of Squring Multily by Simlify 8 _ Fig..8 Design of 5-bit squrer. Ar. Comuter Arithmetic, Multiliction Slide 9

92 Divide-nd-Conquer Squrers Building wide squrers from nrrower ones H HH H H LL L L LH H L L L Rerrnged rtil roducts in b-by-b multiliction b bits b bits H HH b bits H L L LH L LL Divide-nd-conquer (recursive) strtegy for synthesizing b b squrer from b b squrers nd multilier. Ar. Comuter Arithmetic, Multiliction Slide 9

93 .6 Combined Multily-Add Units () (b) (c) (d) } } } } Additive inut CSA-tree outut Crry-sve dditive inut CSA-tree outut Additive inut Dot mtri for the multiliction Crry-sve dditive inut Dot mtri for the multiliction Multily-dd versus multily-ccumulte Multily-ccumulte units often hve wider dditive inuts Fig..9 Dot-nottion reresenttions of vrious methods for erforming multily-dd oertion in hrdwre. Ar. Comuter Arithmetic, Multiliction Slide 9