Stack Manipulation. Other Issues. How about larger constants? Frame Pointer. PowerPC. Alternative Architectures

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1 Other Issues Stck Mnipultion support for procedures (Refer to section 3.6), stcks, frmes, recursion mnipulting strings nd pointers linkers, loders, memory lyout Interrupts, exceptions, system clls nd conventions Register use convention Register $9 is used s stck pointer Stck grows from high ddress to low ddress Stck pointer should point to the lst filled ddress Once entries re removed, stck pointer should e djusted Nme Register numer Usge $zero the constnt vlue $v-$v -3 vlues for results nd expression evlution $-$3 4-7 rguments $t-$t7 8-5 temporries $s-$s7 6-3 sved $t8-$t9 4-5 more temporries $gp 8 glol pointer $sp 9 stck pointer $fp 3 frme pointer $r 3 return ddress Frme Pointer How out lrger constnts? Stores the lst ddress for the lst frme When completing suroutine, frme ddress cn e used s the strting stck pointer vlue We'd like to e le to lod it constnt into register Must use two instructions, new "lod upper immedite" instruction lui $t, filled with zeros Then must get the lower order its right, i.e., ori $t, $t, ori 3 4 Alterntive Architectures PowerPC Design lterntive: provide more powerful opertions gol is to reduce numer of instructions executed dnger is slower cycle time nd/or higher CPI Sometimes referred to s RISC vs. CISC virtully ll new instruction sets since 98 hve een RISC VAX: minimize code size, mke ssemly lnguge esy instructions from to 54 ytes long! We ll look t PowerPC nd 8x86 Indexed ddressing exmple: lw $t,$+$s3 #$t=memory[$+$s3] Wht do we hve to do in MIPS? Updte ddressing updte register s prt of lod (for mrching through rrys) exmple: lwu $t,4($s3) #$t=memory[$s3+4];$s3=$s3+4 Wht do we hve to do in MIPS? Others: lod multiple/store multiple specil counter register c Loop decrement counter, if not goto loop 5 6

2 8x86 A dominnt rchitecture: 8x86 978: The Intel 886 is nnounced (6 it rchitecture) 98: The 887 floting point coprocessor is dded 98: The 886 increses ddress spce to 4 its, +instructions 985: The 8386 extends to its, new ddressing modes : The 8486, Pentium, Pentium Pro dd few instructions (mostly designed for higher performnce) 997: MMX is dded This history illustrtes the impct of the golden hndcuffs of comptiility dding new fetures s someone might dd clothing to pcked g n rchitecture tht is difficult to explin nd impossile to love Complexity: Instructions from to 7 ytes long one opernd must ct s oth source nd destintion one opernd cn come from memory complex ddressing modes e.g., se or scled index with 8 or it displcement Sving grce: the most frequently used instructions re not too difficult to uild compilers void the portions of the rchitecture tht re slow wht the 8x86 lcks in style is mde up in quntity, mking it eutiful from the right perspective 7 8 Registers in 8xY86 Architecture Exmples of non- rithmetic instructions 9 Instruction Encoding Summry Instruction complexity is only one vrile lower instruction count vs. higher CPI / lower clock rte Design Principles: simplicity fvors regulrity smller is fster good design demnds compromise mke the common cse fst Instruction set rchitecture very importnt strction indeed!

3 Arithmetic Numers Where we've een: Performnce (seconds, cycles, instructions) Astrctions: Instruction Set Architecture Assemly Lnguge nd Mchine Lnguge Wht's up hed: Implementing the Architecture opertion ALU result Bits re just its (no inherent mening) conventions define reltionship etween its nd numers Binry numers (se )... deciml:... n - Of course it gets more complicted: numers re finite (overflow) frctions nd rel numers negtive numers e.g., no MIPS sui instruction; ddi cn dd negtive numer) How do we represent negtive numers? i.e., which it ptterns will represent which numers? 3 4 Possile Representtions MIPS Sign Mgnitude: One's Complement Two's Complement = + = + = + = + = + = + = + = + = + = +3 = +3 = +3 = - = -3 = -4 = - = - = -3 = - = - = - = -3 = - = - Issues: lnce, numer of zeros, ese of opertions Which one is est? Why? it signed numers: two = ten two = + ten two = + ten... two = +,47,483,646 ten two = +,47,483,647 ten two =,47,483,648 ten two =,47,483,647 ten two =,47,483,646 ten... two = 3 ten two = ten two = ten mxint minint 5 6 Two's Complement Opertions Addition & Sutrction Negting two's complement numer: invert ll its nd dd rememer: negte nd invert re quite different! Converting n it numers into numers with more thn n its: MIPS 6 it immedite gets converted to its for rithmetic copy the most significnt it (the sign it) into the other its -> -> "sign extension" (lu vs. l) Just like in grde school (crry/orrow s) Two's complement opertions esy sutrction using ddition of negtive numers + Overflow (result too lrge for finite computer word): e.g., dding two n-it numers does not yield n n-it numer + note tht overflow term is somewht misleding, it does not men crry overflowed 7 8

4 One- Bit Adder Adder Boolen Alger Tkes three input its nd genertes two output its Multiple its cn e cscded A B CI CO S C = A.B + A.CI+ B.CI S = A.B.CI + A.B.CI+A.B.CI +A.B.CI 9 Detecting Overflow Effects of Overflow No overflow when dding positive nd negtive numer No overflow when signs re the sme for sutrction Overflow occurs when the vlue ffects the sign: overflow when dding two positives yields negtive or, dding two negtives gives positive or, sutrct negtive from positive nd get negtive or, sutrct positive from negtive nd get positive Consider the opertions A + B, nd A B Cn overflow occur if B is? Cn overflow occur if A is? An exception (interrupt) occurs Control jumps to predefined ddress for exception Interrupted ddress is sved for possile resumption Detils sed on softwre system / lnguge exmple: flight control vs. homework ssignment Don't lwys wnt to detect overflow new MIPS instructions: ddu, ddiu, suu note: ddiu still sign-extends! note: sltu, sltiu for unsigned comprisons Rel Design An ALU (rithmetic logic unit) A B C D E F D = A + B + C E = A.B.C + A.B.C + A.B.C F = A.B.C Let's uild n ALU to support the ndi nd ori instructions we'll just uild it ALU, nd use of them opertion op res result Possile Implementtion (sum-of-products): 3 4

5 Different Implementtions Building it ALU Opertion Not esy to decide the est wy to uild something Don't wnt too mny inputs to single gte Don t wnt to hve to go through too mny gtes for our purposes, ese of comprehension is importnt Opertion ALU Result Let's look t -it ALU for ddition: Result ALU Result Sum c out = + c in + c in sum = xor xor c in ALU Result How could we uild -it ALU for dd, nd, nd or? How could we uild -it ALU? ALU3 Result3 6 Wht out sutrction ( )? Tiloring the ALU to the MIPS Two's complement pproch: just negte nd dd. How do we negte? A very clever solution: Binvert Opertion Need to support the set-on-less-thn instruction (slt) rememer: slt is n rithmetic instruction produces if rs < rt nd otherwise use sutrction: (-) < implies < Need to support test for equlity (eq $t5, $t6, $t7) use sutrction: (-) = implies = Result 7 8 Supporting slt Test for equlity Cn we figure out the ide? Notice control lines: = nd = or = dd = sutrct = slt Bnegte ALU ALU Result Result Opertion Zero Note: zero is when the result is zero! ALU Result 3 3 ALU3 Result3 Set Overflow 9 3