Address/Data Control. Port latch. Multiplexer

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1 4.1 I/O PORT OPERATION As discussed in chpter 1, ll four ports of the 8051 re bi-directionl. Ech port consists of ltch (Specil Function Registers P0, P1, P2, nd P3), n output driver, nd n input buffer. Port 0 (pins 32-39) The output driver nd the input buffer of Port 0 re used to ccess externl memory. For this purpose, Port 0 sends out the low byte of the externl memory ddress, which is time-multiplexed with the dt byte tht is being written or red. The schemtic below gives the functionl digrm of typicl bit within Port 0. It shows the port bit ltch nd I/O buffer. The bit ltch is like D-type flip-flop, which will clock vlue from the internl bus in response to write to ltch signl from the CPU. The Q output of the ltch is plced on the internl bus in response to red ltch signl from the CPU. The level of the port pin itself is plced on the internl bus in response to red pin signl from the CPU. To use the port bit s n input the port bit ltch must contin 1 to turn off the output driver FET. It is therefore necessry to ensure tht logic 1 is written to the ltch of ny port bit tht is to be used s n input. This requirement pplies not just to Port 0, but lso to the remining three ports. I n t e r n l D t Internl red ltch Write to ltch D Q Port ltch Q Address/Dt Control Multiplexer V CC Port Pin B u s Internl red pin Note tht there is no internl pull-up resistor connected to the port pin. To use the pins of port 0 s both input nd output ports, ech pin must be connected externlly to 10K ohm pull-up resistor. With externl pull-up resistors connected upon reset, port 0 is configured s n output port. V CC 10K P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 Port 0 with externl pull-up resistors 4-1

2 Port 1 (pins 1-8) Port 1 is generl-purpose bi-directionl I/O port. The pins in this port hve no lternte functions. Port 2 (pins 21-28) The output drivers of Port 2 re used to ccess externl memory. Port 2 sends out the high byte of the ddress if it is 16-bit wide. Otherwise, the Port 2 pins continue to send out the P2 Specil Function Register content. Port 3 (pins 10-17) All of the Port 3 pins re multi-functionl. They re not only I/O port pins, but lso serve the functions of the vrious fetures. (Plese refer to chpter 1) The following schemtic gives the port bit structure for Port 1, Port 2, nd Port 3. Notice tht for Port 2 we hve omitted the multiplexer, which switches the port bit to send out ddress informtion when Port 2 is used s n ddress bus. V CC I n t e r n l D t Internl red ltch Write to ltch Internl pull-up resistor D Q Port ltch Port Pin B u s Internl red pin When reset occurs ll the port ltches in the 8051 hve 1 s written to them. If 0 is subsequently written to port ltch, it cn be reconfigured s n input by writing 1 to it. Progrmming the I/O Port Tsk #1: Write progrm to toggle every bit of P1 continuously (# B # B) BACK: MOV A, #55H MOV P1, A MOV A, #0AAH MOV P1, A SJMP BACK BACK: MOV P1, #55H MOV P1, #0AAH SJMP BACK MOV P1, #55H BACK: XLR P1, #0FFH SJMP BACK Red-modify-write 4-2

3 Tsk #2: Write progrm to toggle bit 2 of P1 continuously (#XXXXX0XXB #XXXXX1XXB) BACK: SETB P1.2 CLR P1.2 SJMP BACK BACK: CPL P1.2 SJMP BACK Tsk #3: Write progrm to configure port 0 s n input port, nd then dt is received from tht port nd sent to P1. MOV MOV BACK: MOV MOV SJMP A, #0FFH P0, A A, P0 P1, A BACK MOV MOV BACK: MOV SJMP A, #0FFH P0, A P1, P0 BACK 4.2 TIMER OPERATION The 8051 hs two on-chip 16-bit timers. These cn be configured to work either s timers or s counters. Timer When operting s timer the timer s register increments by one for every mchine-cycle. We my therefore think of it s counting mchine cycles. Since one mchine-cycle consists of twelve (12) oscilltor periods the count rte is one-twelve (1/12) of the oscilltor frequency. Counter In the counter mode the timer s register is incremented in response to 1 -to- 0 trnsition in its corresponding externl input pin T0 for Timer 0 nd T1 for Timer 1. In this mode the CPU smples the externl input during Phse 2 of Stte 5 (or in short S5P2) of every mchine cycle. When the CPU detects tht the input pin is high in one cycle nd low in the following cycle, it increments the count. The new count ppers in the timer register during Phse 1 of Stte 3 (S3P1) of the cycle following the one in which the trnsition ws detected. Since it tkes two (2) mchine cycles (or 24 oscilltor clock periods) to recognise 1 - to- 0 trnsition the mximum count rte is one twenty-fourth (1/24) of the oscilltor frequency. There is no restriction on the duty-cycle of the externl input signl. However, to ensure tht given level is smpled t lest once before it chnges, it should be held for minimum of one full mchine cycle. Mchine cycle 1 Mchine cycle 2 Mchine cycle 3 Stte 1 Stte 2 Stte 3 Stte 4 Stte 5 Stte 6 Stte 1 Stte 2 Stte 3 Stte 4 Stte 5 Stte 6 Stte 1 Stte 2 Stte 3 Stte 4 Externl Clock Pulse 1 0 Counter

4 The digrm below shows the timer/counter configurtions. Controlled by Counter / Timer (C / T) System clock Divide by 12 Tx Pin TLx THx Timer flg (TFx) TRx bit in TCON Gte bit in TMOD Mode 0 nd 1 configurtion Mode 2 configurtion INTx Pin TLx Note: x denotes the timer being used, i.e. x = 0 or 1 8 bits 8 bits Lod THx Timer Specil Function Registers TMOD We cn progrm the timer to work in one of four modes. We do these selections through the Timer/Counter Mode Control Register (TMOD) of the timer/counter, which is one of the specil function registers. Note tht this register is not bit ddressble. The digrm below shows the formt of the Mode Control Register. Timer 1 Timer 0 MSB LSB GATE C / T M1 M0 GATE C / T M1 M0 Bit Nme GATE C / T Function Gting control bit. GATE = 1 GATE = 0 Timer / Counter select bit. C / T = 0 C / T = 1 Timer/Counter x is enbled only if INTx pin = 1 nd TRx control pin is set (hrdwre control). Timer x is enbled whenever TRx control bit is set (softwre control). Timer opertion. Counter opertion. M0, M1 Mode selection bits (see tble below). 4-4

5 M1 M0 Operting Mode 0 0 Mode 0: 13-bit Timer Mode. 8-bit Timer/Counter THx with TLx s 5-bit presclr. 0 1 Mode 1: 16-bit Timer Mode. 16-bit Timer/Counter THx nd TLx re cscded. No presclr. 1 0 Mode 2: 8-bit Auto-Relod. THx holds vlue which is to be reloded into TLx ech time it overflows. 1 1 Mode 3: Split Timer Mode. Timer 0 TL0 is n 8-bit timer controlled by Timer 0 control bits; TH0 is n 8-bit timer controlled by Timer 1 control bits. Timer 1 Stopped. Mode 0: Mode 1: Mode 2: Mode 3: In this mode the Timer High Byte (THx) is cscded with the lower five bytes of the Timer Low Byte (TLx) to form 13-bit register. The upper three bits of TLx is not used. As the counter rolls over from ll 1s to ll 0s it sets the timer interrupt (overflow) flg TFx. The counted input is switched to the timer when TRx = 1 nd either GATE = 0 or INTx = 1. This mode is generlly not used much nowdys. This is 16-bit timer mode. Its opertion is the sme s tht for Mode 0 except tht ll 16-bits of the timer register re used. The timer registers (TLx nd THx) my be written to or red t ny time by softwre. Mode 2 configures the timer register s n 8-bit counter (TLx) with utomtic relod. When TLx overflows it not only sets the interrupt (overflow) flg (TFx), but lso relods TLx with the contents of THx, which is pre-set by softwre. The relod leves the contents of THx unchnged. In this mode Timer 0 works s if it is two seprte 8-bit timers. TL0 uses Timer 0 control bits (GATE, C/ T, TR0, INT0, nd TF0). TH0 is locked into timer function (counting mchine cycles) nd tke over the use of TR1 nd TF1 from Timer 1. TH0 now controls Timer 1 s interrupt. Although Timer 1 is stopped by Mode 3, switching it into one of the other modes cn strt it. However Timer 1 overflowing will not ffect the overflow flg TF1, since it is now connected to TH0. The other specil function registers tht re used to control the opertion of the timer/counters re TH0, TL0, TH1, TL1, nd TCON. TCON TCON is the Timer/Counter Control Register which contins the sttus nd control bits for the two 8051 timers. It lso contins four bits tht re used for the control of externl interrupts. Note tht TCON is bit ddressble. The formt of the TCON is: MSB LSB TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 4-5

6 TCON: Timer/Counter Control Register Symbol Bit Lbel Nme nd Description TF1 TCON.7 Timer-1 overflow flg. Set by hrdwre on overflow. Clered by hrdwre when processor vectors to interrupt routine. TR1 TCON.6 Timer-1 run control bit. Set / clered by softwre to turn timer / counter on / off. TF0 TCON.5 Timer-0 overflow flg. Set by hrdwre on overflow. Clered by hrdwre when processor vectors to interrupt routine. TR0 TCON.4 Timer-0 run control bit. Set / clered by softwre to turn timer / counter on / off. IE1 TCON.3 Interrupt-1 Edge flg. Set by hrdwre when interrupt-1 flling edge is detected. Clered when interrupt is processed. IT1 TCON.2 Interrupt-1 Type control bit. Set / clered by softwre to specify flling edge / low level triggered externl interrupts. IE0 TCON.1 Interrupt-0 Edge flg. Set by hrdwre when interrupt-1 flling edge is detected. Clered when interrupt is processed. IT0 TCON.0 Interrupt-0 Type control bit. Set / clered by softwre to specify flling edge / low level triggered externl interrupts. Progrmming the timer/counter Tsk #1: Select the mode of opertion nd initilize the timer/counter if we wish to use Timer 0 s 16-bit counter, which counts clock pulses tht re externlly gted to the counter by INT0. Initiliztion entils writing the pproprite mode word to the mode control register (TMOD). The mode we need is mode 1 nd hence M0 = 1 nd M1 = 0. Since the clock source is internl we hve C/ T = 0, nd gted externlly so we hve GATE = 1. As we re not using Timer 1 we cn put 0 into ll it mode word bits. The mode control word is 09H s shown below. MSB The instruction tht lods the mode control register with the required mode word is MOV TMOD, #09H. The next word we need to write to the timer is the control word. We need to first ensure tht the time is off by writing 0 to TR0. Since TR0 is bit ddressble we cn simply use the instruction CLR TR0. Tsk #2: Write progrm using Timer 0 to output 10 khz squre wve on pin 0 of Port 1 (P1.0) A 10 khz squre wve hs equl mrk-to-spce rtio, i.e. it hs equl high nd low durtion of 50 µs. This time intervl is less thn 256 µs, we cn use mode 2 with uto-relod. Assuming n oscilltor clock of 12 MHz, ech count is 1 µs so tht we need totl of 50 counts less thn 00H, or 50. The progrm is s follows ORG XXXXH MOV TMOD, #02H ; mode 2, 8-bit uto-relod MOV TH0, #-50 ; put 50 relod vlue in TH0 SETB TR0 ; strt timer LOOP: JNB TF0, LOOP ; wit for overflow CLR TF0 ; cler timer overflow flg bit CPL P1.0 ; toggle Port 1.0 SJMP LOOP ; repet END LSB 0 1

7 4.3 SERIAL PORT OPERATION The 8051 hs seril port which supports single chnnel full-duplex seril communiction. The receive dt (RxD) nd trnsmit dt (TxD) signls of the seril port re the lternte functions of pins P3.0 nd P3.1 on Port 3. Note tht the seril signls provided by these pins re t TTL signl levels. To mke them comptible with RS232 stndrd for seril trnsmission we need to use suitble driver IC, such s the MAX233, to do the necessry level trnsltions. SCON & SBUF There re two specil function registers ssocited with the seril port. These re the seril port control nd sttus register (SCON) nd seril port buffer (SBUF). The seril port buffer (SBUF) is in fct physiclly two seprte registers the seril port trnsmit register nd receive register. Writing to SBUF lods the trnsmit register nd reding from SBUF ccesses the receive buffer. The receive register is receive-buffered, mening tht the seril port cn commence reception of second byte of dt before previously received byte hs been red from the receive register. However, if the first byte still hs not been red by the time the reception of the second byte is complete, one of the bytes will be lost. We cn select to operte the seril port in one of four modes Mode 0, Mode 1, Mode 2, nd Mode 3. To do so we write the pproprite word to the seril port control nd sttus register, SCON, t ddress 98H. This register is bit ddressble. The digrm nd tble below give the formt of this register nd the definition of the bits within the register. MSB LSB SM0 SM1 SM2 REN TB8 RB8 TI RI Symbol Bit Lbel Nme nd Description SM0 SCON.7 Seril mode selection bit 0. SM1 SCON.6 Seril mode selection bit 1. SM2 SCON.5 Seril mode selection bit 2. Enbles the multi-processor communiction feture in Mode 2 nd 3. In Mode 2 or 3, if SM2 = 1 the RI will not be ctivted if the received 9 th dt bit (RB8) = 0. In Mode 1, if SM2 = 1 the RI will not be ctivted if vlid stop bit ws not received. In Mode 0, SM2 should be 0. REN SCON.4 Enble seril reception. Set/cler by softwre to enble/disble reception. TB8 SCON.3 9 th dt bit trnsmitted in Mode 2 nd 3. Set/cler by softwre s desired. RB8 SCON.2 9 th dt bit received in Mode 2 nd 3. In Mode 1, if SM2 = 0 then RB8 is the received stop bit. In Mode 0, RB8 is not used. TI SCON.1 Trnsmit interrupt flg. Set by hrdwre t the end of the 8 th bit time in Mode 0, or t the beginning of the stop bit, in ny other modes, in seril trnsmission. Must be clered by softwre. RI SCON.0 Receive interrupt flg. Set by hrdwre t the end of the 8 th bit time in Mode 0, or hlfwy through the stop bit time in ny other modes, in ny seril reception (except see SM2). Must be clered by softwre. 4-7

8 The mode selection using SCON.7 nd SCON.6 is s follows: SM0 SM1 MODE Description Bud Rte Shift register Fixed (f osc /12) bit UART Vrible (set by timer) bit UART Fixed (f osc /32 or f osc /64) bit UART Vrible (set by timer) Mode 0: Mode 1: Mode 2: Mode 3: In this mode the port is operting in n 8-bit shift register mode. Seril dt enter nd go out through the RxD pin. The TxD pin outputs the shift clock. The bud rte is fixed t one-twelve of the oscilltor frequency. In this mode the port opertes s n 8-bit UART. Ten bits re trnsmitted through TxD or received through RxD. The ten bits comprise, strt bit ( 0 ), 8 dt bits (with the LSB first), nd stop bit ( 1 ). When received the stop bit goes into RB8 in the specil function register SCON. The bud rte for this mode is vrible. The port opertes s 9-bit UART in this mode. Eleven bits of dt re trnsmitted or received. The eleven bits re mde up of strt bit ( 0 ), 8 dt bits (LSB first), progrmmble 9 th dt bit, nd stop bit ( 1 ). On trnsmit the 9 th dt bit (TB8 in SCON) cn be ssigned vlue of 1 or 0. Alterntively, for exmple, the prity bit (P, in the PSW) cn be moved to TB8. On receive the 9 th dt bit goes into RB8 in SCON, while the stop bit is ignored. The bud rte is progrmmble to be f osc /12 or f osc /64. This mode is the sme s Mode 2 except tht the bud rte is progrmmble nd is provided by the timer. In ll four modes, we initite trnsmission by writing to the SBUF register. In Mode 0 we strt reception by setting the bits RI = 0, nd REN = 1. While in other modes, if REN = 1, reception will strt when n incoming strt bit is received. To prepre for seril reception we cn set REN = 1 t the beginning of progrm by either executing the instruction SETB REN, or lod SCON with mode word tht hs SCON.4 = 1, i.e. by executing the instruction MOV SCON, #XXX1XXXXB. Note tht the don t cre bits X re relly not don t cre bits s such here. They must be ppropritely chosen to set the mode of opertion we desire. Bud Rte Settings For The Seril Ports Mode 0 nd Mode 2 The bud rte in Mode 0 is fixed t f osc /12. The bud rte in Mode 2 depends on the vlue of the SMOD bit in the specil function register PCON (Power Control). It is given by Mode 2 bud rte = (2 SMOD /64) f osc. Thus if SMOD = 0 (defult upon RESET or power up) the Mode 2 bud rte = (1/64) f osc, nd if SMOD = 1 the Mode 2 bud rte = (1/32) f osc. Mode1 nd Mode 3 In the 8051, the bud rte is determined by the Timer 1 overflow rte nd the vlue of SMOD s follows: Mode 1 & 3 bud rte = (2 SMOD /32) x (Timer 1 Overflow Rte). The Timer 1 interrupt should be disbled for this ppliction. The Timer itself cn be set for either s timer or s counter opertion nd in ny of its 3 running modes. It is typicl in most pplictions to set it to timer opertion, in the uto-relod mode (the high nibble of TMOD = 0010B). In this cse the bud rte is given by: Mode 1 & 3 bud rte = 2 SMOD x 32 f osc. 12 x [256 - (TH1)] Note tht using 12 MHz crystl oscilltor we will incur n error in the bud rte generted in this wy. If exct bud rtes re required we hve to use MHz crystl. The tble below gives the commonly used bud rte generted with MHz crystl. 4-8

9 Bud Rte f osc SMOD Timer 1 C / T Mode Relod Vlue Mode 1,3:62.5K 12 MHz FFH 19, MHz FDH MHz FDH MHz FAH MHz F4H MHz E8H MHz DH MHz H MHz FEEBH Progrmming the Seril Port Tsk #1: Write the initiliztion for the seril port so tht it will operte in synchronous mode with 8-bit dt nd bud rte of The first thing we need to set is the seril port mode control word. For 8-bit synchronous communictions we need to operte in Mode 1, so we set SM0 = 0, SM1 = 1, SM2 = 0. To enble the receiver we hve REN = 1, nd to set the trnsmitter for trnsmission of the first chrcter we set TI = 1. Thus the seril port mode control word is 52H. Next we set mode control word for Timer 1 which is given by GATE = 0, C/ T= 0, M1 = 1, nd M0 = 0. We cn set ll bits for Timer 0 to 0. The required word is 20H. To find the required vlue tht we need to put into TH1 we need to use the expression given bove. Here we ssume, for simplicity, tht the crystl frequency of the microcontroller is MHz so tht for 9600 bud we need TH1 = FDH. The initiliztion segment is therefore: ORG XXXXH INIT: MOV SCON, #52H ; 8-bit syn, mode 1 MOV TMOD, #20H ; set Timer 1 to mode 2 MOV TH1, #0FDH ; 9600 bud rte SETB TR1 ; strt Timer 1 Tsk #2: Write subroutine clled OUTCHR to trnsmit the 7-bit ASCII code in the ccumultor out through the seril port, with odd prity dded s the 8 th bit. Return with the vlue in the ccumultor unchnged, i.e. with the prity bit removed. We obtin the prity of the ASCII code in the ccumultor by looking t the prity flg bit in the PSW. However, remember lthough the prity flg in the PSW reflects the number of 1s in the ccumultor fter every mchine cycle it is set differently. If the number of 1s is even, P = 0, nd if it is odd P = 1. In the prity 4-9

10 bit conventionlly 1 represents even prity nd 0 represents odd prity. Thus we need complement the prity flg bit before putting it into the most significnt bit of the ccumultor. The progrm for the trnsmission of the single chrcter is s follows: ORG XXXXH MAIN: ; min progrm OUTCHR: ; OUTCHR subroutine MOV C, P ; Get prity flg bit, CPL C ; convert, MOV ACC.7, C ; nd put in bit 7 of the ACC MOV SBUF, A ; sent new chrcter WAIT: JNB TI, WAIT ; hs lst chrcter been sent? CLR TI ; yes, cler flg CLR ACC.7 ; remove prity bit in ACC RET ; return to min progrm Tsk #3: Write progrm to trnsfer the messge YES serilly t 9600 bud, 8-bit dt, 1 stop bit. Do this continuously. ORG XXXXH INIT: MOV SCON, #50H ; 8-bit, 1 stop bit, REN enbled MOV TMOD, #20H ; set Timer 1 to mode 2 MOV TH1, #-3 ; 9600 bud rte SETB TR1 ; strt Timer 1 AGAIN: MOV A, # Y ; trnsfer Y ACALL TRANS MOV A, # E ; trnsfer E ACALL TRANS MOV A, # S ; trnsfer S ACALL TRANS SJMP AGAIN ; seril dt trnsfer subroutine TRANS: MOV SBUF, A ; sent new chrcter WAIT: JNB TI, $ ; hs lst chrcter been sent? CLR TI ; yes, cler flg RET ; return to min progrm 4-10

CoE3DJ4 Digital Systems Design. Chapter 5: Serial Port Operation

CoE3DJ4 Digital Systems Design Chapter 5: Serial Port Operation Serial port 8051 includes an on-chip serial port Hardware access to the port is through TXD and RXD (Port 3 bits 1 and 0) Serial port is