Enginner To Engineer Note

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1 Technicl Notes on using Anlog Devices DSP components nd development tools from the DSP Division Phone: (800) ANALOG-D, FAX: (781) , FTP: ftp.nlog.com Using n ADSP-2181 DSP s IO Spce to IDMA boot nother ADSP Contributed by J. O. Lst Modified 10/28/97 This ppliction note describes n exmple hrdwre nd softwre interfce between the Internl DAM (IDMA) port of the ADSP Additionlly, this ppliction note shows how host DSP cn boot trget DSP using the IDMA port. As ech specific system design hs it s own requirements nd chllenges, this ppliction note does not presume to provide the only possible solution. Rther, it is ment to provide the system designer flexible frmework of ides tht cn be tilored to meet individul system requirement. IDMA Opertion The host DSP cn gin ccess of the trget ADSP-2181 s internl memory through the trget s IDMA port. Any host processors ccessing the trget ADSP-2181 through IDMA cn tret the trget DSP s memory mpped slve peripherl, nd cn hve ccess to ll of the trget s internl Dt Memory (DM) nd Progrm memory (PM), excluding control registers. The dsp-2181 s IDMA port consists of 16 bit multiplexed ddress/dt bus (IAD15:0), select line (/IS), IDMA ddress ltch (IAL), red (/IRD), write (/IWR), nd cknowledge (/IACK) signls. The host DSP is responsible for inititing ll dt trnsfers. The trget DSP memory ddress is loded into the IDMA Address register (IDMAA). This register contins the 14 bit internl memory ddress, long with bit to specify the type of trnsfer: 24 bit Progrm Memory opcodes, or 16 bit Dt memory dt. The IDMAA register cn be initilized by either the trget DSP or by the host DSP. The host cn initilized this register by performing n ddress ltch cycle. An ddress ltch cycle is defined by the host sserting the IAL signl, nd then trnsferring 15 bit (14 ddress bits plus 1 destintion memory type bit) vlue on the IAD pins. To stremline the trnsfer of lrge segments of opcodes or dt, n Address Ltch Cycle does not need to be performed for ech IDMA ccess. Insted, once ltched, the ddress is utomticlly incremented fter every IDMA word trnsfer. As the IDMA port hs 16 bit bus, 24 bit trnsfers require two host ccesses. The first ccess trnsfers the most significnt 16 bits, the second ccess trnsfers the lest significnt 8 bits, right justified, with zero filled upper byte. IDMA ddress increments occur fter the entire 24 bit word hs been trnsferred for PM trnsfer, or fter the entire 16 bit dt word hs been trnsferred for DM trnsfer Booting the DSP The IDMA Port on the DSP cn be used to boot lod the DSP on power up. This elimintes the need for seprte EPROM for the DSP. On the ADSP-2181, booting is controlled through the use of the MMAP nd BMODE pins. Booting through the IDMA port is enbled by holding the MMAP pin low, nd the BMODE pin high. With this signl combintion, on RESET, the DSP does not ctivte its externl ddress bus to ccess n EPROM. Insted, the DSP expects host to begin IDMA trnsfers to fill its internl Dt nd Progrm memories. This process consists of the host performing stndrd IDMA instruction nd dt trnsfers. Booting is terminted when the DSP restrt vector t DSP Address PM(0x0000) is written. An efficient boot loding sequence would consist of the host filling the DSP s internl Progrm Memory strting t loction PM(0x0001), nd using the utomtic ddress increment feture on the IDMA port to speed the trnsfer of code block in scending ddress order. The host cn then initilize dt memory. When ll initiliztion is complete, the host should then initilize the DSP s restrt vector nd DSP progrm execution will commence.

2 Technicl Notes on using Anlog Devices DSP components nd development tools from the DSP Division Phone: (800) ANALOG-D, FAX: (781) , FTP: ftp.nlog.com Interfce Hrdwre Design The IDMA port of the trget DSP is mpped into two loctions in the host ADSP s IO spce. On loction is used by the host to ltch the ddress tht n IDMA write would trget. The other loction is used when trnsferring dt n instruction informtion. The trget DSP hs been configured for IDMA boot, the MMAP=0 nd the BMODE=1. Miniml logic is required to connect the externl bus of the host ADSP-2181 to the trget s IDMA port. The only externl logic tht is required is singulr or gte, which is used to ensure tht IAL nd /IWR re never sserted t the sme time. This is chieved by using the A) nd /WR lines from the host s inputs to n OR gte, whose output is then connected to /IWR on the trget DSP. A0, from the host, is connected to the ddress ltch signl, IAL, on the trget. This connection llows the host to commence n ddress ltch sequence by writing to n ddress tht contins bit 0 in the host memory. The write strobe, /IOMS, is connected to /IS, so tht ny write to the IO spce of the host will trigger the write strobe of the trget DSP s IDMA port. The 16 dt lines form the host s IO spce (D8-D23) re directly connected to the IAD dt bus on the trget ADSP The host will use this bus to trnsmit the DSP memory ddresses, s well s trnsfer dt to the DSP. Generting Boot Code The ADSP-21xx fmily opertes on 24- bit instruction opcodes. The IDMA port cn only ccept 16-bit vlues. To trnsfer instruction opcodes through the IDMA port, the most significnt 16 bits trnsferred first, followed by the lest significnt 8 bits, right justified. of the ADSP-2100 Fmily Assembler Tools & Simultor Mnul. Since the executble file contins 24 bit DSP opcodes, the file needs to be re-formtted to dhere to the IDMA port s 16 bit dt requirement. First, it is necessry to remove the plce holders nd formtting heders from the opcodes from the.exe file. The ADSP-2100-Fmily.EXE formt seprtes Progrm Memory nd Dt Memory segments on module-by-module bsis. The executble formt hs the following <---- Strt of PM RAM Module 0000 <---- Strting ddress <---- First Opcode 789bc <---- Second Opcode def012 <---- Third Opcode : : # <---- End-of-module <---- Strt of DM RAM segment 0000 <---- Strting ddress 1234 <---- First dt word 5679 <---- Second dt word : : : : # <---- End-of-module specifier After the plce holders hve been removed, the 24 bit opcodes need to be reformtted into 2 16 bit words. The first the 16 MSBs nd the second with the 8 LSBs with leding zeroes. Note, the usge of the PX register is gretly helpful for implementing this procedure, s seen in the ttched code. DSP Executble files re produced by the ADSP-21xx Fmily Linker. The Linker tkes object files generted by the Assembler nd C Compiler, plces them within the memory rchitecture defined by the system rchitecture file, nd genertes DSP executble (.EXE). A detiled description is vilble in Appendix B

3 Technicl Notes on using Anlog Devices DSP components nd development tools from the DSP Division Phone: (800) ANALOG-D, FAX: (781) , FTP: ftp.nlog.com TOPICS FOR FURTHER DISCUSSION Hrdwre Signling In mny instnces, it my be desirble for the host nd DSP processors to hve dditionl venues of communiction. The host cn use one of its progrmmble flgs s n output ttched to hrdwre interrupt on the DSP. With this method, the host cn lert the DSP prior to trnsfer, or inform the DSP tht trnsfer hs been completed. This cn be especilly useful becuse there is no interrupt ssocited with IDMA opertion on the ADSP The DSP cn likewise use progrmmble flg s n output to signl the host if there is new dt for the host to use, or if new code is required for downlod. Multiple DSP Processors In this ppliction note, we focused on connecting single ADSP-2181 to microprocessor. This scheme cn be expnded to multiple DSP processors without too much trouble. In multiple DSP system, ll IDMA lines except IS nd IACK cn be bussed together. Multiple IS lines re needed to select ech individul DSP processor, nd multiple IACK lines re needed to monitor the ctivity on ech individul DSP processor. Ech DSP processor needs two micro controller memory spce ddresses ssigned to it, nd tht ddress ssignment used to ssert the pproprite IS signl. Ech DSP processor cn then be ccessed individully. References ADSP-2100 Fmily User s Mnul, Third Edition (9/95), Anlog Devices, Inc. ADSP-2100 Fmily Assembler Tools & Simultor Mnul, Anlog Devices, Inc. ADSP-2100 Fmily EZ-Kit Lite Reference Mnul, Anlog Devices, Inc. /*This progrm trnsfer dt from mster ADSP-2181 to slve ADSP-2181 /*through the IDMA port.module/bs=0x0000 idm_trnsfer;.const length =68; {deciml length of vector}.var/pm/ram x_input[length];.init x_input: <xin.dt>; JUMP strt; NOP; NOP; NOP; {Interupt vector tble} {No interrupts used}

4 Technicl Notes on using Anlog Devices DSP components nd development tools from the DSP Division Phone: (800) ANALOG-D, FAX: (781) , FTP: ftp.nlog.com strt: AX0=0x0000; DM(0x3fff)=AX0; DM(0x3fe6)=AX0; DM(0X3FFE)=AX0; L6=0; I6=^x_input; M6=1; MODIFY(i6,m6); {Sys Control reg, PM wit sttes off} {PF control reg, ll PF inputs} {# of wit sttes for ddress 0-1ff} {length of the dt buffer} {strting point of dt to be trnsferred} {increment mount} {pointer init to 2nd vlue of vector} /***************ddress ltch to 0x0001 ************************************************* CALL check_ck; AX0=0x0001; IO(0x0001)=AX0; {check to see if trget is redy to receive} {strting ddress to write t in the slve} {writing to this ddress will toggle both the} {/IS nd IAL lines on the slve, dditionlly,} {this will send the ddress to be ltched} /***************write ll dt, strting t ddress 0x0001************************************ CNTR=length-1; {counter set to #words to be trnsmitted} DO loop1 UNTIL CE; CALL check_ck; {check to see if trget is redy to receive} CALL formt; {formt dt for trnsfer} IO(0x0100)=AY0; {/IWR nd IS sserted, the first 16 msb of} {dt re put onto IAD 0-15} CALL check_ck; {check to see if trget is redy to receive} IO(0x0100)=AY1; {/IWR nd IS sserted, 8 lsb of dt, right} {justified with leding zeros re put} {onto IAD 0-15} loop1: NOP; /***************ltch to ddress 0x0000************************************************* CALL check_ck; AX0=0x0000; IO(0x0001)=AX0; {check to see if trget is redy to receive} {strting ddress to write t in the slve} {writing to this ddress will toggle both the} {/IS nd IAL lines on the slve, dditionlly,} {this will send the ddress to be ltched} /***************write to ddress 0x0000************************************************* I6=^x_input; {point to beginning of dt buffer} CALL check_ck; {check to see if trget is redy to receive}

5 Technicl Notes on using Anlog Devices DSP components nd development tools from the DSP Division Phone: (800) ANALOG-D, FAX: (781) , FTP: ftp.nlog.com CALL formt; IO(0x0100)=AY0; CALL check_ck; IO(0x0100)=AY1; {formt dt for trnsfer} {/IWR nd IS sserted, the first 16 msb of} {dt re put onto IAD 0-15} {check to see if trget is redy to receive} {/IWR nd IS sserted, 8 lsb of dt, right} {justified with leding zeros re put} {onto IAD 0-15} idle; /*The "formt" subroutine pre-formts the 24 bit wide progrm memory dt into 16 bit wide dt. The /*16 most significnt bits re stored in AY0 nd the 8 lest significnt bits re stored in AY1, right /*justified with leding zeroes. formt: AY0=PM(I6,M6); {the 16 MSBs re stored in dt register AY0} AY1=PX; RTS; {the 8 LSBs re stored in dt register AY1} /*The "check_ck" subroutine checks to see if the /IACK line is low check_ck: AX0=dm(0x3fe5); {Poll PF1, which is connected to /IACK} AR=TSTBIT 1 of AX0; {corresponds to PF1} IF NE JUMP check_ck; {if not redy, check /IACK gin} RTS;.endmod;

6 Technicl Notes on using Anlog Devices DSP components nd development tools from the DSP Division Phone: (800) ANALOG-D, FAX: (781) , FTP: ftp.nlog.com SYSTEM BLOCK DIAGRAM /IOMS /IS ADSP-2181 Host A0 IAL ADSP-2181 Trget /WR OR /IWR D8-23 IAD0-15