Verilog Simulation & Debugging Tools
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1 Verilog Simulation & Debugging Tools Digital Circuit Lab TA: Po-Chen Wu
2 Outline Environment Setup NC-Verilog nlint nwave Verdi 2
3 Environment Setup 3
4 Login to the Linux Server Many EDA tools are provided only for the Linux OS. So we have to use software like PuTTY/PieTTY/MobaXterm on our local computer to login to the linux server and use the EDA tools on it. 4
5 NTUEE Linux Servers IC Design Lab (TA: 邱茂菱 ) Server list IP NAME TYPE CPU CPU CLOCK MEMORY OS cad16 IBM X3400 Intel Xeon GHz * G RHEL cad17 IBM X3550 Intel Xeon GHz * G RHEL cad42 IBM X3500 Intel Xeon 64 2 GHz * G CentOS 5 5
6 X Window System X Window System (X11, X, and sometimes informally X-Windows) is a windowing system for bitmap displays, common on UNIX-like (ex: Linux) operating systems. Microsoft Windows is not shipped with support for X, but many third-party implementations exist, as free and open source software such as Cygwin/X, and proprietary products such as Xming. 6
7 Introduction to MobaXterm (1/2) MobaXterm is free software that can be installed onto your local Windows or Mac computer which provides a graphical user interface and a command line shell for the server. Official Website 7
8 Introduction to MobaXterm (2/2) MobaXterm provides useful features for developers: Multitab terminal with embedded Unix commands (ls, cd,...). Embedded X11 server for easily exporting your Linux display. Passwords management for SSH, SFTP, etc (on demand password saving). 8
9 Session Settings Click the Session button and specify which session you want. Usually this will be SSH. For that click SSH
10
11 1 (double-click) 2 11
12 Command Line Shell We can also use the command line shell to login to the server. ssh [-p YYYYY] bxxxxx: your usesr name YYYYY: port number here -p 22 is redundant because 22 is the default port number. 12
13 Upload Files (1/2) Uploading files fom your local PC to the server Choose which file(s) to upload 13
14 Upload Files (2/2) Moving and copying files by using the dragand-drop
15 Download Files (1/2) Downloading files from the server to local PC Select directory 15
16 Download Files (2/2) Moving and copying files by using the dragand-drop
17 NC-Verilog 17
18 Introduction to NC-Verilog The Cadence NC-Verilog simulator is a Verilog digital logic simulator. We can use NC-Verilog to Compiles the Verilog source files. Elaborates the design and generates a simulation snapshot. Simulates the snapshot. 18
19 Before Using NC-Verilog Source the environment settings of CAD tools. source ~cvsd/cvsd.cshrc If you try entering the command "ncverilog" but it turns out "command not found," it means there's something wrong with the "*.cshrc" file or the software license is out of date. 19
20 Running Verilog (1/2) Run the Verilog simulation: ncverilog testbench.v exp2.rsa.v +access+r Another choice of running Verilog simulation: ncverilog -f exp2_rsa.f +access+r In exp2_rsa.f 20
21 Running Verilog (2/2) "+access+r" is added to enable waveform file dumping. In testbench.v, line 69~72 or *.fsdb has smaller file size than *.vcd. But $fsdbdumpfile cannot work without sourcing verdi.cshrc. 21
22 Simulation Results Check the simulation result to see if the Verilog design is finished correctly. 22
23 nlint 23
24 Introduction to nlint nlint is a comprehensive HDL design rule checker fully integrated with the Debussy debugging system (Developed by SpringSoft). We can use nlint to check the coding style of our design and if it is synthesizable. 24
25 Before Using nlint Source the environment settings of CAD tools. source ~cvsd/verdi.cshrc To avoid the warning *WARN* Failed to check out license. occurs when starting nlint, please type the following command: setenv LM_LICENSE_FILE 25
26 Start nlint Type the following command: nlint -gui & The token "&" enable you to use the terminal while nlint is running in the background. Just ignore this warning. 26
27 Specify the Design File 1 27
28
29 Start Checking 1 29
30 Not all the warnings or errors are valuable. 30
31 nwave 31
32 Introduction to nwave nwave is one of the best waveform (*.vcd or *.fsdb) viewer. We can debug easily by checking the waveform file dumped during simulation. 32
33 Before Using nwave Source the environment settings of CAD tools. source ~cvsd/verdi.cshrc To avoid the Verdi warning window occurs, please type the following command: setenv LM_LICENSE_FILE 33
34 Start nwave Type the following command: nwave & Also, the token "&" enable you to use the terminal while Verdi is running in the background. Just ignore this warning. 34
35 Open the FSDB File 1 35
36
37 Choose Signals 1 37
38 1 2 Choose signals we are interested in
39 Browse the Whole Waveform 1 39
40 Browse the Specified Interval press & drag 40
41 41
42 Search for Specified Signal 4,5,
43 Jump to the cursor position (Used when we are lost) cursor position (Search by rising oe) 43
44 Change Sign Representation
45 Change Radix Representation
46 46
47 Change Signal Position 2 Press middle mouse button, drag and then drop. 1 47
48 48
49 Signal Aliasing
50 1 4 2 Note that signal aliasing is a strict one-toone correspondence so the value represented in the viewer must exactly represent what format your filter expects. (e.g., binary, hexadecimal)
51 51
52 Reload the Waveform Remember to reload the waveform whenever finishing another Verilog simulation. 1 52
53 Verdi 53
54 Introduction to Verdi The Verdi Automated Debug System is an advanced open platform for debugging digital designs with powerful technology that helps you: 1. Comprehend complex and unfamiliar design behavior. 2. Automate difficult and tedious debug processes. 3. Unify diverse and complicated design environments. 54
55 Basic Function (1/2) ntrace A source code viewer and analyzer that operates on the knowledge database (KDB) to display the design hierarchy and source code (Verilog, VHDL, SysmVerilog, SystemC, PSL, OVA, mixed) for selected design blocks. The main window of Verdi. 55
56 Basic Function (2/2) nwave A state-of-the-art graphical waveform viewer and analyzer that is fully integrated with Verdi's source code, schematic, and flow views. nschema A schematic viewer and analyzer that generates interactive debug-specific logic diagrams showing the structure of selected portions of a design. These two tools can be opened through ntrace. 56
57 Before Using Verdi Source the environment settings of CAD tools. source ~cvsd/verdi.cshrc To avoid the Verdi warning window occurs, please type the following command: setenv LM_LICENSE_FILE 57
58 Start Verdi Type the following command: verdi & Also, the token "&" enable you to use the terminal while Verdi is running in the background. Just ignore this warning. 58
59 ntrace 1 59
60
61 1 (double-click) Hierarchical Browser Netlist Code Window Message Window 61
62 1 1 double-click 62
63 1 1 double-click 63
64 1 64
65 1 65
66 2 1 66
67 67
68 2 1 68
69 69
70 nschema 1 70
71 Push View In 1 (double-click) 71
72 1 72
73 73
74 1 (right-click) 2 74
75 1 (right-click) 2 75
76 76
77 nwave 1 77
78
79 1 Press middle mouse button, drag and then drop. 79
80 80
81 1 Ctrl + C 81
82 1 (right-click) 2 82
83 83
84 1 2 84
85 1 85
86 1 86
87 87
88 88
89 The End. Any question?
90 Reference 1. "MobaXterm User Manual by The Centre for eresearch, University of Auckand. 2. "Cadence NC-Verilog Simulator Tutorial by Cadence 3. "Quick Start: an nlint Tutorial" by NOVAS 4. "Introduction to Verdi" by Abel Hu 5. "Verdi 3 datasheet" by Synopsys 90
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