Cell-Based Design Flow. TA : 吳廸優

Transcription

1 Cell-Based Design Flow TA : 吳廸優 dywu@viplab.cs.nctu.edu.tw 1

2 Outline Overview Design Flow Stage 1 RTL Development Synthesis Gate Level Simulation Design Flow Stage 2 Placement and Routing Post Layout Simulation 2

3 Cell-based Design Flow Overview A design flow is a set of procedures that allows designers to progress from a specification for a chip to the final chip implementation in an error-free way. 3

4 Source: CM: 5086 VLSI Design Lab Cell-based Design Flow Stage 1 Implement your own verilog program Need to pass the provided testbench Synthesis your logic with provided (or modify by yourself) tcl file Stage 2 Use your(provided) netlist file to run the Auto Place and Route (APR) flow Specification Development System Models RTL code development Functional Verification Synthesis Timing Verification Physical Synthesis/Place and Route Physical Verification System Architecture RTL Synthesis Physical Design Prototype Build and Test 4 System Integration and Software Test

5 Cell-based Design Tool System Architecture/SW simulation C/C++, Matlab, System C, System Verilog RTL simulation/debug NC-Verilog, NC-VHDL, ModelSim, Verdi(nWave) (without delay) Synthesis RTL Compiler, Design Compiler, Power Compiler Gate level simulation/debug NC-Verilog, NC-VHDL, ModelSim, Verdi(nWave) (with delay) Physical Design SoC Encounter, Astro, IC Compiler Others PrimePower, Calibre, Nanosim 5

6 Outline Overview Design Flow Stage 1 RTL Development Synthesis Gate Level Simulation Design Flow Stage 2 Placement and Routing Post Layout Simulation 6

7 RTL Development Development / simulation NC-verilog $ncverilog + <your_testbench_file> 7

8 RTL Development Check the simulation output Dump waveform from testbench when simulation $fsdbdumpfile( MAC.fsdb ); nwave $nwave (Verdi -nwave) 8

9 RTL Development Verilog dump related command VCD file format(value Change Dump) $dumpfile( output.vcd ); $dumpvars; FSDB file format(from Novas) $fsdbdumpfile( output.fsdb ); $fsdbdumpvars; Fsdb file is the input of Verdi Verdi(debussy): a powerful debugging tool provided by NOVAS $ Verdi 9

10 Verdi from NOVAS $ Verdi & File->Import Design ->From File ->TESTBED.v ->Add ->OK RTL Development 10

11 Source: CIC Jan.08 Design Compiler Synthesis Synthesis=translation+ optimization+ mapping Residue = 16 h0000; If(high_bits==2 b10) residue = state_table[i]; Else state_table[i] = 16 h0000; HDL Source(RTL) Translate(HDL Compiler) Optimize + Map (Design Compiler) NO Timing Info => Generic Boolean Timing Info => Target Technology 11

12 Synthesis Design Compiler It synthesizes your designs (Verilog) into optimized technology-dependent, gate-level designs. Use Design Compiler GUI Startup x-win ( or any other X terminal application) $design_vision (dv) 12

13 Synthesis Environment Setup /home directory/.cshrc : set path and license of synthesis tool /your working directory/.synopsys_dc.setup : setup technology file, designware library file etc Use DC-TCL script file(.tcl) Set design constraints $dv -f syn.tcl 13

14 Synthesis Detail of.synopsys_dc.setup ASIC Technology file (cell library) For schematic For Designware 14

15 Synthesis Modify the syn.tcl Your Design Name TOP Module Name Set wire delay model Setup & hold time library 15

16 Synthesis 16

17 Synthesis SDC file : synopsys design constrain Setup input/output delay and loading SDF file : standard delay format Setup the rising/holding/falling time for each cell of your design 17

18 Synthesis Put the RTL file,.synopsys_dc.setup and syn.tcl to your working directory, or assert the setup commands by hand, while synthesis. Under your working directory, make new directories, Report and Netlist, for saving synthesis reports. 18

19 Synthesis Output result Command return result(error) command command Command return result(done) 19

20 Synthesis The synthesis information is in your Report directory timing.txt 20

21 Gate Level Simulation Verify your synthesis result Modify your testbench (TESTBED.v) `include./netlist/seq_mac16_syn.v sdf_annotate(./netlist/seq_mac16_syn.sdf, top) $ncverilog + <your_testbench_file> + -v <Tech_verilog_file> 21

22 Gate Level Simulation Check the simulation output nwave $nwave (Verdi -nwave) 22

23 Outline Overview Design Flow Stage 1 RTL Development Synthesis Gate Level Simulation Design Flow Stage 2 Placement and Routing Post Layout Simulation 23

24 SOC Encounter Placing & Routing Flow Netlist(verilog) Timing Constrain(sdc) IO Constrain IO, P/G Placement Specify floorplan Power Planning Amoeba Placement Timing Analysis Pre-CTS Optimize Power Route Clock Tree Synthesis Timing Analysis Post-CTS Optimize Power Analysis SI Driven Route Timing/SI Analysis Post-Route Optimize GDS file Netlist, DEF 4 Main Step (must be in order): IO Placement, Cell Placement, CTS, SI Driven Routing 24 Source: CIC Jan. 2009, SoC Encounter

25 Basic View $encounter Floorplan view Ameoba view Physical view 25

26 Design -> Design Import Project Setup netlist Cell Library Physical Library IO Map file 26

27 IO, Power/Ground Placement Floorplan -> Connect Global Nets 27

28 Floorplan Floorplan -> Specify Floorplan 28

29 Power Planning Power -> Power Planning -> Add Rings 29

30 Cell Placement Place -> Standard Cell And Blocks 30

31 Route -> Special Route Power Route 31

32 Pre-CTS Timing Timing -> Analyze Timing -> Pre-CTS -> Setup If timing is not meet, Timing -> Optimize -> Pre-CTS 32 -> setup

33 Add Tie Hi/Lo cell Place -> Tie HI/LO -> Add 33

34 Clock -> Design Clock Clock Tree Synthesis 34

35 Post-CTS Timing Timing -> Analyze Timing -> Post-CTS -> setup/hold If timing is not meet, Timing -> Optimize -> Post-CTS 35 -> setup/hold

36 Route -> NanoRoute SI Driven Route 36

37 Post-Route Timing Timing -> Analyze Timing -> Post-Route -> setup/hold If timing is not meet, Timing -> Optimize -> Post-Route 37 -> setup/hold

38 Result Analysis Final step DRC LVS verification Save file Verify -> Verify Connectivity Verify -> Verify Geometry Design -> Save Design As -> SoCE -> Seq_MAC16_final.enc Design -> Save -> Netlist -> Seq_MAC16_LAYOUT.v Timing -> Calculate Delay -> disable ideal Clock -> Seq_MAC16_LAYOUT.sdf 38

39 Final 39

40 Post Layout Simulation Verify your physical design result Modify your testbench (TESTBED.v) `include./netlist/seq_mac16_layout.v sdf_annotate(./netlist/seq_mac16_layout.sdf, top) $ncverilog + <your_testbench_file> + -v <Tech_verilog_file> 40