Tutorial for Verilog Synthesis Lab (Part 2)

Transcription

1 Tutorial for Verilog Synthesis Lab (Part 2) Before you synthesize your code, you must absolutely make sure that your verilog code is working properly. You will waste your time if you synthesize a wrong code! A synthesizer takes high-level design file (HDL code) and produces gate level representation of the design using technology library. Same design can be represented in gate level in multiple ways. Using synthesis tool, we will try to get optimized representation of our HDL code. In this tutorial, we will use the simple decoder that we encoded and simulated in Part 1. To complete lab requirement, you must synthesize the serial multiplier that you have written, tested and verified. 1) For synthesis, we will use Design Analyzer from Synopsys. To initiate design analyzer, go to lab3 directory (cd /ELEC4708/lab3) and type design_analyzer. You should see a blank window of Design Analyzer. Investigate through menus to familiarize yourself with the tool. 2) Click Setup->Defaults to setup default environment. DO NOT close any windows in the Design Analyzer by using the "close" window command of the native windowing environment! ALWAYS use the Cancel buttons provided. 3) Before we proceed further, check to make sure your design environment is set up properly. Open a File Manager and go to the lab3 directory. Select view->show hidden files option. You should see a file named.synopsys_dc_setup (The leading dot means it s a hidden file, in case you are wondering). 4) Right click on the file and select Open. See if following lines exist in your file and are not commented out. If not, edit properly. Save and exit your editor. /* Canadian Microelectronics Corporation * Sample.synopsys_dc.setup file, for use with CMOSP18 * March 14, 2000 * * Library and Search Path variables assume links are in place so * $SYNOPSYS/cmc/cmosp18 points to the libraries in this design kit * which are compiled for the proper version of Synopsys */ /* search_path = {.} ELEC4708: Lab 3 Tutorial (2) Bashir Morshed Page 1 of 8

2 search_path = search_path + {synopsys_root + /libraries/syn} search_path = search_path + {synopsys_root + /cmc/cmosp18/syn} */ search_path = {.} search_path = search_path + {/CMC/tools/synopsys2004/syn_V SP1/libraries/syn/} search_path = search_path + {/CMC/kits/cmosp18/synopsys/2004/syn} search_path = search_path + {/opt/ads/dsynthesis/lib/verilog} search_path = search_path + {/CMC/tools/synopsys2004/syn_V SP1/libraries/syn + /dw/sim_ver} synlib_wait_for_design_license = {DesignWare-Foundation} link_library = "tpz973gwc.db vst_n18_sc_tsm_c4_wc.db *" target_library = {tpz973gwc.db vst_n18_sc_tsm_c4_wc.db} symbol_library = {} /* Assume there is a./work directory */ define_design_lib work -path Work /* Try and make names compatible with Cadence dfii, from Preview man. */ bus_naming_style = "%s_%d_" verilogout_no_tri = "true" define_name_rules preview -allowed "A-Za-z0-9_" /* Preview man. page says set the verilogout_single_bit = true, but to get the sram cells to work you may need false. */ verilogout_single_bit = "true" /* Some usefull scripts. */ view_script_submenu_items = \ {"Remove All Designs","remove_design find(design \"*\")", \ "Save All Designs", "write find(design \"*\") -out save.db", \ "set_dont_touch All Designs", "set_dont_touch find(design \"*\")", \ "Remove dont_touch All Designs", \ "remove_attribute find(design \"*\") dont_touch", \ "Remove Unconnected Ports", \ "remove_unconnected_ports -blast_buses find(-hierarchy cell, \"*\")", \ "Fix Multiple Ports (on selected hierarchy)", \ "set_fix_multiple_port_nets -all", \ "Change Names for Preview", \ "change_names -rules preview -hierarchy > change_names.out" } 5) Click Setup->Command Window. This will bring up the command window that gives you access to dc_shell and also immediate feedback on the progress of your synthesis session. Resize it and drag it to the appropriate place in your display. All commands entered via the menus of the Design Analyzer are echoed, so you can learn how to write dc_shell commands. Advanced users always use shell command of this command window and script files for synthesis. 6) Click File->Read. Then browse the verilog file. You should notice a block named decoder shown in design analyzer window. Cancel the verilog window. All lines should also be seen in command window. The design analyzer window showing top Hierarchy level of the simple decoder should look like the snapshot below. ELEC4708: Lab 3 Tutorial (2) Bashir Morshed Page 2 of 8

3 Notice the button on the left hand side toolbar. In your multiplier, you might have one or more modules, depending on your code. 7) To analyze a verilog file, click File->analyze. Then browse through the directory to find your verilog file. For this tutorial we will synthesize 3-bit decoder (located in /lab3/decoder/verilog/verilog.v). Later you have to synthesize the multiplier. As the decoder is much simpler, expect to go through additional requirements for the multiplier. Some tips are given at the end of the tutorial. Enable Create New Library if it does not exist. Default library is WORK. Cancel Analysis window and read info in command window. If successful, go to next step. 8) Select the decoder, then click File->elaborate. Select Library: WORK and Design: Decoder(verilog). Click OK. It produces lower level representations for you design. It might also create another decoder icon. Cancel Elaborate window and read info in command window. 9) Double click on any decoder icon. You will see Symbol level representation with pins for inputs and outputs. Zoom in and see different features of this view. Notice that the active icon on the left side toolbar is changed from top level to symbol level. Also up arrow button became active, as you can move up one level now. These arrows (up and down) are to traverse the hierarchy of a design. ELEC4708: Lab 3 Tutorial (2) Bashir Morshed Page 3 of 8

4 10) Double click on the decode module and you will see Schematic level representation. It should look like the picture below. This gate level implementation of the 3 bit decoder has 9 inverters, 6 OR gates and 2 AND gates. Zoom in and see different areas in details. Why do you see two colors for wires (green and blue)? Why there are only one input pin and one output pin? Do you think this is the optimal implementation for the decoder? Why? 11) We have to compile the design to get optimized synthesized implementation. For the simple decoder that we have, we will only add capacitive loading at output port and compile it. We will use a capacitive load of 0.2 pf. Symbol level view is convenient for applying attributes and constraints to a design. Select the output pin (port), then click Attribute->Operating Environment->Load, enter 0.2 in ELEC4708: Lab 3 Tutorial (2) Bashir Morshed Page 4 of 8

5 capacitive load field (do not put unit as no character is permitted, you must use default unit of pf). Click Apply, then Cancel. Cancel the bus selector window also. 12) Now, to synthesize the design, type compile in the command window. Wait until the simulation is done. Go through all the info posted in command window. 13) Look at the new implementation generated by synthesizer. It has actually optimized your design automatically! Now you see only 3 inverters and 8 NOR ELEC4708: Lab 3 Tutorial (2) Bashir Morshed Page 5 of 8

6 gates. Keeping the functionality same, the synthesizer optimizes a design based on constraints. 14) Scroll the command window and you will notice different steps of optimization and a lot of other information. By default, we have used medium effort for optimization. As you increase your effort, simulation time becomes longer. 15) Click Tools->Design Optimization. You can access some optimization criteria from here. When you click OK, the synthesizer will compile with that option. Otherwise, you can type compile map_effort high to synthesize with high effort. Type compile -? to check out available command line options. For our simple decoder design, however, compiling efforts do not change this decoder schematic, as this is a very simple circuit anyway. For your multiplier, it might make huge differences. ELEC4708: Lab 3 Tutorial (2) Bashir Morshed Page 6 of 8

7 16) To save your design as an unmapped db format, select File -> Save As, navigate to the WORK directory in the Directory menu, and name your design as decoder.db, choose DB as the File Format. Select Save all designs in hierarchy option. When a design is saved as a.db file, the design plus all attributes are saved. The equivalent command will be: write -format db -hierarchy output decoder.db. 17) For reports, select the top level design, click Analysis -> Report, select on Area, Timing. You could direct the output to a file for later reference. Inspect the Report Output window, use the mouse to select a line, click on the Next button, the item(s) in the corresponding schematic will be "selected" automatically. The equivalent dc_shell commands will be: report_area and report_timing. 18) To exit the design analyzer, select File->Quit. Click OK. ELEC4708: Lab 3 Tutorial (2) Bashir Morshed Page 7 of 8

8 Some tips for the serial multiplier synthesis: To read in another design without quitting Design Analyzer, first remove the current design by selecting the design to be removed, then Edit -> Delete. This would remove the design from the Design Compiler memory, it would not remove any physical design files. Then load another design by analyze, read. To analyze or read multiple files, use left mouse button to select one file, then use middle mouse button to select the rest. You can also type names in the window with space in between (not comma). Notice the prompts in command window. Look for errors and warnings. Those lines are printed for reasons! In design analyzer section, you might need to do uniquify after your have done Read, Analyze and Elaborate (depending on your code). To uniquify, select the TOP MODULE and click Edit -> Uniquify -> Hiererchy. If you have clock in your design, you must assign Attributes->Clocks->Specify and Skew properties. Select Don t Touch Network in this window to avoid synthesis of clock tree (preferred). Set the period for your clock in this window. To set timing constraint, select input port and output port on which you want to set up the constraint. Click Attributes>Optimisation Constraints>Timing Constraints. A new window will pop up where you will see a From field which contains name of input port and a To field which contains output port name. If you fill maximum delay>rise 10 and select Same Rise and Fall, the synthesizer will set maximum delay of 10 ns for that path. It is equivalent to say set_max_delay 10 from InPort to OutPort in command window. Go through Attributes menu and see all available options. You can also specify drive strength for input ports, input/output delays, operating conditions etc. To specify the maximum area and maximum fanout constraint, select Attributes>Optimisation Constraints>Design Constraints. To see the critical path, use control-t. Select pins or ports and select Analysis- >Highlight to see related information. To check timing violations, inspect the timing report. Each Incr entry indicates the delay from the previous point to the current point, and the Path entry indicates the total delay from the input external delay to the current point. You can detect any suspicious path with exceptional long delay through this inspection. The most important thing is to check the slack, which is the required delay minus the actual delay, if it reports MET, your design has met the timing constraints, if it reports VIOLATED, you should go back to your HDL code and re-write it to improve timing. Then go back and re-analyze -elaborate the block and compile the whole design again. You can re-simulate your netlisted file to verify functionality of the synthesized design. ELEC4708: Lab 3 Tutorial (2) Bashir Morshed Page 8 of 8