EE 5327 VLSI Design Laboratory. Lab 1 - Verilog Simulation

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1 EE 5327 VLSI Design Laboratory Lab 1 - Verilog Simulation PURPOSE: The purpose of this lab is to introduce you to gate, behavioral and dataflow Verilog models. You will compile and simulate three models for a full adder & a model for a four-bit adder using the Synopsys Verilog tool suite - VCS. Setup 1. Use a text editor to put those settings in your home account (/home/class/ee5327xx/).cshrc file. # for vcs setenv SNPSLMD_LICENSE_FILE 27000@dogbert.itlabs.umn.edu setenv VCS_HOME /home/vlsilab/synopsys/vcs set path=($vcs_home/bin /usr/ccs/bin $path) 2. Save.cshrc file and quit the text editor. 3. Source.cshrc file by typing the following command at UNIX command prompt. (Note that you DON T have to do this in your next login and beyond.) source.cshrc 4. Type mkdir labs to make a directory labs in your home directory. 5. Type cd labs to enter the directory labs. 6. Type mkdir lab1 to make a directory lab1 in the directory labs. 7. Type cd lab1 to enter the directory lab1. 8. Download files to lab1 directory. Compile and Simulate Files Using Command Line 9. Use the following VCS commands to compile and simulate Verilog files. The VCS compiler will generate an executable file simv and two folders (csrc/ and sim.daidir/) which contain object files and libraries. vcs Is the command that starts the Verilog compiler. -Mupdate Is a compile-time option. Compile-time options control how VCS compiles your source code. There are also run-time options that control how VCS simulates your design. This compile-time option specifies incremental compilation and update the makefile. Incremental compilation is compiling only the modules that have changed since you last compiled the source file. Using this compile-time option now, even though you have never compiled any of the design s modules before is worthwhile because this option also tells VCS to create a subdirectory in your current directory named csrc and in that subdirectory are object files, and in some cases C or assembly intermediate files, and files Univ. of Minnesota Jan 13, of 5

2 that VCS uses to determine if it needs to compile a module over again. The makefile contains commands that VCS uses to generate object files, sometimes C or assembly files, and build the executable that you simulate. Over-writing the makefile with a new one ensures that VCS does not use a makefile that is out of date for your design. We recommend that you always use the -Mupdate compile-time option Compile and simulate gate model vcs Mupdate fa_st.v fa_gate.v 9.2. Compile and simulate dataflow model vcs Mupdate fa_st.v fa_df.v 9.3. Compile and simulate behavioral model vcs Mupdate fa_st.v fa_bh.v Compile and Simulate Files Using with VirSim 10. Use the following commands to start interactive simulation. vcs Is the command that starts the Verilog compiler. -RI This compile-time option tells VCS to start simulation immediately after compilation and start VirSim. Think of this option as telling VCS to Run Interactively after it compiles your source code Compile and simulate gate model vcs Mupdate RI fa_st.v fa_gate.v Compile and simulate dataflow model vcs Mupdate RI fa_st.v fa_df.v Compile and simulate behavioral model vcs Mupdate RI fa_st.v fa_bh.v 11. The popped up window is VirSim Interactive window that looks like this. Univ. of Minnesota Jan 13, of 5

3 12. Click on Window/Hierarchy and Window/Waveform respectively to bring up the hierarchy and waveform windows. Univ. of Minnesota Jan 13, of 5

4 13. Click on stimulus in the Hierarchy window and then the signals will be listed on the right-hand side pane. 14. Select all the signals and drag them (using middle button of your mouse) into the Univ. of Minnesota Jan 13, of 5

5 waveform window. 15. In the interactive window, there are three panes. The bottom pane is Simulator Control where you click on the upper OK button that will trigger the simulator to run 20 sec. You may modify this step number as needed. 16. Print. You can specify the begin time and end time of the final print out and the print command is lp dvlsilab. Or you may print your waveform into a postscript file and then send the file to the printer using the command: lp dvlsilab mywaveform1.ps, assuming you saved it under the name mywaveform1.ps. If your waveforms appear congested, then you may increase the Time Slices to 2 or more before you print them. Task: Design, compile and simulate your own four bit adder (either ripple or carry look ahead adder). Try to ensure that your stimulus module will be a good test bench for your design. A two-bit adder Verilog file is given for reference. The command to compile the file is: vcs Mupdate twobitfa.v fa_xx.v (any 1-bit full adder module). Then type to start simulation. Reference [1] VCS User Guide from Synopsys Inc. Univ. of Minnesota Jan 13, of 5