Fri. Aug 25 Announcements

Transcription

1 Fri. Aug 25 Announcements HW 1 / Lab 1 next week Tools and fundamentals of instructions Remember no in-lab quiz but HWs still marked Slides online Complete class for last year This year s slides available as I mod/create them. First In-Class Quiz Monday First 10 minutes of class Make sure clickers are registered You can have any resources you want/need 1

2 Module 1-B ISA Overview Tim Rogers

3 Learning Outcome #1 An ability to program a microcontroller to perform various tasks How? A. Architecture and Programming Model B. Instruction Set Overview C. Assembly Control Structures D. Control Structure Applications E. Table Lookup F. Parameter Passing G. Macros and Structured Programming 3

4 Objective Instruction Set Overview Prof. Meyer s Perspective Why? Prof. Rogers Perspective 362 Student s Perspective? Actual ECE 362 Meme (Author unknown) 4

5 Notation for numbers Notation How Used Examples Prefix: $ Suffix: h/h hexadecimal (base 16) number $1234 = 1234h = 1234H = Prefix:! Suffix: t/t Prefix: % Suffix: b/b decimal (base 10) number!1234 = 1234t = 1234T = binary (base 2) number % = b = B =

6 Review of conversions Easy to convert between power-2 bases Formally can always break/group pow-2 bases num_bits = log 2 (base) 6

7 Short Cut for Conversion Among Powers of 2 Exercise: Convert (110101) 2 to base 16 (hex) l Exercise: Convert (A3F) 16 to base 2 (binary) 7

8 In your head power two conversions Many way to think about this My approach: Remember way-points 2 5 = = 1024 =1k 2 20 = 1024k = 1M So when I asked you how much memory in 16-bits (2 16 ): Take the exponent, break into easy waypoints: 16 = 10 1k + 5 x x 2 = 64k 8

9 General Notation Notation How Used Examples ( ) contents of register/memory location (A) (0800h) ; beginning of a comment LDAA 0800h ; (A) = (0800h) : concatenation of two quantities 16-bit result in (A):(B) º (D) 32-bit result in (D):(X) 9

10 General Notation Notation How Used Examples assignment or copy (arrow points to destination) (A) (B) means load the A register with the contents of the B register (the contents of B remains the same) «exchange (or swap ) of contents (D) «(X) means exchange the contents of the D and X registers ~ shorthand for number of assuming an 8 MHz bus clock, each cycle is instruction execution cycles 125 ns (nanoseconds) (bit-wise) complement mask means the bit-wise complement of mask 10

11 Addressing Notation Notation How Used Examples addr effective address for operand LDAA addr ; (A) = (addr) # immediate addressing when used before const. operand, indexed addressing when placed between two entities in the operand field [ ] indirect addressing when used to bracket the operand field LDAA #80h ; (A) = 80h LDAA #$12 ; (A) = 12h LDAA #$A5 ; (A) = A5h LDAA # b ; (A) = AAh LDAA 2,X ; (A) = ((X) + 2) STAA D,Y ; ((D)+(Y)) = (A) STAA [2,X] ; (((X)+2):((X)+3)) = (A) LDAA [D,Y] ; (A) = (((D)+(Y)):((D)+(Y)+1)) 11

12 Addressing Mode and Operands Operand Memory Operand Output Typically in our accumulator ISA: One operand is a register that is also the output Other comes from memory Some exceptions: Store outputs to memory Only one operand in some instructions Addressing mode determines where instruction inputs/outputs come from / go to 12

13 Inherent Addressing Abbrev. Name Description Examples INH Inherent Operand[s] in register[s] DAA DEX Example Instruction X -1 Assembly Instruction opcode DEX Operands implicit from opcode 13

14 Immediate Addressing Abbrev. Name Description Examples IMM Immediate Operand follows #. Value embedded in instruction. LDAA #$FF ADDA #3 A Example Instruction Assembly Instruction opcode immediate ADDA # Value of operand encoded in instruction. 14

15 Direct Addressing Abbrev. Name Description Examples DIR/EXT Direct/Extended Effective memory address in instruction. Direct = 1B addr. Extended = 2B addr. LDAA $FF ; direct ADDA $88FF ; extended A Example Instruction Memory Eff. Address Assembly Instruction Eff. Address of operand encoded in instruction. opcode addr high addr low ADDA $88FF

16 Mon Aug. 28 Announcements To refresh anything on the course website use shift+refresh Error in the slides? Good catch! Post it to piazza, I will correct it and you will get bonus credit. 16

17 Addressing Mode Types 1. Inherent 2. Immediate 3. Direct/Extended 4. Indexed with constant 5. Indexed with accumulator offset 6. Indexed with auto pre/post inc/dec 7. Indexed-Indirect with constant offset 8. Indexed-Indirect with Accumulator Offset 17

18 Indexed with constant offset Abbrev. Name Description Examples IDX IDX1 IDX2 X A Indexed with Constant Offset Eff. address = (<X Y SP PC>) + signed_const IDX=5-bit const IDX1=9-bit const IDX2=16-bit const Example Instruction LDAA 0,X STAA -50,Y ADDA 1024,X Post-byte which index register Const. offset encoded in instruction. Memory Eff. Address + Assembly Instruction opcode postbyte offset high offset low ADDA 1024,X

19 Indexed with accumulator offset Abbrev. Name Description Examples IDX X A Indexed with Accumulator Offset + Eff. address = (<X Y SP PC>) + (A B D) Accumulator is treated as unsigned Example Instruction LDAA B,X STAA A,X ADDA A,X Post-byte defines which index register + accumulator. Memory Assembly Instruction opcode postbyte ADDA A,X

20 Indexed with auto increment/decrement Abbrev. Name Description Examples IDX Indexed with Auto Pre-/Post- Increment or Decrement Eff. address = (<X Y SP PC>) + signed_const Can inc/dec index reg. before/after use. Const range: 1-8 LDAA 1,-Y ; pre-dec STAA 2,+SP ; pre-inc ADDA 8,PC- ; post-dec ADDA 8,X+ ; post-inc X A Example Instruction + Inc/dec value encoded in instruction Memory Assembly Instruction opcode postbyte ADDA 8,X Post-byte defines which index register. 20

21 Indexed-Indirect with constant offset Abbrev. Name Description Examples [IDX2] Indexed-Indirect with Constant Offset X A Eff. address = ((<X Y SP PC>) + signed_const) Example Instruction LDAA [0,Y] ADDA [5,X] Memory 2 memory lookups Eff Address (H) Eff Address (L) Indirect Address + Assembly Instruction opcode postbyte offset high offset low ADDA [5,X]

22 Indexed-Indirect with accumulator offset Abbrev. Name Description Examples [D,IDX] Indexed-Indirect with Accumulator Offset X D Eff. address = ((<X Y SP PC>) + (D)) + Example Instruction LDAA [D,Y] ADDD [D,X] Memory 2 memory lookups Eff Address (H) Eff Address (L) Assembly Instruction opcode postbyte ADDD [D,X]

23 Pointless Clicker question #1 Do you think you understand indirect addressing: A: Yes P B: No 23

24 Pointless Clicker Question #2 What is the result after the instruction: ADDA 2,X Memory Addr Value 0 0t A: A=12t, X = 0t B: A=17t, X = 0t P C: A=21t, X = 2t D: A=21t, X = 0t E: I am too lost to try Regs Name Value A 10t 1 2t 2 7t 3 0t X 0t t 24

25 Pointless Clicker Question #3 What is the result after the instruction: ADDA [0,X] Memory Addr Value 0 0t A: A=12t, X = 0t B: A=17t, X = 0t P C: A=21t, X = 2t D: A=21t, X = 0t E: I am too lost to try Regs Name Value A 10t 1 2t 2 7t 3 0t X 0t t 25

26 Instruction classes Data Transfer Arithmetic Logical Transfer of control (branch/jump) Machine control special or weird Every instructions in ISA listed in 2 places: Quick reference: Detailed Description: 26

27 Data Transfer Instructions Just move data Swap Regs: 4 Exchange 1 Memory to Register: Load/Stack Pop B A 3 Register to Register: Transfer (Move) 2 Register to Memory: Store/Stack Push 5 Copy Memory: Move Memory 27

28 Wed Aug. 30 Announcements Quiz results uploaded to blackboard Ended up being out of 8 (5 in actual quiz + 3 pointless questions). Everyone just got a point for the pointless questions. 28

29 Loads/Stores Description Assembly mnemonic operation Examples Load register with memory value Store register into memory LDA<A B> addr; 8-bit LD<D X Y S> addr; 16-bit STA<A B> addr; 8-bit ST<D X Y S> addr; 16-bit Note: These instructions will change condition register (CCR) bits. 1-6 cycles dep. on addressing mode Move data between registers and memory Can use different addressing modes (<A B C D X Y SP PC>) (addr) LDAA #4 LDAB [D,X] (<A B C D X Y SP PC>) (addr) STAA $4 STD [0,Y] Which addressing modes make no sense in stores? 29

30 B Exchange A Swap register contents Note: Only Inherent addressing used Description Assembly mnemonic operation Examples Exchange Register Contents EXG <ANY>,<ANY> (<ANY>) «(<ANY>) EXG A,B EXG A,X Some complications, can you guess when? Does not change CCR bits. All take 1 cycle. 8-bit Lower ½ 16-bit 16-bit bit 30

31 B Transfer (Copy) Register A Copy one register to another Description Assembly mnemonic operation Examples Copy Register Note: Only Inherent addressing used TFR <ANY>,<ANY> (<ANY>) (<ANY>) TFR A,B TFR A,X Some complications, can you guess when? Does not change CCR bits. All take 1 cycle. 16-bit 8-bit Signextension 8-bit 16-bit 8-bit Lower ½ 16-bit 31

32 Move (Copy) Memory Copy memory values Description Assembly mnemonic operation Examples Copy 1B Memory Copy 2B Memory MOVB addr1,addr2 ; 8-bits (addr1) (addr2) MOVB #1, $900 MOVB 1,X+,2,Y+ MOVW addr1,addr2 ; 16-bits (addr1) (addr2) MOVW #1, 0, X (addr1+1) (addr2+1) MOVW 1,X+,2,Y+ Does not change CCR bits. 4-6 cycles. addr1: IMM, DIR, INDEXED Addr2: DIR, INDEXED 32

33 Stack Review First In Last Out (FILO) or Last In First Out (LIFO) Data Structure Name A B Regs Value 5t 10t PULA PSHB SP Memory Addr Value t Stack grows down (in addresses) SP 100t 99t

34 Stack Instructions Save and retrieve data from stack Description Assembly mnemonic operation Examples Push Register to Stack PSH<A B C> ; 8-bits (SP) (SP) - 1 ((SP)) <A B C> PSH<D X Y>; 16-bits (SP) (SP) - 1 ((SP)) (lower-8-bits<d X Y>) (SP) (SP) - 1 ((SP)) (upper-8-bits<d X Y>) Pull (Pop) Register from Stack PUL<A B C>; 8-bit Note: PULC overwrite CC register PSH: 2 cycles PUL: 3 cycles (<A B C>) ((SP)) (SP) (SP) + 1 PUL<D X Y>; 16-bit (upper-8-bits<d X Y>) ((SP)) (SP) (SP) + 1 (lower-8-bits<d X Y>) ((SP)) (SP) (SP) + 1 PSHA PSHY PULB PULX 34

35 Instruction Classes 1. Data Transfer 2. Arithmetic Group 3. Logical 4. Transfer of control (branch/jump) 5. Machine Control 6. Special 35

36 Arithmetic Instructions Heart of the ISA. Performs arithmetic 1. Add 2. Subtract 3. Multiply 4. Divide 5. Compare/Test 6. Complement 7. Increment/Decrement 8. Min/Max 36

37 Add Note: CC bits were made for these instructions. N/Z/V/C/H are all effected 1-6 cycles, depending on addressing mode Description Assembly mnemonic operation Examples Add contents of memory to register ADD<A B> addr; 8-bit (<A B>) (<A B>) + (addr) ADDA #4 ADDB [2,X] ADC<A B> addr; 8-bits (<A B>) (<A B>) + (addr) + (c) ADCA #4 ADCB [2,X] ADDD addr; 16-bit (D) (D) + (addr):(addr+1) ADDD $900 ADDD 1,X 37

38 Subtract Note: CC bits were made for these instructions. N/Z/V/C/H are all effected Description Assembly mnemonic operation Examples Subtract contents of memory to register SUB<A B> addr; 8-bit (<A B>) (<A B>) - (addr) SUBA #4 SUBB [2,X] SBC<A B> addr; 8-bits (<A B>) (<A B>) - (addr) - (c) SUBA #4 SUBB [2,X] SUBD addr; 16-bit (D) (D) - (addr):(addr+1) SUBD $900 SUBD 1,X Modes/structure identical to addition What is missing from ADD/SUB? 38

39 Load Effective Address (LEA) Can think of it as a way to perform arithmetic on 16-bit registers Simply: (X) (X) + 2 Description Assembly mnemonic operation Examples Compute address, store it in register LEA<X Y S> addr (<X Y S>) addr LEAX 2, X LEAY B, X LEAY 2, -X Can use any Indexed addressing mode 39

40 Register-to-Register Add Description Assembly mnemonic operation Examples Add Registers ABA (A) (A) + (B) ABA AB<X Y> (<X Y>) $00:(B) + (<X Y>) ABX ABY Are replaced with: LEAX B,X LEAY B,Y 40

41 Overflow Dependent on the integer bit-width Occurs because the result is larger (or smaller) than can be represented in the fixed bit-width Ex: 8-bit numbers 255t+1t=256t $FF + $1 = $100 = $00 (in 8-bits) Generally you can detect overflow if: Adding 2 +ive numbers results in the ive number Adding 2 ive numbers results in a +ive number Adding numbers of opposite signs CANNOT result in overflow Note: You can also detect overflow if the carry-in to the sign-bit is different from the carry-out bit 41

42 Other conditions (all bits in CCR register) Zero: Result was zero Negative: Highest bit is 1 Carry/Borrow: Carry-out of the sign position after addition or borrow out of the sign position after subtraction. 42

43 Review: Packed Binary Coded Decimal 4-bits to describe a digit between 0-9 $A-$F not used 2 digits in every byte. Want to perform normal binary addition on data in BCD format Problem: Normal addition does not know about BCD Solution: Add special adjusting instruction 43

44 Decimal Adjust Note: Just an adjustment. MUST be run after ADD ADC ABA Description Assembly mnemonic operation Examples Decimal Adjust A DAA Decimal adjust the result of ADD, ADC, or ABA DAA 44

45 ADD of BCD Operands Followed by DAA DAA

46 ADD of BCD Operands Followed by DAA DAA

47 ADD of BCD Operands Followed by DAA result of ADD DAA

48 ADD of BCD Operands Followed by DAA DAA result of ADD since L.N. > 9, add 6 to adjust

49 ADD of BCD Operands Followed by DAA DAA result of ADD since L.N. > 9, add 6 to adjust

50 ADD of BCD Operands Followed by DAA DAA result of ADD since L.N. > 9, add 6 to adjust since U.N. > 9, add 6 to adjust 50

51 ADD of BCD Operands Followed by DAA DAA result of ADD since L.N. > 9, add 6 to adjust since U.N. > 9, add 6 to adjust CF is hundred s position 51

52 ADD of BCD Operands Followed by DAA DAA result of ADD since L.N. > 9, add 6 to adjust since U.N. > 9, add 6 to adjust CF is hundred s position ten s one s 52

53 Multiply Description Assembly mnemonic operation Examples 8x8 unsigned integer multiply 16x16 unsigned integer multiply 16x16 signed integer multiply Description 16x16 integer multiply and accumulate MUL (D) (A) x (B) MUL EMUL (Y):(D) (D) x (Y) EMUL EMULS (Y):(D) (D) x (Y) EMULS Note: special addressing mode Assembly mnemonic operation EMACS addr (addr):(addr+1):(addr+2):(addr+3) (addr):(addr+1):(addr+2):(addr+3) + ( ((X)) x ((Y)) ) Examples EMACS 53

54 Divide Description Assembly mnemonic operation Examples unsigned integer divide signed integer divide unsigned integer divide signed integer divide unsigned fraction divide IDIV IDIVS EDIV EDIVS FDIV (X) (D) (X) (D) remainder (X) (D) (X) (D) remainder (Y) (Y):(D) (X) (D) remainder (Y) (Y):(D) (X) (D) remainder (X) (D) (X) (D) remainder IDIV IDIVS EDIV EDIVS FDIV Assumes operands are unsigned binary fractions 54

55 Unsigned Binary Fractions Motivation: Number <1 MSB of unsigned binary fraction is 2-1 Do we need an FMUL? A: Yes B: No P What is the result of FDIV produced when dividing $2000 by $8000? A: $0000 B: $4000 P C: $8000 D: $FFFF E: none of the above 55

56 Fri Sept. 1 Announcements No Class/Lab Office Hours Monday In class Quiz on Wednesday Sept 6 th Even if there is no formal quiz bring your clicker for participation questions HW 2/ Lab 2 are available and have been all week (I forgot to update the dates) Slides updated based on bugs found In particular some clarification around indirect addressing 56

57 Compare operations Important for conditional branch operations ; Usual branch operation CMPA #$FF ;First compare A to $FF BGT label ;If A is > $FF, branch to label 57

58 Compare/Test You can compare 2 numbers (<,>,=,>=,<=) by subtracting them and looking at the CCR register Description Compare Accumulators Compare Register with Memory Assembly mnemonic operation CBA Set CCR based on (A) (B) CBA Examples CMP<A B> addr Set CCR based on (<A B>) - (addr) CMPA #2 CMPB 2,X CP<X Y S D> addr Set CCR based on (<X Y S D>) - (addr):(addr+1) CPD $50 Test for Register for Zero Test for Memory for Zero TST<A B> Set CCR based on (<A B>) - $00 TSTA TSTB TST addr Set CCR based on (addr) - $00 TST 1,X TST $900 Sets CCR based on subtraction without actually storing the subtracted result 58

59 Other Arithmetic Instruction Types 1. Add 2. Subtract 3. Multiply 4. Divide 5. Compare/Test 6. Complement 7. Increment/Decrement 8. Min/Max Fairly Obvious. See Manual for Details 59

60 Instruction Classes 1. Data Transfer 2. Arithmetic Group 3. Logical 4. Transfer of control (branch/jump) 5. Machine Control 6. Special 60

61 Logical Instructions If Arithmetic is the heart, logical/control instructions are the brain 1. Boolean 2. Shift, rotate 3. Set/Clear 61

62 Boolean Operations Which instruction would you use to clear bits of the CCR? AND/OR/EOR Operate on <A B> with various addressing modes Detailed in manual Description Assembly mnemonic A: ORCC B: ANDCC P Useful to set and clear bits of CCR operation Examples ANDCC ANDCC immediate (CCR) (CCR) bitwise-and immediate ANDCC #$FE ORCC ORCC immediate (CCR) (CCR) bitwise-or immediate ORCC #$01 Only immediate There are also instructions to set/clear individual of the CCR example: CLC ; clears carry-bit 62

63 Rotate vs Arithmetic Shift vs Logical Shift Type Operation Assembly Rotate left ROL <addr A B> Actually same operation Rotate right Arithmetic shift left Arithmetic shift right Logical shift left Logical shift right ROR <addr A B> ASL <addr A B D> ASR <addr A B> LSL <addr A B D> LSR <addr A B D> 63

64 Clearing, Setting and Testing bit in Memory Mask is always a constant Description Assembly mnemonic operation Examples Bit Clear BCLR addr, mask (addr) (addr) bitwise-and mask BCLR $50, 01 Bit Set BSET addr, mask (addr) (addr) bitwise-or (mask) BSET 1, X, $FE Description Assembly mnemonic operation Examples Bit Test BIT<A B> addr Set CCR based on: (<A B>) bitwise-and (addr) BITA #1 BITB 900h Useful to test if bits in memory are set These instructions very useful for controlling peripherals 64

65 Instruction Classes 1. Data Transfer 2. Arithmetic Group 3. Logical 4. Transfer of control (branch/jump) 5. Machine Control 6. Special 65

66 Transfer of Control Instructions If Arithmetic is the heart, logical/control instructions are the brain for (int i = 0; i < n; ++i) { // do stuff } if (/**/) { // do stuff } else { // do other stuff } int result = foo(a); 1. Unconditional jumps/branches 2. Subroutine linkage (function calling) 3. Conditional branches 4. Compound test and branch 66

67 Unconditional Jumps and Branches Description Assembly mnemonic operation Examples Jump to PC JMP addr (PC) addr JMP $900 JMP 0,X JMP [0,Y] Branch to PC BRA rel8 (PC) (PC) + rel8 BRA label Long Branch to PC LBRA rel16 (PC) (PC) + rel16 LBRA label Jumps absolute. Branches relative. Use label, assembler figures out offset 67

68 How the branch offset is computed Encoded offset is dependent on the instruction length Remember: PC points to next instruction org 800h [01] 20FE 3 short bra short [04] 1820FFFC 5 long lbra long end Symbol Table 2-byte instruction 4-byte instruction LONG 0802 SHORT

69 Calling a function (aka subroutine) int main() { // do stuff foo(); // do stuff } Move PC to function Move PC Back void foo() { // do stuff } 69

70 Subroutine Linkage (Function Calling) Description Assembly mnemonic operation Examples Jump to subroutine JSR addr (SP) (SP) 2 ((SP)) (PCh) ((SP)+1) (PCl) (PC) addr Branch to subroutine BSR rel8 (SP) (SP) 2 ((SP)) (PCh) ((SP)+1) (PCl) (PC) (PC) + rel8 Return from subroutine RTS (PCh) ((SP)) (PCl) ((SP)+1) (SP) (SP) + 2 JSR $900 JSR 0,X JSR [D,Y] BSR label RTS 70

71 Simple Conditional Branches 8 Instructions where branch is based on C/N/V/Z bit clear/set Most useful: branch if equal/not equal More cycles if taken, less if not taken Description Assembly mnemonic operation Examples Branch if no equal Z =0 Branch if equal Z = 1 BNE rel8 LBNE rel16 BEQ rel8 LBEQ rel16 if Z = 0 (PC) (PC) + <rel8 rel16> else // No Nothing (effectively a NOP) if Z = 1 (PC) (PC) + <rel8 rel16> else // No Nothing (effectively a NOP) BNE label LBNE label BEQ label LBEQ label 71

72 More useful conditional branches (signed) Usually we want to test for (=,<=,<,>,>=) These instructions assumed signed numbers were subtracted Description Assembly mnemonic operation Examples Branch if greater than Z + [N Å V] = 0 Branch if less than or equal to Z + [N Å V] = 1 Branch if greater than or equal [N Å V] = 0 Branch if less than [N Å V] = 1 BGT rel8 LBGT rel16 BLE rel8 LBLE rel16 BGE rel8 LBGE rel16 BLT rel8 LBLT rel16 if [Z + [N Å V] == 0] (PC) (PC) + <rel8 rel16> else // No Nothing (effectively a NOP) if [Z + [N Å V] == 1] (PC) (PC) + <rel8 rel16> else // No Nothing (effectively a NOP) if [[N Å V] == 0] (PC) (PC) + <rel8 rel16> else // No Nothing (effectively a NOP) if [[N Å V] == 1] (PC) (PC) + <rel8 rel16> else // No Nothing (effectively a NOP) BGT label LBGT label BLE label LBLE label BGE label LBGE label BLT label LBLT label 72

73 Derivation of Signed Conditionals R 1 R 0 (R) M 1 M 0 (M)? C Z N V (R) = (M) (R) < (M) (R) > (M) (R) > (M) (R) > (M) (R) = (M) (R) > (M) (R) > (M) (R) < (M) (R) < (M) (R) = (M) (R) < (M) (R) < (M) (R) < (M) (R) > (M) (R) = (M) Z = 1 (R) = (M) Z + (N Å V) = 0 (R) > (M) N Å V = 1 (R) < (M) 73

74 Derivation of Signed Conditionals 0 1 N d N 2 0 C C d 7 d 6 d 12 d 13 d 15 d 14 d d 11 1 V V 10 0 V BLE condition = Z + (N Å V) BGT condition = (Z + (N Å V)) Z Z Z 74

75 Derivation of Signed Conditionals 0 0 N N 2 d 1 C C d d d 12 d 13 d 15 d 14 d V d 11 0 V 10 1 V BLT condition = N V + N V = N Å V BGE condition = (N Å V) Z Z Z 75

76 More useful conditional branches (unsigned) Branch if higher than C + Z = 0 Description Assembly mnemonic operation Examples Branch if lower than or the same C + Z = 1 Branch if higher than or the same C = 0 Branch if lower than C = 1 BHI rel8 LBHI rel16 BLS rel8 LBLS rel16 BHS rel8 LBHS rel16 BLO rel8 LBLO rel16 if [C + Z == 0] (PC) (PC) + <rel8 rel16> else // No Nothing (effectively a NOP) if [C + Z == 1] (PC) (PC) + <rel8 rel16> else // No Nothing (effectively a NOP) if [C == 0] (PC) (PC) + <rel8 rel16> else // No Nothing (effectively a NOP) if [C = 1] (PC) (PC) + <rel8 rel16> else // No Nothing (effectively a NOP) BHI label LBHI label BLS label LBLS label BHS label LBHS label BLO label LBLO label 76

77 Derivation of Unsigned Conditionals R 1 R 0 (R) M 1 M 0 (M)? C Z N V (R) = (M) (R) < (M) (R) < (M) (R) < (M) (R) > (M) (R) = (M) (R) < (M) (R) < (M) (R) > (M) (R) > (M) (R) = (M) (R) < (M) (R) > (M) (R) > (M) (R) > (M) (R) = (M) Z = 1 (R) = (M) C + Z = 0 (R) > (M) C = 1 (R) < (M) 77

78 Derivation of Unsigned Conditionals 0 1 N N 2 d 1 C C d d d 12 d 13 d 15 d 14 d V d 11 0 V 10 0 V BLS condition = C + Z BHI condition = (C + Z) Z Z Z 78

79 Derivation of Unsigned Conditionals 0 1 N N 2 d 1 C C d d d 12 d 13 d 15 d 14 d V d 11 0 Z Z Z V 10 0 V BLO condition = C BHS condition = C 79

80 Signed vs. Unsigned Conditionals Example: Difference between BGT and BHI ; signed conditional LDAA #$01 ;interpret as +1 CMPA #$FF ;interpret as -1 BGT label ;branch taken ; unsigned conditional LDAA #$01 ;interpret as 1 CMPA #$FF ;interpret as BHI label ;branch not taken 80

81 Bit Test and Branch Branch or no branch? MEM[100] = BRCLR 100, , 0011, label If all the high bits in the mask are 0 in memory, then branch A: Take branch P B: Do not take branch P Description Assembly mnemonic operation Examples Branch if bits clear BRCLR addr, mask8, rel8 if (addr) bitwise-and mask8 == 0 (PC) (PC) + <rel8 rel16> else // No Nothing (effectively a NOP) Branch if bits set BRSET addr, mask8, rel8 if (addr) bitwise-and mask8 == 0 (PC) (PC) + <rel8 rel16> else // No Nothing (effectively a NOP) BRCLR $50, 01,label BRCLR 0,X,$FF,label BRSET $50, 01,label BRSET 0,X,$FF,label If all the high bits in the mask are 1 in memory, then branch 81

82 Register Test and Branch Description Assembly mnemonic operation Examples Test Register and Branch if zero Test Register and branch if not zero TBEQ <ANY>, rel9 if [(r)== 0] (PC) (PC) + rel9 else // No Nothing (effectively a NOP) TBNE <ANY>, rel9 if [(r)!= 0] (PC) (PC) + rel9 else // No Nothing (effectively a NOP) TBEQ label TB label BLE label LBLE label 82

83 Increment/Decrement Register, Test for Zero and Conditionally Branch Common set of operations: created 1 special instruction to do all of them at once Any guess at when these are useful? These are very useful for loops Description Assembly mnemonic operation Examples Increment reg and branch if zero Increment reg and branch if not zero Decrement reg and branch if zero Decrement reg and branch if not zero IBEQ <ANY>, rel9 (<ANY>) (<ANY>) + 1 if [(<ANY>) == 0] (PC) (PC) + rel9 IBNE <ANY>, rel9 (<ANY>) (<ANY>) + 1 if [(<ANY>)!= 0] (PC) (PC) + rel9 DBEQ <ANY>, rel9 (<ANY>) (<ANY>) - 1 if [(<ANY>) == 0] (PC) (PC) + rel9 DBNE <ANY>, rel9 (<ANY>) (<ANY>) - 1 if [(<ANY>)!= 0] (PC) (PC) + rel9 IBEQ A, label IBNE X, label DBEQ SP, label DBNE Y, label 83

84 Instruction Classes 1. Data Transfer 2. Arithmetic Group 3. Logical 4. Transfer of control (branch/jump) 5. Machine Control 6. Special Not universal and can be complex. Will introduce as needed. 84