Condition Code Register. Microcomputer Architecture and Interfacing Colorado School of Mines Professor William Hoff

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1 Condition Code Register 1

2 Topics Condition code register Addition and subtraction instructions Conditional branches 2

3 Condition Code Register Condition code bits are automatically set by some instructions C bit is set if there is a carry out after an addition (or a borrow out after a subtraction) V bit is set if there was overflow after two s complement addition Only meaningful if the operation was on two s complement numbers Recall that overflow occurs if you add two positive numbers and get a negative, or two negative numbers and get a positive Z is set if the result is zero N is set if the result is negative (this is just the most significant bit) H bit is the carry out of bit position 3 ( half carry ) S,X,I are not automatically set by instructions (we will cover them later) 3

4 Example ADDA instruction from CPU12 Reference Manual 4

5 Example ldaa #$AA ; load accumulator A with $AA adda #$BC ; add $BC to accumulator A Carry out of most significant bit position Carry out of bit 3 position carries ($AA) ($BC) Result is $66 Resulting condition code bits? Resulting condition code bits H N Z V C means unchanged 5

6 Example ldaa #$73 ; load accumulator A with $73 adda #$FA ; add $FA to accumulator A Resulting condition code bits H N Z V C 6

7 Overflow Interpretation If adding unsigned numbers, C=1 means overflow If adding two s complement numbers, V=1 means overflow (a) If unsigned: Ok, no overflow, and C=0. N,V bits not meaningful b) If two s complement: Resulting condition code bits: N = 1 V = 1 C = 0 Z = 0 Too big; not in range Overflow, set V=1. 7

8 Example Resulting condition code bits: N = V = C = Z = 8

9 Add and subtract instructions 16 bit addition instructions also set N,Z,V,C bits Subtract instructions also set N,Z,V,C bits You can test for overflow the same way (C is actually borrow-out, not carry-out) adca,adcb are used to do multiprecision addition Table 1.7 Add and subtract instructions Mnemonic aba abx aby adca <opr> adcb <opr> adda <opr> addb <opr> addd <opr> Function Add B to A Add B to X Add B to Y Add with carry to A Add with carry to B Add without carry to A Add without carry to B Add without carry to D Subtract Instructions Operation A [A] + [B] X [X] + [B] Y [Y] + [B] A [A] + [opr] + C B [B] + [opr] + C A [A] + [opr] B [B] + [opr] D [D] + [opr] Mnemonic Function Operation sba sbca <opr> sbcb <opr> suba <opr> subb <opr> subd <opr> Add Instructions Subtract B from A Subtract with borrow from A Subtract with borrow from B Subtract memory from A Subtract memory from B Subtract memory from D A [A] - [B] A [A] - [opr] - C B [B] - [opr] - C A [A] - [opr] B [B] - [opr] D [D] - [opr] 9

10 Conditional Branches Unlike BRA (branch always), these instructions only branch if a condition is true If the condition isn t true, execution just continues on to the next instruction Examples Test if for overflow (unsigned) ldaa adda bcs N1 N2 OVERFLOW Test if a number is zero deca beq ZERO These instructions test whether a certain bit in the condition code register is set (or clear) Branch if clear Branch if set Bit BCC BCS C BNE BEQ Z BPL BMI N BVC BVS V Test if a number is positive subd M1 bpl POSITIVE 10

11 Conditional Branches (continued) These instructions test a combination of condition code bits Use these immediately after doing a subtraction; e.g., N1-N2 Example ldaa N1 suba N2 bhi N1BIGGER ; go here if N1>N2 (unsigned) If you look at the definition of BHI: It branches if C + Z = 0 (the + means logic OR ) This makes sense because if C=1 then N1<N2 and we don t want to branch Also if Z=1 then N1=N2 and we don t want to branch BGE ( ) BLT (<) 2 s comp BGT (>) BLE ( ) 2 s comp BHS ( ) BLO (<) Unsigned BHI (>) BLS ( ) Unsigned 11

12 Summary The Condition Code Register is one of the CPU registers The bits in the CCR are automatically set as a result of executing machine code instructions You can test those bits to do things like Detect if an instruction gave a zero result, or overflow Conditionally branch, if a CCR bit is set 12