5.1 The ISR: Overvieui. chapter

Transcription

1 chapter 5 The LC-3 n Chapter 4, we dscussed the basc components of a computer ts memory, ts processng unt, ncludng the assocated temporary storage (usually a set of regsters), nput and output devces, and the control unt that drects the actvty of all the unts (ncludng tself!). We also studed the sx phases of the nstructon cycle FETCH, DECODE, ADDRESS EVALUATON, OPERAND FETCH, EXECUTE, and STORE RESULT. We are now ready to ntroduce a "real" computer, the LC-3. To be more nearly exact, we are ready to ntroduce the nstructon set archtecture (SA) of the LC-3. We have already teased you wth a few facts about the LC-3 and a few of ts nstructons. Now we wll examne the SA of the LC-3 n a more comprehensve way. Recall from Chapter 1 that the SA s the nterface between what the software commands and what the hardware actually carres out. n ths chapter and n Chapters 8 and 9, we wll pont out the mportant features of the SA of the LC-3. You wll need these features to wrte programs n the LC-3's own language, that s, n the LC-3's machne language. A complete descrpton of the SA of the LC-3 s contaned n Appendx A. 5.1 The SR: Overveu The SA specfes all the nformaton about the computer that the software has to be aware of. n other words, the SA specfes everythng n the computer that s avalable to a programmer when he/she wrtes programs n the computer's own machne language. Thus, the SA also specfes everythng n the computer that

2 116 chapter 5 The LC-3 s avalable to someone who wshes to translate programs wrtten n a hgh-level language lke C or Pascal or Fortran or COBOL nto the machne language of the computer. The SA specfes the memory organzaton, regster set, and nstructon set, ncludng opcodes, data types, and addressng modes Memory Organzaton The LC-3 memory has an address space of 2 16 (.e., 65,536) locatons, and an addressablty of 16 bts. Not all 65,536 addresses are actually used for memory locatons, but we wll leave that dscusson for Chapter 8. Snce the normal unt of data that s processed n the LC-3 s 16 bts, we refer to 16 bts as one word, and we say the LC-3 s word-addressable Regsters Snce t usually takes far more than one machne cycle to obtan data from memory, the LC-3 provdes (lke almost all computers) addtonal temporary storage locatons that can be accessed n a sngle machne cycle. The most common type of temporary storage locatons and the one used n the LC-3 s the general purpose regster set. Each regster n the set s called a general purpose regster (GPR). Regsters have the same property as memory locatons n that they are used to store nformaton that can be retreved later. The number of bts stored n each regster s usually one word. n the LC-3, ths means 16 bts. Regsters must be unquely dentfable. The LC-3 specfes eght GPRs, each dentfed by a 3-bt regster number. They are referred to as RO, Rl,... R7. Fgure 5.1 shows a snapshot of the LC-3's regster set, sometmes called a regster fle, wth the eght values 1, 3, 5, 7, -2, -4, -6, and -8 stored n RO,... R7, respectvely. Regster 0 (RO) Regster 1 (R1) Regster 2 (R2) Regster 3 (R3) Regster 4 (R4) Regster 5 (R5) Regster 6 (R6) Regster 7 (R7) Fgure 5.1 The regster fle before the ADD nstructon

3 5.1 The SA: Overvew Regster 0 Regster 1 Regster 2 Regster 3 Regster 4 Regster 5 Regster 6 Regster 7 (RO) (Rl) (R2) (R3) (R4) (R5) (R6) (R7) Fgure 5.2 The regster fle after the ADD nstructon Recall that the nstructon to ADD the contents of RO to Rl and store the result n R2 s specfed as ADD R2 RO Rl where the two sources of the ADD nstructon are specfed n bts [8:6] and bts [2:0]. The destnaton of the ADD result s specfed n bts [11:9]. Fgure 5.2 shows the contents of the regster fle of Fgure 5.1 AFTER the nstructon ADD R2, Rl, RO s executed The nstructon Set An nstructon s made up of two thngs, ts opcode (what the nstructon s askng the computer to do) and ts operands (who the computer s expected to do t to). The nstructon set of an SA s defned by ts set of opcodes, data types, and addressng modes. The addressng modes determne where the operands are located. You have just seen an example of one opcode ADD and one addressng mode regster mode. The operaton the nstructon s askng the computer to perform s 2's complement nteger addton, and the locatons where the computer s expected to fnd the operands are the general purpose regsters Opcodes Some S As have a very large set of opcodes, one for each of a large number of tasks that a program may wsh to carry out. Other S A s have a very small set of opcodes. Some SAs have specfc opcodes to help wth processng scentfc calculatons. For example, the Hewlett Packard Precson Archtecture has an nstructon that performs a multply, followed by an add (A * B) + C on three source operands. Other SAs have nstructons that process vdeo mages obtaned from the World Wde Web. The ntel x86 SA added a number of nstructons ntel calls MMX

4 141 chapter 5 The LC-3 nstructons because they extend the SA to assst wth MultMeda applcatons that use the Web. Stll other S A s have specfc opcodes to help wth handlng the tasks of the operatng system. For example, the VAX archtecture, popular n the 1980s, had an opcode to save all the nformaton assocated wth one program that was runnng pror to swtchng to another program. Almost all computers prefer to use a long sequence of nstructons to ask the computer to carry out the task of savng all that nformaton. Although that sounds counterntutve, there s a ratonale for t. Unfortunately, the topc wll have to wat for a later semester. The decson as to whch nstructons to nclude or leave out of an SA s usually a hotly debated topc n a company when a new SA s beng specfed. The LC-3 SA has 15 nstructons, each dentfed by ts unque opcode. The opcode s specfed by bts [15:12] of the nstructon. Snce four bts are used to specfy the opcode, 16 dstnct opcodes are possble. However, the LC-3 SA specfes only 15 opcodes. The code 1101 has been left unspecfed, reserved for some future need that we are not able to antcpate today. There are three dfferent types of nstructons, whch means three dfferent types of opcodes: operates, data movement, and control. Operate nstructons process nformaton. Data movement nstructons move nformaton between memory and the regsters and between regsters/memory and nput/output devces. Control nstructons change the sequence of nstructons that wll be executed. That s, they enable the executon of an nstructon other than the one that s stored n the next sequental locaton n memory. Fgure 5.3 lsts all the nstructons of the LC-3, the bt encodng [15:12] for each opcode, and the format of each nstructon. The use of these formats wll be further explaned n Sectons 5.2, 5.3, and Data Types A data type s a representaton of nformaton such that the SA has opcodes that operate on that representaton. There are many ways to represent the same nformaton n a computer. That should not surprse us. n our daly lves, we regularly represent the same nformaton n many dfferent ways. For example, a chld, when asked how old he s, mght hold up three fngers, sgnfyng he s 3 years old. f the chld s partcularly precocous, he mght wrte the decmal dgt 3 to ndcate hs age. Or, f he s a CS or CE major at the unversty, he mght wrte , the 16-bt bnary representaton for 3. f he s a chemstry major, he mght wrte All four represent the same entty: 3. f the SA has an opcode that operates on nformaton represented by a data type, then we say the SA supports that data type. n Chapter 2, we ntroduced the only data type supported by the SA of the LC-3: 2's complement ntegers Addressng Modes An addressng mode s a mechansm for specfyng where the operand s located. An operand can generally be found n one of three places: n memory, n a regster, or as a part of the nstructon. f the operand s a part of the nstructon, we refer to t as a lteral or as an mmedate operand. The term lteral comes from the

5 5.1 The SA: Overvew ADD + ADD + AND + AND + BR JMP JSR JSRR LD + LD + LDR + LEA + NOT + RET RT ST ST STR TRAP reserved SR SR t t [ DR 1 1 DR 1 DR SR1 SR1 1 0 > mm5 00 SR DR SR1 1 mm5 PCoffset9 000 BaseR n z P DR DR " " DR " DR DR 000 BaseR PCoffsetH PCoffset9 r BaseR PCoffset offset6 \ -1 SR 111 PCoffset « SR 1 1 SR PCoffset9 - PCoffset P SR BaseR offset trapvect8 Fgure 5.3 Formats of the entre LC-3 nstructon set. NOTE: + ndcates nstructons that modfy condton codes

6 120 chapter 5 The LC-3 fact that the bts of the nstructon lterally form the operand. The term mmedate comes from the fact that we have the operand mmedately, that s, we don't have to look elsewhere for t. The LC-3 supports fve addressng modes: mmedate (or lteral), regster, and three memory addressng modes: PC-relatve, ndrect, and Base+offset. We wll see n Secton 5.2 that operate nstructons use two addressng modes: regster and mmedate. We wll see n Secton 5.3 that data movement nstructons use all fve modes Condton Codes One fnal tem wll complete our overvew of the SA of the LC-3: condton codes. Almost all SAs allow the nstructon sequencng to change on the bass of a prevously generated result. The LC-3 has three sngle-bt regsters that are set (set to 1) or cleared (set to 0) each tme one of the eght general purpose regsters s wrtten. The three sngle-bt regsters are called N 9 Z, and P, correspondng to ther meanng: negatve, zero, and postve. Each tme a GPR s wrtten, the N, Z, and P regsters are ndvdually set to 0 or 1, correspondng to whether the result wrtten to the GPR s negatve, zero, or postve. That s, f the result s negatve, the N regster s set, and Z and P are cleared. f the result s zero, Z s set and N and P are cleared. Fnally, f the result s postve, P s set and N and Z are cleared. Each of the three sngle-bt regsters s referred to as a condton code because the condton of that bt can be used by one of the control nstructons to change the executon sequence. The x86 and SPARC are two examples of SAs that use condton codes to do ths. We show how the LC-3 does t n Secton Operate nstructons Operate nstructons process data. Arthmetc operatons (lke ADD, SUB, MUL, and DV) and logcal operatons (lke AND, OR, NOT, XOR) are common examples. The LC-3 has three operate nstructons: ADD, AND, and NOT. The NOT (opcode = 1001) nstructon s the only operate nstructon that performs a unary operaton, that s, the operaton requres one source operand. The NOT nstructon bt-wse complements a 16-bt source operand and stores the result of ths operaton n a destnaton. NOT uses the regster addressng mode for both ts source and destnaton. Bts [8:6] specfy the source regster and bts [11:9] specfy the destnaton regster. Bts [5:0] must contan all s. f R5 ntally contans , after executng the followng nstructon: NOT R3 R5 R3 wll contan

7 5.2 Operate nstructons 121 RO R1 R2 R R4 R R6 R7 / / 1 6 '16 NOT Fgure 5.4 Data path relevant to the executon of NOT R3, R5 Fgure 5.4 shows the key parts of the data path that are used to perform the NOT nstructon shown here. Snce NOT s a unary operaton, only the A nput of the ALU s relevant. t s sourced from R5. The control sgnal to the ALU drects the ALU to perform the bt-wse complement operaton. The output of the ALU (the result of the operaton) s stored nto R3. The ADD (opcode = 0001) and AND (opcode = 0101) nstructons both perform bnary operatons; they requre two 16-bt source operands. The ADD nstructon performs a 2's complement addton of ts two source operands. The AND nstructon performs a bt-wse AND of each par of bts n ts two 16-bt operands. Lke the NOT, the ADD and AND use the regster addressng mode for one of the source operands and for the destnaton operand. Bts [8:6] specfy the source regster and bts [1L;9] specfy the destnaton regster (where the result wll be wrtten). The second source operand for both ADD and AND nstructons can be specfed by ether regster mode or as an mmedate operand. Bt [5] determnes whch s used. f bt [5] s 0, then the second source operand uses a regster, and bts [2:0] specfy whch regster. n that case, bts [4:3] are set to 0 to complete the specfcaton of the nstructon.

8 145 chapter 5 The LC-3 For example, f R4 contans the value 6 and R5 contans the value -18, then after the followng nstructon s executed ADD Rl R4 R5 Rl wll contan the value 12. f bt [5] s 1, the second source operand s contaned wthn the nstructon. n fact, the second source operand s obtaned by sgn-extendng bts [4:0] to 16 bts before performng the ADD or AND. Fgure 5.5 shows the key parts of the data path that are used to perform the nstructon ADD Rl, R4, #-2. Snce the mmedate operand n an ADD or AND nstructon must ft n bts [4:0] of the nstructon, not all 2's complement ntegers can be mmedate operands. Whch ntegers are OK (.e., whch ntegers can be used as mmedate operands)? R Fgure 5.5 Data path relevant to the executon of ADD Rl, R4, #-2

9 5.3 Data Movement nstructons 123 What docs the followng nstructon do? Example f) ANSWER: Regster 2 s cleared (.e., set to all ()s). Wha dues the followng nstructon do? Example lllllllll ANSWER: Regster ft s ncremented (.e., R6 R6 +1). Note that a regster can he used as a source and.dsn as a destnaton n he nstructon. Ths s true for all the nstructons n the.c-3. Recall that the 2's complement of a number can be obtaned by complementng the number and addng 1. Therefore, assumng the value*. A and B are m RO and R. what sequence of three nstructons perforns "A mnus B" and wrtes the result nto R2? Example 5.3 ANSWER: l > 7 ft Rl NOT(B) NOT Rl Rl 111 jjjlf jt^t? J ADD R2 Rl CJ R2 A +(-:;> ADD R2 RO Queston: What dstasteful result s be avoded? 5.3 Data Movement nstructons Data movement nstructons move nformaton between the general purpose regsters and memory, and between the regsters and the nput/output devces. We wll gnore for now the busness of movng nformaton from nput devces to regsters and from regsters to output devces. Ths wll be the major topc of Chapter 8 and an mportant part of Chapter 9 as well. n ths chapter, we wll confne ourselves to movng nformaton between memory and the general purpose regsters.

10 124 chapter 5 The LC-3 The process of movng nformaton from memory to a regster s called a load, and the process of movng nformaton from a regster to memory s called a store. n both cases, the nformaton n the locaton contanng the source operand remans unchanged. n both cases, the locaton of the destnaton operand s overwrtten wth the source operand, destroyng the pror value n the destnaton locaton n the process. The LC-3 contans seven nstructons that move nformaton: LD, LDR, LD, LEA, ST, STR, and ST. The format of the load and store nstructons s as follows: opcode DR or SR Addr Gen bts ~ Data movement nstructons requre two operands, a source and a destnaton. The source s the data to be moved; the destnaton s the locaton where t s moved to. One of these locatons s a regster, the second s a memory locaton or an nput/output devce. As we sad earler, n ths chapter the second operand wll be assumed to be n memory. We wll save for Chapter 8 the cases where the second operand specfes an nput or output devce. Bts [11:9] specfy one of these operands, the regster. f the nstructon s a load, DR refers to the destnaton regster that wll contan the value after t s read from memory (at the completon of the nstructon cycle). f the nstructon s a store, SR refers to the regster that contans the value that wll be wrtten to memory. Bts [8:0] contan the address generaton bts. That s, bts [8:0] encode nformaton that s used to compute the 16-bt address of the second operand. n the case of the LC-3's data movement nstructons, there are four ways to nterpret bts [8:0]. They are collectvely called addressng modes. The opcode specfes how to nterpret bts [8:0]. That s, the LC-3's opcode specfes whch addressng mode should be used to obtan the operand from bts [8:0] of the nstructon PC-Relatve Mode LD (opcode = 0010) and ST (opcode = 0011) specfy the PC-relatve addressng mode. Ths addressng mode s so named because bts [8:0] of the nstructon specfy an offset relatve to the PC. The memory address s computed by sgnextendng bts [8:0] to 16 bts, and addng the result to the ncremented PC. The ncremented PC s the contents of the program counter after the FETCH phase; that s, after the PC has been ncremented. f a load, the memory locaton correspondng to the computed memory address s read, and the result loaded nto the regster specfed by bts [11:9] of the nstructon. f the nstructon LD R2 xlaf s located at x4018, t wll cause the contents of x3fc8 to be loaded nto R2.

11 5.3 Data Movement nstructons R LD R2 x1af RO R1 R PC ' R[8:0] SEXT R 3 R4 R5 R6 R7 ' 16 " V ADD / ' 16 MAR 16 MDR Fgure 5.6 Data path relevant to executon of LD R2, xlaf Fgure 5.6 shows the relevant parts of the data path requred to execute ths nstructon. The three steps of the LD nstructon are dentfed. n step 1, the ncremented PC (x4019) s added to the sgn-extended value contaned n R[8:0] (xffaf), and the result (x3fc8) s loaded nto the MAR. n step 2, memory s read and the contents of x3fc8 are loaded nto the MDR. Suppose the value stored n x3fc8 s 5. n step 3, the value 5 s loaded nto R2, completng the nstructon cycle. Note that the address of the memory operand s lmted to a small range of the total memory. That s, the address can only be wthn +256 or 255 locatons of the LD or ST nstructon snce the PC s ncremented before the offset s added. Ths s the range provded by the sgn-extended value contaned n bts [8:0] of the nstructon ndrect Mode LD (opcode 1010) and ST (opcode = 1011) specfy the ndrect addressng mode. An address s frst formed exactly the same way as wth LD and ST. However, nstead of ths address beng the address of the operand to be loaded or stored, t contans the address of the operand to be loaded or stored. Hence the

12 149 chapter 5 The LC-3 name ndrect. Note that the address of the operand can be anywhere n the computer's memory, not just wthn the range provded by bts [8:0] of the nstructon as s the case for LD and ST. The destnaton regster for the LD and the source regster for ST, lke all the other loads and stores, are specfed n bts [11:9] of the nstructon. f the nstructon LD R3 xlcc s n X4A1B, and the contents of x49e8 s x2110, executon of ths nstructon results n the contents of x2110 beng loaded nto R3. Fgure 5.7 shows the relevant parts of the data path requred to execute ths nstructon. As s the case wth the LD and ST nstructons, the frst step conssts of addng the ncremented PC (x4alc) to the sgn-extended value contaned n R[8:0] (xffcc), and the result (x49e8) loaded nto the MAR. n step 2, memory s read and the contents of x49e8 (x2110) s loaded nto the MDR. n step 3, snce x2110 s not the operand, but the address of the operand, t s loaded nto the MAR. n step 4, memory s agan read, and the MDR agan loaded. Ths tme the MDR s loaded wth the contents of x2110. Suppose the value 1 s stored n memory locaton x2110. n step 5, the contents of the MDR (.e., 1) are loaded nto R3, completng the nstructon cycle. R LD R3 x1cc RO R1 R2 ' R[8:0] R PC SEXT 16 xffcc R4 R5 R6 R7 16 ADD t ' MAR MDR x2110 (D(D Fgure 5.5 Data path relevant to the executon of ADD Rl, R4, #-2

13 5.3.3 Base+offset Mode 5.3 Data Movement nstructons 127 LDR (opcode = 0110) and STR (opcode = 0111) specfy the Base+offset addressng mode. The Base+offset mode s so named because the address of the operand s obtaned by addng a sgn-extended 6-bt offset to a base regster. The 6-bt offset s lterally taken from the nstructon, bts [5:0]. The base regster s specfed by bts [8:6] of the nstructon. The Base+offset addressng uses the 6-bt value as a 2's complement nteger between 32 and +31. Thus t must frst be sgn-extended to 16 bts before t s added to the base regster. f R2 contans the 16-bt quantty x2345, the nstructon LDR R1 R2 xld loads R1 wth the contents of x2362. Fgure 5.8 shows the relevant parts of the data path requred to execute ths nstructon. Frst the contents of R2 (x2345) are added to the sgn-extended value contaned n R[5:0] (xoold), and the result (x2362) s loaded nto the MAR. Second, memory s read, and the contents of x2362 are loaded nto the MDR. Suppose the value stored n memory locaton x2362 s xofof. Thrd, and fnally, the contents of the MDR (n ths case, xofof) are loaded nto Rl R LDR R1 R2 x1d ' R[5:0] SEXT /16 X001D R0 R1 R2 R3 R4 R5 R6 R ADD / '16 MAR '16 MDR Fgure 5.8 Data path relevant to the executon of LDR Rl, R2, xld

14 128 chapter 5 The LC-3 Note that the Base+offset addressng mode also allows the address of the operand to be anywhere n the computer's memory mmedate Mode The fourth and last addressng mode used by the data movement nstructons s the mmedate (or, lteral) addressng mode. t s used only wth the load effectve address (LEA) nstructon. LEA (opcode =1110) loads the regster specfed by bts [11:9] of the nstructon wth the value formed by addng the ncremented program counter to the sgn-extended bts [8:0] of the nstructon. The mmedate addressng mode s so named because the operand to be loaded nto the destnaton regster s obtaned mmedately, that s, wthout requrng any access of memory. The LEA nstructon s useful to ntalze a regster wth an address that s very close to the address of the nstructon dong the ntalzng. f memory locaton x4018 contans the nstructon LEA R5, # - 3, and the PC contans x4018, LEA R5-3 R5 wll contan x4016 after the nstructon at x4018 s executed. Fgure 5.9 shows the relevant parts of the data path requred to execute the LEA nstructon. Note that no access to memory s requred to obtan the value to be loaded. 15 R0 R LEA R5 x1 FD R1 R2 R[8:0] R3 PC SEXT R4 R5 R6 R Fgure 5.5 Data path relevant to the executon of ADD Rl, R4, #-2

15 5.3 Data Movement nstructons 129 Agan, LEA s the only load nstructon that does not access memory to obtan the nformaton t wll load nto the DR. t loads nto the DR the address formed from the ncremented PC and the address generaton bts of the nstructon An Example We conclude our study of addressng modes wth a comprehensve example. Assume the contents of memory locatons x30f6 through x30fc are as shown n Fgure 5.10, and the PC contans x30f6. We wll examne the effects of carryng out the nstructon cycle seven consecutve tmes. The PC ponts ntally to locaton x30f6. That s, the content of the PC s the address x30f6. Therefore, the frst nstructon to be executed s the one stored n locaton x30f6. The opcode of that nstructon s 1110, whch dentfes the load effectve address nstructon (LEA). LEA loads the regster specfed by bts [11:9] wth the address formed by sgn-extendng bts [8:0] of the nstructon and addng the result to the ncremented PC. The 16-bt value obtaned by sgnextendng bts [8:0] of the nstructon s xfffd. The ncremented PC s x30f7. Therefore, at the end of executon of the LEA nstructon, Rl contans x30f4, and the PC contans x30f7. The second nstructon to be executed s the one stored n locaton x30f7. The opcode 0001 dentfes the ADD nstructon, whch stores the result of addng the contents of the regster specfed n bts [8:6] to the sgn-extended mmedate n bts [4:0] (snce bt [5] s 1) n the regster specfed by bts [11:9]. Snce the prevous nstructon loaded x30f4 nto Rl, and the sgn-extended mmedate value s xoooe, the value to be loaded nto R2 s x3102. At the end of executon of ths nstructon, R2 contans x3102, and the PC contans x30f8. Rl stll contans x30f4. The thrd nstructon to be executed s stored n x30f8. The opcode 0011 specfes the ST nstructon, whch stores the contents of the regster specfed by bts [11:9] of the nstructon nto the memory locaton whose address s computed usng the PC-relatve addressng mode. That s, the address s computed by addng the ncremented PC to the 16-bt value obtaned by sgn-extendng bts [8:0] of the nstructon. The 16-bt value obtaned by sgn-extendng bts [8:0] of the nstructon s xfffb. The ncremented PC s x30f9. Therefore, at the end of Address x30f6 x30f7 x30f8 x30f9 x30fa x30fb x30fc Fgure Addressng mode example Rl<- PC-3 R2<- Rl+14 M [x30f4]<- R2 R2<- 0 R2<- R2+5 M[Rl+14]<- R2 R3<- M[M[x3F04]]

16 130 chapter 5 The LC-3 executon of the ST nstructon, memory locaton x30f4 contans x3102, and the PC contans x30f9. At x30f9, we fnd the opcode 0101, whch represents the AND nstructon. After executon, R2 contans the value 0, and the PC contans x30fa. At x30fa, we fnd the opcode 0001, sgnfyng the ADD nstructon. After executon, R2 contans the value 5, and the PC contans x30fb. At x30fb, we fnd the opcode 0111, sgnfyng the STR nstructon. The STR nstructon (lke the LDR nstructon) uses the Base+offset addressng mode. The memory address s obtaned by addng the contents of the regster specfed by bts [8:61 (the BASE regster) to the sgn-extended offset contaned n bts [5:0]. n ths case, bts [8:6] specfy Rl. The contents of R1 are stll x30f4. The 16-bt sgn-extended offset s xoooe. Snce x30f4 + xoooe s x3102, the memory address s x3102. The STR nstructon stores nto x3102 the contents of the regster specfed by bts [11:9], that s, R2. Recall that the prevous nstructon (at x30fa) stored the value 5 nto R2. Therefore, at the end of executon of ths nstructon, locaton x3102 contans the value 5, and the PC contans x30fc. At x30fc, we fnd the opcode 1010, sgnfyng the LD nstructon. The LD nstructon (lke the ST nstructon) uses the ndrect addressng mode. The memory address s obtaned by frst formng an address as s done n the PCrelatve addressng mode. n ths case, the 16-bt value obtaned by sgn-extendng bts [8:0] of the nstructon s xfff7. The ncremented PC s x30fd. Ther sum s x30f4, whch s the address of the operand address. Memory locaton x30f4 contans x3102. Therefore, x3102 s the operand address. The LD nstructon loads the value found at ths address (n ths case 5) nto the regster dentfed by bts [11:9] of the nstructon (n ths case R3). At the end of executon of ths nstructon, R3 contans the value 5 and the PC contans x30fd. 5.4 Control nstructons Control nstructons change the sequence of the nstructons that are executed. f there were no control nstructons, the next nstructon fetched after the current nstructon fnshes would be the nstructon located n the next sequental memory locaton. As you know, ths s because the PC s ncremented n the FETCH phase of each nstructon. We wll see momentarly that t s often useful to be able to break that sequence. The LC-3 has fve opcodes that enable ths sequental flow to be broken: condtonal branch, uncondtonal jump, subroutne (sometmes called functon) call, TRAP, and return from nterrupt. n ths secton, we wll deal almost exclusvely wth the most common control nstructon, the condtonal branch. We wll also ntroduce the uncondtonal jump and the TRAP nstructon. The TRAP nstructon s partcularly useful because, among other thngs, t allows a programmer to get nformaton nto and out of the computer wthout fully understandng the ntrcaces of the nput and output devces. However, most of the dscusson of the TRAP nstructon and all of the dscusson of the subroutne call and the return from nterrupt we wll leave for Chapters 9 and 10.

17 5.4.1 Condtonal Branches 5.4 Control nstructons 154 The format of the condtonal branch nstructon (opcode = 0000) s as follows: N z p PCoffset Bts [11], [10], and [9] correspond to the three condton codes dscussed n Secton Recall that n the LC-3, all nstructons that wrte values nto the general purpose regsters set the three condton codes (.e., the sngle-bt regsters N, Z, P) n accordance wth whether the value wrtten s negatve, zero, or postve. These nstructons are ADD, AND, NOT, LD, LD, LDR, and LEA. The condton codes are used by the condtonal branch nstructon to determne whether to change the nstructon flow; that s, whether to depart from the usual sequental executon of nstructons that we get as a result of ncrementng PC durng the FETCH phase of each nstructon. The nstructon cycle s as follows: FETCH and DECODE are the same for all nstructons. The PC s ncremented durng FETCH. The EVALUATE ADDRESS phase s the same as that for LD and ST: the address s computed by addng the ncremented PC to the 16-bt value formed by sgn-extendng bts [8:0] of the nstructon. Durng the EXECUTE phase, the processor examnes the condton codes whose correspondng bts n the nstructon are 1. That s, f bt [ 11 ] s 1, condton code N s examned. f bt [10] s 1, condton code Z s examned. f bt [9] s 1, condton code P s examned. f any of bts [11:9] are 0, the correspondng condton codes are not examned. f any of the condton codes that are examned are n state 1, then the PC s loaded wth the address obtaned n the EVALUATE ADDRESS phase. f none of the condton codes that are examned are n state 1, the PC s left unchanged. n that case, n the next nstructon cycle, the next sequental nstructon wll be fetched. For example, f the last value loaded nto a general purpose regster was 0, then the current nstructon (located at x4027) shown here BR n z p xod9 would load the PC wth x4101, and the next nstructon executed would be the one at x4101, rather than the nstructon at x4028. Fgure 5.11 shows the data path elements that are requred to execute ths nstructon. Note the logc requred to determne whether the sequental nstructon flow should be broken. n ths case the answer s yes, and the PC s loaded wth x4101, replacng x4028, whch had been loaded durng the FETCH phase of the condtonal branch nstructon. f all three bts [11:9] are 1, then all three condton codes are examned. n ths case, snce the last result stored nto a regster had to be ether negatve, zero, or postve (there are no other choces), one of the three condton codes must be n state 1. Snce all three are examned, the PC s loaded wth the address obtaned n the EVALUATE ADDRESS phase. We call ths an wrccondtonal branch snce

18 155 chapter 5 The LC-3 Yes! Fgure 5.11 Data path relevant to the executon of BRz xod9 the nstructon flow s changed uncondtonally, that s, ndependent of the data that s beng processed. For example, f the followng nstructon, BR n xl85 located at x507b, s executed, the PC s loaded wth x5001. What happens f all three bts [11:9] n the BR nstructon are 0? An Example We are ready to show by means of a smple example the value of havng control nstructons n the nstructon set. Suppose we know that the 12 locatons x3100 to x310b contan ntegers, and we wsh to compute the sum of these 12 ntegers.

19 5.4 Control nstructons 133 Fgure 5.12 An algorthm for addng 12 ntegers A flowchart for an algorthm to solve the problem s shown n Fgure Frst, as n all algorthms, we must ntalze our varables. That s, we must set up the ntal values of the varables that the computer wll use n executng the program that solves the problem. There are three such varables: the address of the next nteger to be added (assgned to Rl), the runnng sum (assgned to R3), and the number of ntegers left to be added (assgned to R2). The three varables are ntalzed as follows: The address of the frst nteger to be added s put n Rl. R3, whch wll keep track of the runnng sum, s ntalzed to 0. R2, whch wll keep track of the number of ntegers left to be added, s ntalzed to 12. Then the process of addng begns. The program repeats the process of loadng nto R4 one of the 12 ntegers, and addng t to R3. Each tme we perform the ADD, we ncrement Rl so t wll pont to (.e., contan the address of) the next number to be added and decrement R2 so we wll know how many numbers stll need to be added. When R2 becomes zero, the Z condton code s set, and we can detect that we are done. The 10-nstructon program shown n Fgure 5.13 accomplshes the task. The detals of the program executon are as follows: The program starts wth PC = x3000. The frst nstructon (at locaton x3000) loads Rl wth the address x3100. (The ncremented PC s x3001; the sgn-extended PCoffset s xooff.) The nstructon at x3001 clears R3. R3 wll keep track of the runnng sum, so t must start off wth the value 0. As we sad prevously, ths s called ntalzng the SUM to zero. The nstructons at x3002 and x3003 set the value of R2 to 12, the number of ntegers to be added. R2 wll keep track of how many numbers have already been added. Ths wll be done (by the nstructon contaned n x3008) by decrementng R2 after each addton takes place. The nstructon at x3004 s a condtonal branch nstructon. Note that bt [10] s a 1. That means that the Z condton code wll be examned. f t s set, we know

20 134 chapter 5 The LC-3 Address x3000 x3001 x3002 x3003 x3004 x3005 x3006 x3007 x3008 x Rl< R3 <- 0 R2 < - 0 R2 <- 12 BRz x300a R4 <- M [Rl] R3 <- R3+R4 Rl <- Rl+1 R2 <- R2-1 BRnzp x3004 Fgure 5.13 A program that mplements the algorthm of Fgure 5.12 R2 must have just been decremented to 0. That means there are no more numbers to be added and we are done. f t s clear, we know we stll have work to do and we contnue. The nstructon at x3005 loads the contents of x3100 (.e., the frst nteger) nto R4, and the nstructon at x3006 adds t to R3. The nstructons at x3007 and x3008 perform the necessary bookkeepng. The nstructon at x3007 ncrements Rl, so Rl wll pont to the next locaton n memory contanng an nteger to be added (n ths case, x3101). The nstructon at x3008 decrements R2, whch s keepng track of the number of ntegers stll to be added, as we have already explaned, and sets the N, Z, and P condton codes. The nstructon at x3009 s an uncondtonal branch, snce bts [11:9] are all 1. t loads the PC wth x3004. t also does not affect the condton codes, so the next nstructon to be executed (the condtonal branch at x3004) wll be based on the nstructon executed at x3008. Ths s worth sayng agan. The condtonal branch nstructon at x3004 follows the nstructon at x3009, whch does not affect condton codes, whch n turn follows the nstructon at x3008. Thus, the condtonal branch nstructon at x3004 wll be based on the condton codes set by the nstructon at x3008. The nstructon at x3008 sets the condton codes dependng on the value produced by decrementng R2. As long as there are stll ntegers to be added, the ADD nstructon at x3008 wll produce a value greater than zero and therefore clear the Z condton code. The condtonal branch nstructon at x3004 examnes the Z condton code. As long as Z s clear, the PC wll not be affected, and the next nstructon cycle wll start wth an nstructon fetch from x3005. The condtonal branch nstructon causes the executon sequence to follow: x3000, x3001, x3002, x3003, x3004, x3005, x3006, x3007, x3008, x3009, x3004, x3005, x3006, x3007, x3008, x3009, x3004, x3005, and so on untl the value n R2 becomes 0. The next tme the condtonal branch nstructon at x3004 s executed, the PC s loaded wth x300a, and the program contnues at x300a wth ts next actvty. Fnally, t s worth notng that we could have wrtten a program to add these 12 ntegers wthout any control nstructons. We stll would have needed the LEA

21 5.4 Control nstructons 158 nstructon n x3000 to ntalze Rl. We would not have needed the nstructon at x3001 to ntalze the runnng sum, nor the nstructons at x3002, and x3003 to ntalze the number of ntegers left to be added. We could have loaded the contents of x3100 drectly nto R3, and then repeatedly (by ncrementng Rl, loadng the next nteger nto R4, and addng R4 to the runnng sum n R3) added the remanng 11 ntegers. After the addton of the twelfth nteger, we would go on to the next task, as does the example of Fgure 5.13 wth the branch nstructon n x3004. Unfortunately, nstead of a 10-nstructon program, we would have had a 35- nstructon program. Moreover, f we had wshed to add 100 ntegers wthout any control nstructons nstead of 12, we would have had a 299-nstructon program nstead of 10. The control nstructons n the example of Fgure 5.13 permt the reuse of sequences of code by breakng the sequental nstructon executon flow Two Methods for Loop Control We use the term loop to descrbe a sequence of nstructons that get executed agan and agan under some controllng mechansm. The example of addng 12 ntegers contans a loop. Each tme the body of the loop executes, one more nteger s added to the runnng total, and the counter s decremented so we can detect whether there are any more ntegers left to add. Each tme the loop body executes s called one teraton of the loop. There are two common methods for controllng the number of teratons of a loop. One method we just examned: the use of a counter. f we know we wsh to execute a loop n tmes, we smply set a counter to n, then after each executon of the loop, we decrement the counter and check to see f t s zero. f t s not zero, we set the PC to the start of the loop and contnue wth another teraton. A second method for controllng the number of executons of a loop s to use a sentnel. Ths method s partcularly effectve f we do not know ahead of tme how many teratons we wll want to perform. Each teraton s usually based on processng a value. We append to our sequence of values to be processed a value that we know ahead of tme can never occur (.e., the sentnel). For example, f we are addng a sequence of numbers, a sentnel could be a # or a *, that s, somethng that s not a number. Our loop test s smply a test for the occurrence of the sentnel. When we fnd t, we know we are done Example: Addng a Column of Numbers Usng a Sentnel Suppose n our example of Secton 5.4.2, we know the values stored n locatons x3100 to x310b are all postve. Then we could use any negatve number as a sentnel. Let's say the sentnel stored at memory address x310c s 1. The resultng flowchart for the program s shown n Fgure 5.14 and the resultng program s shown n Fgure As before, the nstructon at x3000 loads Rl wth the address of the frst value to be added, and the nstructon at x3001 ntalzes R3 (whch keeps track of the sum) to 0.

22 136 chapter 5 The LC-3 1 R1 <- x3100 R3 <-0 R4 <- M[R1] R3 <- R3 + R4 ncrement R1 R4 <- M[R1] Fgure 5.14 An algorthm showng the use of a sentnel for loop control Address x x x x x x x x Rl<- x3100 R3 < - 0 R4 <- M[Rl] BRn x3008 R3 <- R3+R4 Rl <- Rl+1 R4 <- MtRl] BRnzp x3003 Fgure 5.15 A program that mplements the algorthm of Fgure 5.14 At x3002, we load the contents of the next memory locaton nto R4. f the sentnel s loaded, the N condton code s set. The condtonal branch at x3003 examnes the N condton code, and f t s set, sets PC to x3008 and onto the next task to be done. f the N condton code s clear, R4 must contan a vald number to be added. n ths case, the number s added to R3 (x3004), Rl s ncremented to pont to the next memory locaton (x3005), R4 s loaded wth the contents of the next memory locaton (x3006), and the PC s loaded wth x3003 to begn the next teraton (x3007) The J MP nstructon The condtonal branch nstructon, for all ts capablty, does have one unfortunate lmtaton. The next nstructon executed must be wthn the range of addresses that can be computed by addng the ncremented PC to the sgn-extended offset

23 5.4 Control nstructons 137 obtaned from bts [8:0] of the nstructon. Snce bts [8:0] specfy a 2's complement nteger, the next nstructon executed after the condtonal branch can be at most +256 or 255 locatons from the branch nstructon tself. What f we would lke to execute next an nstructon that s 1,000 locatons from the current nstructon. We cannot ft the value 1,000 nto the 9-bt feld; ergo, the condtonal branch nstructon does not work. The LC-3 SA does provde an nstructon JMP (opcode = 1100) that can do the job. An example follows: JMP R2 The JMP nstructon loads the PC wth the contents of the regster specfed by bts [8:6] of the nstructon. f ths JMP nstructon s located at address x4000, R2 contans the value x6600, and the PC contans x4000, then the nstructon at x4000 (the JMP nstructon) wll be executed, followed by the nstructon located at x6600. Snce regsters contan 16 bts, the full address space of memory, the JMP nstructon has no lmtaton on where the next nstructon to be executed must resde The TRAP nstructon Fnally, because t wll be useful long before Chapter 9 to get data nto and out of the computer, we ntroduce the TRAP nstructon now. The TRAP (opcode = 1111) nstructon changes the PC to a memory address that s part of the operatng system so that the operatng system wll perform some task n behalf of the program that s executng. n the language of operatng system jargon, we say the TRAP nstructon nvokes an operatng system SERVCE CALL. Bts [7:0] of the TRAP nstructon form the trapvector, whch dentfes the servce call that the program wshes the operatng system to perform. Table A.2 contans the trapvectors for all the servce calls that we wll use wth the LC-3 n ths book trapvector Once the operatng system s fnshed performng the servce call, the program counter s set to the address of the nstructon followng the TRAP nstructon, and the program contnues. n ths way, a program can, durng ts executon, request servces from the operatng system and contnue processng after each such servce s performed. The servces we wll requre for now are * nput a character from the keyboard (trapvector = x23). * Output a character to the montor (trapvector = x21). * Halt the program (trapvector = x25). Exactly how the LC-3 carres out the nteracton between operatng system and executng programs s an mportant topc for Chapter 9.

24 138 chapter 5 The LC Another Example: Countng Occurrences of a Character We wll fnsh our ntroducton to the SA of the LC-3 wth another example program. We would lke to be able to nput a character from the keyboard and then count the number of occurrences of that character n a fle. Fnally, we would lke to dsplay that count on the montor. We wll smplfy the problem by assumng that the number of occurrences of any character that we would be nterested n s small. That s, there wll be at most nne occurrences. Ths smplfcaton allows us to not have to worry about complex converson routnes between the bnary count and the ASC dsplay on the montor a subject we wll get nto n Chapter 10, but not today. Fgure 5.16 s a flowchart of the algorthm that solves ths problem. Note that each step s expressed both n Englsh and also (n parentheses) n terms of an LC-3 mplementaton. The frst step s (as always) to ntalze all the varables. Ths means provdng startng values (called ntal values) for R0, Rl, R2, and R3, the four regsters the computer wll use to execute the program that wll solve the problem. R2 wll keep track of the number of occurrences; n Fgure 5.16, t s referred to as count. t s ntalzed to zero. R3 wll pont to the next character n the fle that s beng examned. We refer to t as ponter snce t contans the address of the locaton where the next character of the fle that we wsh to examne resdes. The ponter s ntalzed wth the address of the frst character n the fle. R0 wll hold the character that s beng counted; we wll nput that character from the keyboard and put t n R0. Rl wll hold, n turn, each character that we get from the fle beng examned. We should also note that there s no requrement that the fle we are examnng be close to or far away from the program we are developng. For example, t s perfectly reasonable for the program we are developng to start at x3000, and the fle we are examnng to start at x9000. f that were the case, n the ntalzaton process, R3 would be ntalzed to x9000. The next step s to count the number of occurrences of the nput character. Ths s done by processng, n turn, each character n the fle beng examned, untl the fle s exhausted. Processng each character requres one teraton of a loop. Recall from Secton that there are two common methods for keepng track of teratons of a loop. We wll use the sentnel method, usng the ASC code for EOT (End of Text) ( ) as the sentnel. A table of ASC codes s n Appendx E. n each teraton of the loop, the contents of Rl are frst compared to the ASC code for EOT. f they are equal, the loop s exted, and the program moves on to the fnal step, dsplayng on the screen the number of occurrences. f not, there s work to do. Rl (the current character under examnaton) s compared to R0 (the character nput from the keyboard). f they match, R2 s ncremented. n ether case, we get the next character, that s, R3 s ncremented, the next character s loaded nto Rl, and the program returns to the test that checks for the sentnel at the end of the fle. When the end of the fle s reached, all the characters have been examned, and the count s contaned as a bnary number n R2. n order to dsplay the

25 5.5 Another Example: Countng Occurrences of a Character 139 Fgure 5.16 An algorthm to count occurrences of a character

26 140 chapter 5 The LC-3 Address x3000 x3001 x3002 x3003 x3004 x3005 x3006 x3007 x3008 x3009 x300a x300b x300c x300d x300e x300f x3010 x3011 x3012 x Startng address of fle R2 < - 0 R3 <- M[x3012] TRAP x23 Rl <- M[R3] R4 <- Rl-4 BRz x300e Rl <- NOT Rl Rl <- Rl + 1 Rl <- Rl + R0 BRnp x300b R2 < - R2 + 1 R3 <- R3 + 1 Rl <- M[R3] BRnzp x3004 R0 <- M[x3013] R0 < - R0 + R2 TRAP x21 TRAP x25 ASC TEMPLATE Fgure 5.17 A machne language program that mplements the algorthm of Fgure 5.16 count on the montor, t s necessary to frst convert t to an ASC code. Snce we have assumed the count s less than 10, we can do ths by puttng a leadng 0011 n front of the 4-bt bnary representaton of the count. Note n Fgure E.2 the relatonshp between the bnary value of each decmal dgt between 0 and 9 and ts correspondng ASC code. Fnally, the count s output to the montor, and the program termnates. Fgure 5.17 s a machne language program that mplements the flowchart of Fgure Frst the ntalzaton steps. The nstructon at x3000 clears R2 by ANDng t wth xoooo; the nstructon at x3001 loads the value stored n x3012 nto R3. Ths s the address of the frst character n the fle that s to be examned for occurrences of our character. Agan, we note that ths fle can be anywhere n memory. Pror to startng executon at x3000, some sequence of nstructons must have stored the frst address of ths fle n x3012. Locaton x3002 contans the TRAP nstructon, whch requests the operatng system to perform a servce call on behalf of ths program. The functon requested, as dentfed by the 8-bt trapvector (or, x23), s to nput a character from the keyboard and load t nto R0. Table A.2 lsts trapvectors for all operatng system servce calls that can be performed on behalf of a user program. Note (from Table A.2) that x23 drects the operatng system to perform the servce call that reads the next character struck and loads t nto R0. The nstructon at x3003 loads the character ponted to by R3 nto Rl. Then the process of examnng characters begns. We start (x3004) by subtractng 4 (the ASC code for EOT) from Rl, and storng t n R4. f the result

27 5.6 The Data Path Revsted 141 s zero, the end of the fle has been reached, and t s tme to output the count. The nstructon at x3005 condtonally branches to x300e, where the process of outputtng the count begns. f R4 s not equal to zero, the character n Rl s legtmate and must be examned. The sequence of nstructons at locatons x3006, x3007, and x3008 determne f the contents of Rl and RO are dentcal. The sequence of nstructons perform the followng operaton: RO + (NOT (Rl) + 1) Ths produces all zeros only f the bt patterns of Rl and RO are dentcal. f the bt patterns are not dentcal, the condtonal branch at x3009 branches to x300b, that s, t skps the nstructon x300a, whch ncrements R2, the counter. The nstructon at x300b ncrements R3, so t wll pont to the next character n the fle beng examned, the nstructon at x300c loads that character nto Rl, and the nstructon at x300d uncondtonally takes us back to x3004 to start processng that character. When the sentnel (EOT) s fnally detected, the process of outputtng the count begns (at x300e). The nstructon at x300e loads nto R0, and the nstructon at x300f adds the count to R0. Ths converts the bnary representaton of the count (n R2) to the ASC representaton of the count (n R0). The nstructon at x3010 nvokes a TRAP to the operatng system to output the contents of R0 on the montor. When that s done and the program resumes executon, the nstructon at x3011 nvokes a TRAP nstructon to termnate the program. 5.6 The Data Path Revsted Before we leave Chapter 5, let us revst the data path dagram that we frst encountered n Chapter 3 (Fgure 3.33). Now we are ready to examne all the structures that are needed to mplement the LC-3 SA. Many of them we have seen earler n ths chapter n Fgures 5.4,5.5,5.6,5.7,5.8,5.9, and We reproduce ths dagram as Fgure Note at the outset that there are two knds of arrows n the data path, those wth arrowheads flled n, and those wth arrowheads not flled n. Flled-n arrowheads desgnate nformaton that s processed. Unflledn arrowheads desgnate control sgnals. Control sgnals emanate from the block labeled "Control." The connectons from Control to most control sgnals have been left off Fgure 5.18 to reduce unnecessary clutter n the dagram Basc Components of the Data Path The Global Bus You undoubtedly frst notce the heavy black structure wth arrowheads at both ends. Ths represents the data path's global bus. The LC-3 global bus conssts of 16 wres and assocated electroncs. t allows one structure to transfer up to 16 bts of nformaton to another structure by makng the necessary electronc connectons on the bus. Exactly one value can be transferred on the bus at one tme. Note that each structure that supples values to the bus has a trangle just