Design of a High-Level Data Link Controller

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1 ECE 551 Course Project Design of a High-Level Data Link Controller Interim Report - Due Wednesday, November 28, 2001, 4:00 PM Final Report - Due Wednesday, December 12, 2001, 4:00 PM Project Teams and Collaboration Project teams are to consist of four students or, alternatively, due to remaining students from division by four, five students with added technical requirements. All project work submitted by a team is to be performed by that team. Design reuse from other teams currently in this course or in the course in the past and from other sources is strictly prohibited. The only inter-team collaboration permitted is clarification of specifications and assistance in tool use. Project Specification The functional specification for the High-Level Data Link Controller (HDLC) is given in the datasheet from the Xilinx, Inc. URL, xf-hdlc.pdf. Frame Structure 7 E 7 E Flag Data Bits 2 or 4 CRC Bytes Flag The HDLC frame structure is shown above. The packet begins with the Flag byte 7E. This Flag byte is followed by a Data Bit stream consisting of the desired transmitted data. Following the Data Bits are the CRC check bytes from the Frame Checking Sequence Generator. There can be either two or four bytes depending on the value on input FCS16_32. The frame ends with the Flag byte 7E. Zero Insertion The pattern used as a flag must be unique and must not appear anywhere else in the entire frame. In terms of the data transmitted however, any pattern is assumed to be able to occur. One way to avoid the appearance of 7E, which consists of a 0 followed by six 1 s followed by a 0, is to insure that the rest of the frame does not contain six 1 s. If five 1 s occur in sequence, a 0 is inserted as the next bit to avoid six 1 s. Whenever five 1 s are encounter at the receiver, the following 0 must be an inserted one, so it removed. Due to this zero insertion, the number of Data Bits will not necessarily be a multiple of eight. The number of extra zeros inserted in the frame is governed by the data values being transmitted. These zeros are removed at the receiver so that after Zero Detection and Removal the number of message bits is a multiple of eight. Note that for proper operation, the Octet Error status must be evaluated on the result of the Zero Detection and Removal, not the original received message.

2 Comment. It is very common to use zero stuffing in communication protocols. Many protocols provide receiver clock synchronization without transmitting the clock. If there are long strings of a given value (0 or 1), it is possible that synchronization will be lost. For example, in the USB protocol the transmitted data is encoded using NRZI (Non-return to Zero Inverted) method. Whenever a 0 occurs, it is replaced in the encoded data by a change from 0-to-1 or 1-to-0. Whenever a 1 occurs the encoded data is unchanged. The edges produced by the encoding of the 0 s are used to synchronize the receiver clock. If a long string of 1 s occurs, synchronization can be lost. To avoid this, a zero is stuffed in every seventh position of a stream of 1 s. 16/32 FCS Generator and Checker Specification The project specification requires a Frame Checking Sequence (FCS) Generator and a Frame Checking Sequence Checker (FCS) that are based on the following polynomials: and x + 1 Equation 1: x 16 + x 12 + x Equation 2: x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 + The basic linear feedback shift register division structure for division by polynomial 1) follows. The stream for which the Frame Checking Sequence is to be supplied is applied to the Input MSB first. After the stream has been entered, then the Frame Checking Sequence can be read out of the Output. and is complemented before use. This structure can be used in both the receiver or transmitter. The mod 2 sum logic is an XOR tree. The shift register is initially reset to 0 synchronously before being used for a frame. Note that in the actual commercial product, the form of the Frame Sequence Check does not necessarily match that given here since there are alternative ways to implement this function. Notamod 2 sum Input x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 = 1 x 16 x 15 x 14 x 13 x 12 x11 x 10 x 9 Output

3 bly, if the received sequence including the CRC is passed through the above, the result will NOT be zero as with alternative designs. Design Specifications Parameter Value Comment Setup File.synopsys_dc.setup Technology files lcbg11p_nom.db & lcbg11io.db; see Tutorial - LSI Logic Setup File for DC - Nominal Delay on website for initial file to use. Operating Conditions Nominal V DD = 2.5 V, Temp = 25 o C, Process = Nominal Clock Frequency Target 400 MHz Minimum If not achievable, then as close as possible Area Minimum For Clock Frequency Target Figure of Merit Input Drive: All Inputs except for RXC and TXC Input Drive: RXC and TXC Input Delay from Clock Rising Edge Output Load: All outputs Output Delay to Clock Rising Edge for All Outputs Wireload Model Achieved Frequency/ Achieved Area in MHz/µ 2 Drive of input receiver IBUFDR output Z Drive of clock receiver CLKC2I Minimum = 1.0 ns Maximum = 1.0 ns Load of High Speed Buffer B28NTLDR input A Minimum = 1.0 ns Maximum = 1.0 ns Default/auto-selected Will be used as measure of design effectiveness drive_of (lcbg11io/ibufdr/z) drive_of (lcbg11io/clkc2i/z) For receiver inputs measured from RXC; for transmitter inputs measured from TXC load_of (lcbg11io/b28ntldr/a) Combinational delay + setup time for external logic driven by the outputs. Synthesis 1. Your synthesis during basic design is to be done with the Operating Conditions given above and with the.synopsys_dc.setup file from the Tutorial - LSI Logic Setup File for DC - Nominal Delay folder. See Final Report for information on submissions. 2. An additional synthesis is to be done with the Operating Conditions set to Worst Case and with the.synopsys_dc.setup file from the Tutorial - LSI Logic Setup File for DC - Worst Case Delay folder. See Final Report for information on submissions. Interim Report The interim report is to represent your functionally correct, simulated design. It is not to contain any synthesis results. However, it is strongly recommended that you perform the analysis and elaboration steps of synthesis in order to insure that your Verilog is compatible with Design Compiler s capabilities.

4 This is a complete summary of the Interim Report requirements. Submit the following: 1) A cover sheet giving the names of all team members and designating the team leader, 2) A diagram showing the logical hierarchy of your modules including descriptive names, modules names and consecutive numbering, 3) Your Verilog code for each module organized in relation to the diagram in 2 (Place the corresponding number from 2 at the top of the pages for each module, 4) Simulation results for your overall design in response to testbenches we will provide by Friday, November 16 at the latest and additional testbenches that you will generate. Include comments and waveform annotation for ease of interpretation of results, and indication of whether or not results are correct. This report will be graded and will be worth 35 project points. Final Report The final report is to present the Verilog code from which the final synthesis was performed and your synthesized results. This is a complete summary of the Final Report requirements. Submit the following: 1) A cover sheet giving the names of all team members and designating the team leader, 2) A diagram showing the logical hierarchy of your modules including descriptive names, modules names and consecutive numbering, 3) Your Verilog code for each module organized in relation to the diagram in 2 (Place the corresponding number from 2 at the top of the pages for each module, 4) Simulation results for your overall design in response to testbenches we will provide by Friday, November 30 at the latest and additional testbenches that you will generate. Include comments and waveform annotation for ease of interpretation of results, and indication of whether or not results are correct. 4) A discussion of problems encountered and solutions, 5) A Synopsys report containing the following for your total final design: attributes, clock, timing constraints, cells, and area, 6) A discussion of what, if any, measures you took to achieve the Clock Frequency Target and Minimum Area, 7) 5 and 6 above using the Worst Case Operating Conditions and Worst Case Delay libraries, 8) The tabulation of the Achieved Frequency, Achieved Area, and Figure of Merit for the Nominal and Worst Case library data, 9) The quantitative comparison of the table values and discussion of the results in terms of what you obtained and what you would expect for these cases, 10) A breakdown of tasks accomplished by each team member including percentage contribution of team members to each individual or shared tasks signed by ALL team members, and 10) Optionally, for a small amount of extra credit, an attempt to meet the Clock Frequency Target for the Worst Case situation by modifying the Verilog and the compile and optimization options. This report will be graded and is worth 100 project points.

5 Tentative Project Grading Description Points Score 1 A diagram showing your logical hierarchy 05 2 Your Verilog code 25 3 Simulation results for your overall design in response to testbenches we will provide and additional testbenches that you will generate. Include comments and waveform annotation for ease of interpretation of results, and indication of whether or not results are correct A discussion of problems encountered and solutions 05 5 A Synopsys report containing the following for your final design: attributes, clock, timing constraints, cells, and total area 6 A discussion of what, if any, measures you took to achieve the Clock Frequency Target and Minimum Area 7 The tabulation of the Achieved Frequency, Achieved Area, and Figure of Merit for the Nominal and Worst Cases 8 The quantitative comparison of the table values and discussion of the results in terms of what you obtained and what you would expect for these cases 9 A breakdown of tasks accomplished by each team member including percentage contribution of team members to shared tasks 10 Extra Credit: Optionally for a small amount of extra credit, attempt to meet the Clock Frequency Target for the Worst Case situation by modifying the Verilog and compile and optimization options EC TOTAL 100 TOTAL EC

Single Channel HDLC Core V1.3. LogiCORE Facts. Features. General Description. Applications

Single Channel HDLC Core V1.3. LogiCORE Facts. Features. General Description. Applications Sept 8, 2000 Product Specification R Powered by Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: logicore@xilinx.com URL: www.xilinx.com/ipcenter Support: