Assignment 1. ECSE-487 Computer archecture Lab. Due date: September 21, 2007, Trottier Assignment Box by 14:30

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1 Assignment 1 ECSE-487 Computer archecture Lab Due date: September 21, 2007, Trottier Assignment Box by 14:30 1 Introduction The purpose of this assignment is to re-familiarize the student with VHDL and to learn how to use industrial electronic design automation (EDA) software such as ModelSim for simulation and Precision RTL for synthesis. The arithmetic logic unit (ALU) is a core component of any CPU. The ALU performs arithmetic operations such as addition, subtraction and multiplication and many more. You can read more about the ALU by following this Wikipedia link ( logic unit) or by referencing a textbook on computer architecture 2 Functional Requirements You are required to implement a complex 8-bit ALU that has a similar architecture as that shown in Figure 1. A description of each port and their type (in/out) is shown in Table 1. Each complex numbers is represented by a 16-bit vector. The most significant byte (8 bits) represents the real part. The least significant byte (8 bits) represents the imaginary part. The real and imaginary parts of the complex number are signed integers. The ALU will also perform basic operations on a finite field (also named Galois Field (GF)). Galois fields are used in many applications such as cryptography and coding theory. For example, they are used in Reed-Solomon codes which are in turn used about everywhere. CD-ROMs, hard disks, deep space probes and many more use Reed-Solomon codes to prevent corruption of the information. You can get more information on finite fields on the Wikipedia links ( field and 1

2 field arithmetic). The specific Galois field that you will operate on will be GF(2 8 ) or GF(256). It contains 256 elements and therefore only needs 8 bits to represent all possible members. The primitive polynomial is the standard x 8 + x 4 + x 3 + x + 1 (do not worry too much about that, you only need to use it for the multiplication operation). In this field, the addition and the substraction are actually the same operation and they are very easy to implement: it is a simple XOR operation. The multiplication is a bit more complicated and can either be computed physically or precomputed and loaded in a lookup table (LUT), the choice is yours. If you opt for the LUT implementation, I suggest writing a small script in C or in Matlab to generate the VHDL code, 256 elements is a bit tedious to enter manually. Detailed instruction on the multiplication algorithm can be found in the links provided above. The operations that your ALU implementation should be able to perform are listed in Table 2.The ALU is synchronous. The inputs must be latched into registers before the computation takes place and the correct output must be latched into a register once it is ready. You are free to add any extra input or output signals that are deemed necessary. It is also up to you to decide how many bits to use for each input and output. You will be required to explain your design decisions in your report. 2.1 Behavioral Description A VHDL behavioral model specifies a module s function using VHDL programming constructs such as ifthen-else clauses, etc. It does not specify any internal structure. A VHDL structural model specifies a module s internal structure by identifying all internal modules or units (call these sub-modules) and defining how they are interconnected using the portmap construct. It does not specify any internal behavior. In this assignment your will learn to use both behavioral and structural models. 2.2 ALU Design Hardware systems can be optimized for various performance measures depending on the goals of the design. In this assignment 3 different goals are of interest: minimum hardware, minimum latency and maximum throughput. The minimum hardware design must reuse components as much as possible. The minimum latency design must reduce the delay required to execute a computation by exploiting parallelism. The maximum throughput design must increase the rate at which results are produced through pipelining. Start by implementing the ALU using a behavioral VHDL model aiming for maximum throughput. Next, select between one of the 2 design optimization (minimum hardware or minimum latency) and implement the ALU using a structural model. Both models should be simulated and synthesized. 2

3 Figure 1: Proposed ALU architecture 2.3 Simulations and Testing Testing is a very important part of the hardware design process that is often neglected. You are expected to thoroughly test your VHDL models to ensure correct operation. Make sure that all special cases are tested. Your benchmark should be included in your report to convince the reader that the design is functioning correctly. Provide a waveform trace showing the execution of 2 operations. The trace should be properly annotated and easy to understand without needing to consult your source code. Describe the important features of the simulation and annotate your traces to improve readability. Remove any irrelevant signals from the traces. Lengthy simulations can be included, if necessary, in an appendix. 2.4 Source Code Your VHDL code should be well documented. Each file should start with a header including the filename, the authors, the date, the last revision date and a meaningful description. A description for mux2.vhd such as this is the mux2 implementation doesn t add any information and is not considered meaningful. All the ports of an entity should be briefly described. Comments should be used to indicate interesting parts of the code or parts that could be improved. Use good names for your variables and signals to improve the readability of your code. Imagine that someone who isn t familiar with this assignment is reading your code and trying to understand it. 3

4 Name Type Description OPCODE In Operation to be performed by the ALU DATA0 In First operand DATA1 In Second operand RESET In Reset the ALU to initial state CLOCK In Input clock DATAOUT Out Result of the operation STATUS Out Status of the DATAOUT port Table 1: Description of the ALU ports Operation Type Complex Arithmetic Galois Field Operation Addition, Substraction, Multiplication Addition/Substraction, Multiplication Table 2: Supported ALU operations 3 Assignment Tasks Here is a recap of what is to be done in this first assignment. 1. Implement an ALU as described in Section 2: (a) Behavioral model aiming for maximum throughput. (b) Structural model aiming either for minimum hardware or minimum latency. 2. Simulate and test your designs. You might need 2 different testbenches for your 2 designs. Your testbenchs should be in a separate file. 3. Your source code should be properly commented so that the marker can follow your design. 4. Provide a waveform trace showing the execution of 2 operations. The trace should be properly annotated and easy to understand without needing to consult your source code. 5. Synthesize your designs without the testbench. In your report, describe the results of the synthesis, including the number of logic cells, look-up tables, and the latency of your circuit. Identify in your designs the piece that consumes the most space and the longest path. 4 Submission Guidelines A hardcopy version of your report excluding VHDL source code is to be submitted either in-class or in the assignment box in the Trottier building. 4

5 An electronic copy of your report including your VHDL source files is to be submitted through WebCT in the form of a compressed archive. The archive should have the following properties: the name of the archive should be of the form firstname lastname.zip or.rar or.tgz. the archive should extract to a directory named firstname lastname. Your report should be no longer than 4 pages (excluding the title page, diagrams and appendices) and should include the following: front page (course number, lab title, student name, ID, date) design description: diagram and brief description of your ALU. brief summary of any important design choices. simulation results: description of testing strategy. simulation traces and discussion of results. synthesis results: critical path. estimated clock speed. resource usage. 5 Marking Scheme 35 : Working ALU implementation. 20 : Automated testbench. 05 : Simulation traces showing two operations. 10 : Synthesis results. 10 : Well structured code including meaningful comments. 20 : Report (discussion of design decisions etc) 5