Digital Integrated Circuit Design II ECE 426/526, Announcements $Date: 2016/06/02 00:31:36 $
|
|
|
- Hannah Hoover
- 5 years ago
- Views:
Transcription
1 Digital Integrated Circuit Design II ECE 426/526, Announcements $Date: 2016/06/02 00:31:36 $ Professor R. Daasch Depar tment of Electrical and Computer Engineering Portland State University Portland, OR (daasch@ece.pdx.edu) Course Website [Note links are parsed by Adober Reader but may not be parsed by browser viewers] R.Daasch, Por tland State University 1 June 2016
2 1 June 2016 I was wrong, wrong wrong about final exam start time Final exam is from 7:30PM to 9:20PM 6 June 2016 Thanks goes to Tim N. for his catch New Date to submit Laborator y 2 is 5 June 2016 Link below is a step-by-step guide to create physical layout from schematic Cadence Wiki home page simulation and layout projects/cadence/wiki/virtuoso New CAD tools include: SOC Encounter and Mentor Graphics Calibre also checks DRC and LVS Include in your datasheet a comparison of clock timings for schematic and physical (layout) views Reminder : Include units in datasheet for layout view X and Ytwo options are microns µm or λ R.Daasch, Por tland State University 2 June 2016
3 1 June 2016 In your design test enable can be either TE active LOW or TE active HIGH Submit completed datasheets for adder subtractor design by Rohan Use correct subject Subject: ECE x26 Laborator y 2 Version {1,2,3} LastName # No late submissions will be accepted R.Daasch, Por tland State University 3 June 2016
4 23 May 2016 University Closed for Memorial Day, No class Monday 30 May 2016 Final Exam Announcement Final Exam, June 6, (7:30PM - 9:20PM) Ondine 218 NOTE: Final Exam start time is one hour earlier than class star t time Comprehensive: Chapters 9-15 Laborator y 2 Pre-grade distributed Some did not submit (why hur t yourself?) Points accumulated by pre-grade will be applied to final laborator y score Corrections and additions will be added to final laborator y score R.Daasch, Por tland State University 4 June 2016
5 23 May 2016 New mater ial will be added to the final laborator y score R.Daasch, Por tland State University 5 June 2016
6 16 May 2016 Reminder about Ver ilog module identifiers module identifier() Verilog module identifiers begin with either a lowercase letter [a-z], an uppercase letter [A-Z], or the underscore (_) Identifiers of more than one character can include any sequence of letters [a-za-z], digits [0-9], dollar signs ($), and underscore characters (_). Correct module identifiers: AdderSubtractor, _fourbitadder Incorrect module identifiers: 4bitadder, $4bit May 20th or before you may submit one new cell, of your choosing, for early grading. Select and submit only one completed cell datasheet either D Flip-flop Scan Register Design, Overflow and Underflow Combinational Design, or R.Daasch, Por tland State University 6 June 2016
7 16 May 2016 Scan and Parallel Register Design. submit on May 20 one completed datasheet as a PDF to TA, Rohan Jagtap, rjagtap@pdx.edu Subject line Subject: ECE x26 PreLaborator y 2 Cell_NAME LastName # The submitted cell datasheet will be graded and wor th up to 15% of the total Laborator y 2 score You may either accept the grade for the cell or submit a revised datasheet on 29 May 2016 All ear ly grading (errors) have to be fixed to ear n additional score R.Daasch, Por tland State University 7 June 2016
8 9 May 2016 Pre-submission of one cell of your choice for pre-grading 20 May 2016, submit one cell Submit for one cell a completed datasheet as a PDF by to TA, Rohan Jagtap. rjagtap@pdx.edu With subject line Subject: ECE x26 PreLaborator y 2 Cell LastName # R.Daasch, Por tland State University 8 June 2016
9 4 May 2016 Tw o options for place and route structural Ver ilog NC-Ver ilog output with input a structural schematic of standard cells Synthesized output with input a behavioral Ver ilog design Warning: Using structural Ver ilog from synthesis introduces possible inconsistency in Spectre simulation results From CIW -> File -> Import -> Ver ilog R.Daasch, Por tland State University 9 June 2016
10 2 May 2016 Midter m graded, returned today Each question wor th 20 points ECE 426: 39:67 ECE 526: 55:79 See me during Office hours or by appointment about grading Low scores should set appointment to discuss improving for final exam Combining Laborator y 2 and Laborator y 3 for single due date of final design Combined laborator y descr iption posted by 4 May 2016 Be sure to set transient option to lvl and nestlvl = 1 Completed design submitted 29 May 2016 R.Daasch, Por tland State University 10 June 2016
11 2 May 2016 Laborator y 2 design a register with both parallel and serial loading options, a one bit-slice and hierarchical design with a 11 bit word Laborator y 3 combines Laborator y 2 register with Addersubtractor R.Daasch, Por tland State University 11 June 2016
12 25 April 2016 Fortunately the fix is simple for Cadence 6.15 Calculator difference from 6.10 Calculator for the bitgen DC supply in the testbench The trouble is with a single character a / in the name of the current signal name "/Vvdd:p" Removing the / by clicking into the buffer or other editable window and delete the / NO NEED to revert to IC6.1.0 stay with IC R.Daasch, Por tland State University 12 June 2016
13 25 April 2016 Red circle arrow on left note / before the /V and / deleted on right in green R.Daasch, Por tland State University 13 June 2016
14 25 April 2016 Laborator y 1 with power evaluated due date reset to this Fr iday 29 Apr il 2016 Reminder Exam 27 April 2016 Coverage: 9, 10, 11.1,2,10 R.Daasch, Por tland State University 14 June 2016
15 20 April 2016 Exam 27 April 2016 Entire period Closed book and notes Technology parameters, Equations (e.g. logical effor t) provided on standard cover page Detailed coverage set 25 April 2016; Chapter 9, 10, 11 Spectre notes Limit transient output file sizes by replacing default Options to lvl from allpub Set nestlvl =1 Bitgen buses are noted in schematics as wide-wire bundles R.Daasch, Por tland State University 15 June 2016
16 20 April 2016 Signal Bitgen Schematic Name Single Bus Bundle Bus A1 A1 A<1:3> A1,A2,A3 A<1> A<1> A<1:3> R.Daasch, Por tland State University 16 June 2016
17 18 April 2016 Midter m will be 27 April 2016 Coverage 9, 10, 11 Practice Problems for each chapter are available in Assignments Laborator y 1, clarifying FO4 load Nor mally, Sbus is driven by ExOr (or similar gates) and C 4 is NAND The definition of FO4 uses h = C out /C in that is, like gates Use FO4 ExOr loads for Sbus and C4 No new yet for ECE x26 video from Winter 2014, it may be lost R.Daasch, Por tland State University 17 June 2016
18 13 April 2016 First Call on mid-term exam Tentatively set for 27 April 2016 Midter m no earlier than 27 April For coverage of Chapter 11 be move back to2may R.Daasch, Por tland State University 18 June 2016
19 11 April 2016 Laborator y 1 bitgen demo PDK 45 Standard cell redefinition that may ease clutter in schematics Not completed yet R.Daasch, Por tland State University 19 June 2016
20 6 Apr il 2016 Laborator y 1, Standard Cell Place and Route is misnamed and is causing confusion Laborator y 1 prepares the design of the 4-bit adder-subtractor for place and route Place and route (and a new tool Cadence SOC Encounter) is Laborator y 2 To check ifyou have latest revision of the notes the date is added to header page R.Daasch, Por tland State University 20 June 2016
21 4 Apr il 2016 PDF of syllabus posted Syllabus ecex26.cgi?2#2 Laborator y 1 is posted and due 25 April 2016 A standard for mat Word file is used to submit reports. Standard Cell Report %7Eecex26/doc/Standard_Cell_Report.docx Repor ts do not have to be long. Modeled after the essential elements of standard cell based design documentation. Laborator y 1 laboratory1.pdf Meet Rohan Jagtap, TA R.Daasch, Por tland State University 21 June 2016
22 4 Apr il 2016 Reminder subject line use the string ECE x26, Adding course number string to subject reduces the delay for aresponse R.Daasch, Por tland State University 22 June 2016
23 30 March 2016 TA is Rohan Jagtap, Office hours in VLSI Lab: Tu Th 2:00-3:00PM or by appointment See Assignments ecex26.cgi?3#3/ for chapter reading order Course Coverage of Digital Integrated Circuits II Complete Weste and Harris, CMOS VLSI Design Review ECE x25 Key Chapters: Chapter 4, Chapter 7, Chapter 9 Chapter 10, Sequential Chapter 11, Datapath Chapter 12, Arrays Chapter 13, Special-Purpose R.Daasch, Por tland State University 23 June 2016
24 30 March 2016 Chapter 15, Test R.Daasch, Por tland State University 24 June 2016
25 28 March 2016 On subject line use the string ECE x26, adding this str ing to subject reduces the delay for a response Laborator y 1 is a character ization of standard cells and logic design of a simple adder and subtractor Simplified data sheet for mat PDK cell ece.pdx.edu/%7eecex26/lab/ PDK45_Cell_Datasheet.doc PDK circuit design PDK45_Design_Datasheet.doc Points to consider in the shift from logic cells to logic design Input is different for testing a logic design than input for testing a single logic gate Eventually, number of rows in truth table is too large 2 n, n number of inputs Bitgen is a simple Spectre compatible generator for input R.Daasch, Por tland State University 25 June 2016
26 28 March 2016 Place and route will commence starting with Laborator y 2 R.Daasch, Por tland State University 26 June 2016
CMOS VLSI Design Lab 2: Datapath Design and Verification
CMOS VLSI Design Lab 2: Datapath Design and Verification In this lab, you will begin designing an 8-bit MIPS processor. You will first review and simulate a Verilog model of the overall processor. You
EEC 116 Fall 2011 Lab #3: Digital Simulation Tutorial
EEC 116 Fall 2011 Lab #3: Digital Simulation Tutorial Dept. of Electrical and Computer Engineering University of California, Davis Issued: October 10, 2011 Due: October 19, 2011, 4PM Reading: Rabaey Insert
An overview of standard cell based digital VLSI design
An overview of standard cell based digital VLSI design Implementation of the first generation AsAP processor Zhiyi Yu and Tinoosh Mohsenin VCL Laboratory UC Davis Outline Overview of standard cellbased
CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN FALL 2005
CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN FALL 2005 AN INTRODUCTION TO DIGITAL SYSTEMS AND THE PPM PROJECT 1. Introduction A digital system consists of digital circuits. It performs sequences of simple
ARM 64-bit Register File
ARM 64-bit Register File Introduction: In this class we will develop and simulate a simple, pipelined ARM microprocessor. Labs #1 & #2 build some basic components of the processor, then labs #3 and #4
Hardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University
Hardware Design Environments Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Outline Welcome to COE 405 Digital System Design Design Domains and Levels of Abstractions Synthesis
ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS)
ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS) Objective Part A: To become acquainted with Spectre (or HSpice) by simulating an inverter,
ECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog
ECE 2300 Digital Logic & Computer Organization Spring 2018 More Sequential Logic Verilog Lecture 7: 1 Announcements HW3 will be posted tonight Prelim 1 Thursday March 1, in class Coverage: Lectures 1~7
Columbia Univerity Department of Electrical Engineering Fall, 2004
Columbia Univerity Department of Electrical Engineering Fall, 2004 Course: EE E4321. VLSI Circuits. Instructor: Ken Shepard E-mail: shepard@ee.columbia.edu Office: 1019 CEPSR Office hours: MW 4:00-5:00
The Microprocessor as a Microcosm:
The Microprocessor as a Microcosm: A Hands-On Approach to VLSI Design Education David Harris David_Harris@hmc.edu November 2002 Harvey Mudd College Claremont, CA Outline Introduction Course Organization
CMOS VLSI Design Lab 3: Controller Design and Verification
CMOS VLSI Design Lab 3: Controller Design and Verification The controller for your MIPS processor is responsible for generating the signals to the datapath to fetch and execute each instruction. It lacks
CMOS VLSI Design Lab 3: Controller Design and Verification
CMOS VLSI Design Lab 3: Controller Design and Verification The controller for your MIPS processor is responsible for generating the signals to the datapath to fetch and execute each instruction. It lacks
CMOS VLSI Design Lab 3: Controller Design and Verification
CMOS VLSI Design Lab 3: Controller Design and Verification The controller for your MIPS processor is responsible for generating the signals to the datapath to fetch and execute each instruction. It lacks
CPE/EE 427, CPE 527, VLSI Design I: Tutorial #2, Schematic Capture, DC Analysis, Transient Analysis (Inverter, NAND2)
CPE/EE 427, CPE 527, VLSI Design I: Tutorial #2, Schematic Capture, DC Analysis, Transient Analysis (Inverter, NAND2) Joel Wilder, Aleksandar Milenkovic, ECE Dept., The University of Alabama in Huntsville
CMOS VLSI Design. Final Project
Harris CMOS VLSI Design Final Project 1. Overview The final project is a chance for you to apply your new skills in VLSI design to a moderate sized problem of your choosing as part of a two-person team.
CSE 141L Computer Architecture Lab Fall Lecture 3
CSE 141L Computer Architecture Lab Fall 2005 Lecture 3 Pramod V. Argade November 1, 2005 Fall 2005 CSE 141L Course Schedule Lecture # Date Day Lecture Topic Lab Due 1 9/27 Tuesday No Class 2 10/4 Tuesday
Design of a High-Level Data Link Controller
ECE 551 Course Project Design of a High-Level Data Link Controller Interim Report - Due Wednesday, November 28, 2001, 4:00 PM Final Report - Due Wednesday, December 12, 2001, 4:00 PM Project Teams and
Digital Integrated Circuit Design I ECE 425/525 Chapter 1
Digital Integrated Circuit Design I ECE 425/525 Chapter 1 Professor R. Daasch Depar tment of Electrical and Computer Engineering Portland State University Portland, OR 97207-0751 (daasch@ece.pdx.edu) http://ece.pdx.edu/~ecex25
ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL. Fall 2017 Final Exam (6.00 to 8.30pm) Verilog SOLUTIONS
ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL Fall 2017 Final Exam (6.00 to 8.30pm) Verilog SOLUTIONS Note: Closed book no notes or other material allowed apart from the one
Recommended Design Techniques for ECE241 Project Franjo Plavec Department of Electrical and Computer Engineering University of Toronto
Recommed Design Techniques for ECE241 Project Franjo Plavec Department of Electrical and Computer Engineering University of Toronto DISCLAIMER: The information contained in this document does NOT contain
PINE TRAINING ACADEMY
PINE TRAINING ACADEMY Course Module A d d r e s s D - 5 5 7, G o v i n d p u r a m, G h a z i a b a d, U. P., 2 0 1 0 1 3, I n d i a Digital Logic System Design using Gates/Verilog or VHDL and Implementation
Lab 2. Standard Cell layout.
Lab 2. Standard Cell layout. The purpose of this lab is to demonstrate CMOS-standard cell design. Use the lab instructions and the cadence manual (http://www.es.lth.se/ugradcourses/cadsys/cadence.html)
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science EECS 150 Spring 2002 Original Lab By: J.Wawrzynek and N. Weaver Later revisions by
Lecture #1: Introduction
Lecture #1: Introduction Kunle Olukotun Stanford EE183 January 8, 20023 What is EE183? EE183 is continuation of EE121 Digital Logic Design is a a minute to learn, a lifetime to master Programmable logic
CS 250 VLSI Design Lecture 11 Design Verification
CS 250 VLSI Design Lecture 11 Design Verification 2012-9-27 John Wawrzynek Jonathan Bachrach Krste Asanović John Lazzaro TA: Rimas Avizienis www-inst.eecs.berkeley.edu/~cs250/ IBM Power 4 174 Million Transistors
CPE/EE 427, CPE 527, VLSI Design I: Tutorial #3, Standard cell design flow (from schematic to layout, 8-bit accumulator)
CPE/EE 427, CPE 527, VLSI Design I: Tutorial #3, Standard cell design flow (from schematic to layout, 8-bit accumulator) Joel Wilder, Aleksandar Milenkovic, ECE Dept., The University of Alabama in Huntsville
DEPT OF ECE EC6612 -VLSI DESIGN LABORATORY MANUAL (REGULATION-2013) LAB MANUAL DEPARTMENT OF ECE NAME: REGISTER NUMBER: YEAR/SEM.: ACADEMIC YEAR: 2015-2016 DEPT OF ECE EC6612 -VLSI DESIGN LABORATORY MANUAL
Lecture 1: Introduction Course arrangements Recap of basic digital design concepts EDA tool demonstration
TKT-1426 Digital design for FPGA, 6cp Fall 2011 http://www.tkt.cs.tut.fi/kurssit/1426/ Tampere University of Technology Department of Computer Systems Waqar Hussain Lecture Contents Lecture 1: Introduction
DESIGN PROJECT TOY RPN CALCULATOR
April 8, 1998 DESIGN PROJECT TOY RPN CALCULATOR ECE/Comp Sci 352 Digital System Fundamentals Semester II 1997-98 Due Tuesday, April 28, 1998; 10% of course grade. This project is to be submitted and will
An Overview of Standard Cell Based Digital VLSI Design
An Overview of Standard Cell Based Digital VLSI Design With examples taken from the implementation of the 36-core AsAP1 chip and the 1000-core KiloCore chip Zhiyi Yu, Tinoosh Mohsenin, Aaron Stillmaker,
ENGR 3410: MP #1 MIPS 32-bit Register File
ENGR 3410: MP #1 MIPS 32-bit Register File Due: October 12, 2007, 5pm 1 Introduction The purpose of this machine problem is to create the first large component of our MIPS-style microprocessor the register
System Verification of Hardware Optimization Based on Edge Detection
Circuits and Systems, 2013, 4, 293-298 http://dx.doi.org/10.4236/cs.2013.43040 Published Online July 2013 (http://www.scirp.org/journal/cs) System Verification of Hardware Optimization Based on Edge Detection
Revision Notes: July2004 Generate tutorial for single transistor analysis. Based on existing schematic entry tutorial developed for ECE410
Cadence Analog Tutorial 1: Schematic Entry and Transistor Characterization Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group. Revision Notes: July2004 Generate tutorial for
Submitting Assignments
Submitting Assignments Blackboard s assignments feature allows the instructor to assign coursework for you to submit electronically. First, you need to locate the assignment. Your instructor will place
Start Active-HDL. Create a new workspace TUTORIAL #1 CREATING AND SIMULATING SIMPLE SCHEMATICS
Introduction to Active-HDL TUTORIAL #1 CREATING AND SIMULATING SIMPLE SCHEMATICS This tutorial will introduce the tools and techniques necessary to design a basic schematic. The goal of this tutorial is
Fundamentals of Digital System Design ECE 3700, CPSC 3700
Fundamentals of Digital System Design ECE 3700, CPSC 3700 Instructor: Priyank Kalla (kalla@ece.utah.edu) 4 Credits Tue, Thu 1:25-1:45pm, WEB 1230 Office Hours: Tue, Thu: 2:30-4pm, or by appointment Office:
Digital Integrated Circuits
Digital Integrated Circuits Introduction to the course Jaeyong Chung SoC Laboratory Incheon National University Course Information Schedule (EPC6055001) Mon 6:55pm - 8:40pm (SI433), Tue 7:50pm - 9:35pm
4DM4 Lab. #1 A: Introduction to VHDL and FPGAs B: An Unbuffered Crossbar Switch (posted Thursday, Sept 19, 2013)
1 4DM4 Lab. #1 A: Introduction to VHDL and FPGAs B: An Unbuffered Crossbar Switch (posted Thursday, Sept 19, 2013) Lab #1: ITB Room 157, Thurs. and Fridays, 2:30-5:20, EOW Demos to TA: Thurs, Fri, Sept.
Sense Amplifiers 6 T Cell. M PC is the precharge transistor whose purpose is to force the latch to operate at the unstable point.
Announcements (Crude) notes for switching speed example from lecture last week posted. Schedule Final Project demo with TAs. Written project report to include written evaluation section. Send me suggestions
CHAPTER 3 METHODOLOGY. 3.1 Analysis of the Conventional High Speed 8-bits x 8-bits Wallace Tree Multiplier
CHAPTER 3 METHODOLOGY 3.1 Analysis of the Conventional High Speed 8-bits x 8-bits Wallace Tree Multiplier The design analysis starts with the analysis of the elementary algorithm for multiplication by
EE 434 ASIC & Digital Systems
EE 434 ASIC & Digital Systems Dae Hyun Kim EECS Washington State University Spring 2018 Course Website http://eecs.wsu.edu/~ee434 Themes Study how to design, analyze, and test a complex applicationspecific
ECE 156A - Syllabus. Description
ECE 156A - Syllabus Lecture 0 ECE 156A 1 Description Introduction to HDL (Hardware Description Language) basic elements, HDL simulation concepts, HDL concurrent statements with examples and applications,
Synthesis. Other key files. Standard cell (NAND, NOR, Flip-Flop, etc.) FPGA CLB
SYNTHESIS Synthesis Involves synthesizing a gate netlist from verilog source code We use Design Compiler (DC) by Synopsys which is the most popular synthesis tool used in industry Target library examples:
KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT
KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:00-11:50AM Class
Don t expect to be able to write and debug your code during the lab session.
EECS150 Spring 2002 Lab 4 Verilog Simulation Mapping UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Lab 4 Verilog Simulation Mapping
Cell-Based Design Flow. TA : 吳廸優
Cell-Based Design Flow TA : 吳廸優 dywu@viplab.cs.nctu.edu.tw 1 Outline Overview Design Flow Stage 1 RTL Development Synthesis Gate Level Simulation Design Flow Stage 2 Placement and Routing Post Layout Simulation
Lab. Course Goals. Topics. What is VLSI design? What is an integrated circuit? VLSI Design Cycle. VLSI Design Automation
Course Goals Lab Understand key components in VLSI designs Become familiar with design tools (Cadence) Understand design flows Understand behavioral, structural, and physical specifications Be able to
101-1 Under-Graduate Project Digital IC Design Flow
101-1 Under-Graduate Project Digital IC Design Flow Speaker: Ming-Chun Hsiao Adviser: Prof. An-Yeu Wu Date: 2012/9/25 ACCESS IC LAB Outline Introduction to Integrated Circuit IC Design Flow Verilog HDL
Good Evening! Welcome!
University of Florida EEL 3701 Fall 2011 Dr Eric M Schwartz Page 1/11 Exam 2 Instructions: Turn off all cell phones, beepers and other noise making devices Show all work on the front of the test papers
IA Digital Electronics - Supervision I
IA Digital Electronics - Supervision I Nandor Licker Due noon two days before the supervision 1 Overview The goal of this exercise is to design an 8-digit calculator capable of adding
A Brief Introduction to Verilog Hardware Definition Language (HDL)
www.realdigital.org A Brief Introduction to Verilog Hardware Definition Language (HDL) Forward Verilog is a Hardware Description language (HDL) that is used to define the structure and/or behavior of digital
Exp#8: Designing a Programmable Sequence Detector
Exp#8: Designing a Programmable Sequence Detector Objectives Learning how to partition a system into data-path and control unit. Integrating Schematics and Verilog code together Overview In this lab you
ASIC Physical Design Top-Level Chip Layout
ASIC Physical Design Top-Level Chip Layout References: M. Smith, Application Specific Integrated Circuits, Chap. 16 Cadence Virtuoso User Manual Top-level IC design process Typically done before individual
Synthesis and APR Tools Tutorial
Synthesis and APR Tools Tutorial (Last updated: Oct. 26, 2008) Introduction This tutorial will get you familiarized with the design flow of synthesizing and place and routing a Verilog module. All the
Introduction to CMOS VLSI Design (E158) Lab 4: Controller Design
Harris Introduction to CMOS VLSI Design (E158) Lab 4: Controller Design The controller for your MIPS processor is responsible for generating the signals to the datapath to fetch and execute each instruction.
CSE140: Components and Design Techniques for Digital Systems
CSE4: Components and Design Techniques for Digital Systems Tajana Simunic Rosing Announcements and Outline Check webct grades, make sure everything is there and is correct Pick up graded d homework at
EE 330 Laboratory Experiment Number 11 Design, Simulation and Layout of Digital Circuits using Hardware Description Languages
EE 330 Laboratory Experiment Number 11 Design, Simulation and Layout of Digital Circuits using Hardware Description Languages Purpose: The purpose of this experiment is to develop methods for using Hardware
ECE 241F Digital Systems
ECE 241F Digital Systems Fall 2016 J. Anderson, P. Chow Basic Information Instructors and Lecture Information Section L101 L102 L103 Instructor Jason Anderson Paul Chow Jason Anderson Office EA 314 EA
ECE 152A LABORATORY 2
ECE 152A LABORATORY 2 Objectives : 1. Understand the trade-off between time- and space-efficiency in the design of adders. In this lab, adders operate on unsigned numbers. 2. Learn how to write Verilog
CSE 591: Advanced Hardware Design and Verification (2012 Spring) LAB #0
Lab 0: Tutorial on Xilinx Project Navigator & ALDEC s Active-HDL Simulator CSE 591: Advanced Hardware Design and Verification Assigned: 01/05/2011 Due: 01/19/2011 Table of Contents 1 Overview... 2 1.1
Part II: Laboratory Exercise
SYDIC-Training Course on Digital Systems Testing and Design for Testability Part II: Laboratory Exercise Gert Jervan (gerje@ida.liu.se) Embedded Systems Laboratory (ESLAB) Linköping University March, 2003
FABRICATION TECHNOLOGIES
FABRICATION TECHNOLOGIES DSP Processor Design Approaches Full custom Standard cell** higher performance lower energy (power) lower per-part cost Gate array* FPGA* Programmable DSP Programmable general
EE 101 Lab 5 Fast Adders
EE 0 Lab 5 Fast Adders Introduction In this lab you will compare the performance of a 6-bit ripple-carry adder (RCA) with a 6-bit carry-lookahead adder (CLA). The 6-bit CLA will be implemented hierarchically
ENGR 3410: Lab #1 MIPS 32-bit Register File
ENGR 3410: Lab #1 MIPS 32-bit Register File Due: October 12, 2005, beginning of class 1 Introduction The purpose of this lab is to create the first large component of our MIPS-style microprocessor the
BUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book
BUILDING BLOCKS OF A BASIC MICROPROCESSOR Part PowerPoint Format of Lecture 3 of Book Decoder Tri-state device Full adder, full subtractor Arithmetic Logic Unit (ALU) Memories Example showing how to write
Midterm Exam ECE 448 Spring 2019 Wednesday, March 6 15 points
Midterm Exam ECE 448 Spring 2019 Wednesday, March 6 15 points Instructions: Zip all your deliverables into an archive .zip and submit it through Blackboard no later than Wednesday, March 6,
Design of a Low Density Parity Check Iterative Decoder
1 Design of a Low Density Parity Check Iterative Decoder Jean Nguyen, Computer Engineer, University of Wisconsin Madison Dr. Borivoje Nikolic, Faculty Advisor, Electrical Engineer, University of California,
Written exam for IE1204/5 Digital Design Thursday 29/
Written exam for IE1204/5 Digital Design Thursday 29/10 2015 9.00-13.00 General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned when
EECS150, Fall 2004, Midterm 1, Prof. Culler. Problem 1 (15 points) 1.a. Circle the gate-level circuits that DO NOT implement a Boolean AND function.
Problem 1 (15 points) 1.a. Circle the gate-level circuits that DO NOT implement a Boolean AND function. 1.b. Show that a 2-to-1 MUX is universal (i.e. that any Boolean expression can be implemented with
Design Methodologies. Full-Custom Design
Design Methodologies Design styles Full-custom design Standard-cell design Programmable logic Gate arrays and field-programmable gate arrays (FPGAs) Sea of gates System-on-a-chip (embedded cores) Design
Final Exam Solution Sunday, December 15, 10:05-12:05 PM
Last (family) name: First (given) name: Student I.D. #: Circle section: Kim Hu Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/CS 352 Digital System Fundamentals
FPGA for Complex System Implementation. National Chiao Tung University Chun-Jen Tsai 04/14/2011
FPGA for Complex System Implementation National Chiao Tung University Chun-Jen Tsai 04/14/2011 About FPGA FPGA was invented by Ross Freeman in 1989 SRAM-based FPGA properties Standard parts Allowing multi-level
EECE 285 VLSI Design. Cadence Tutorial EECE 285 VLSI. By: Kevin Dick Co-author: Jeff Kauppila Co-author: Dr. Arthur Witulski
Cadence Tutorial EECE 285 VLSI By: Kevin Dick Co-author: Jeff Kauppila Co-author: Dr. Arthur Witulski 1 Table of Contents Purpose of Cadence 1) The Purpose of Cadence pg. 4 Linux 1) The Purpose of Linux
Graphics: Alexandra Nolte, Gesine Marwedel, Universität Dortmund. RTL Synthesis
Graphics: Alexandra Nolte, Gesine Marwedel, 2003 Universität Dortmund RTL Synthesis Purpose of HDLs Purpose of Hardware Description Languages: Capture design in Register Transfer Language form i.e. All
CPE/EE 427, CPE 527, VLSI Design I: Tutorial #4, Standard cell design flow (from verilog to layout, 8-bit accumulator)
CPE/EE 427, CPE 527, VLSI Design I: Tutorial #4, Standard cell design flow (from verilog to layout, 8-bit accumulator) Joel Wilder, Aleksandar Milenkovic, ECE Dept., The University of Alabama in Huntsville
structure syntax different levels of abstraction
This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital
Here is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this
This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital
ENGIN 241 Digital Systems with Lab
ENGIN 241 Digital Systems with Lab (4) Dr. Honggang Zhang Engineering Department University of Massachusetts Boston 1 Introduction Hardware description language (HDL): Specifies logic function only Computer-aided
Evolution of CAD Tools & Verilog HDL Definition
Evolution of CAD Tools & Verilog HDL Definition K.Sivasankaran Assistant Professor (Senior) VLSI Division School of Electronics Engineering VIT University Outline Evolution of CAD Different CAD Tools for
ECE410 Design Project Spring 2013 Design and Characterization of a CMOS 8-bit pipelined Microprocessor Data Path
ECE410 Design Project Spring 2013 Design and Characterization of a CMOS 8-bit pipelined Microprocessor Data Path Project Summary This project involves the schematic and layout design of an 8-bit microprocessor
Topics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science. EECS 150 Spring 2000
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science EECS 150 Spring 2000 Lab 1 Introduction to Xilinx Design Software 1 Objectives In this
The Alarm System: The alarm system to be designed has the following inputs.
1 Introduction In this lab you will use the Xilinx CAD tools to complete the design of a simple home alarm system containing sensors for that indicate whether the Windows, Door, and Garage are secure.
UNIT 6 CIRCUIT DESIGN
UNIT 6 CIRCUIT DESIGN 1 2 HIERARCHY DESIGN CMOS LOGIC CIRCUIT DESIGN Learning outcomes FOR HIERARCHY DESIGN Student should be able to: Define hierarchy design. Explain the levels of hierarchical design.
FPGAs: Instant Access
FPGAs: Instant Access Clive"Max"Maxfield AMSTERDAM BOSTON HEIDELBERG LONDON NEW YORK OXFORD PARIS SAN DIEGO SAN FRANCISCO SINGAPORE SYDNEY TOKYO % ELSEVIER Newnes is an imprint of Elsevier Newnes Contents
ECE 331: N0. Professor Andrew Mason Michigan State University. Opening Remarks
ECE 331: N0 ECE230 Review Professor Andrew Mason Michigan State University Spring 2013 1.1 Announcements Opening Remarks HW1 due next Mon Labs begin in week 4 No class next-next Mon MLK Day ECE230 Review
Testing & Verification of Digital Circuits ECE/CS 5745/6745. Hardware Verification using Symbolic Computation
Testing & Verification of Digital Circuits ECE/CS 5745/6745 Hardware Verification using Symbolic Computation Instructor: Priyank Kalla (kalla@ece.utah.edu) 3 Credits Mon, Wed 1:25-2:45pm, WEB 2250 Office
VLSI Lab Tutorial 1. Cadence Virtuoso Schematic Composer Introduction
VLSI Lab Tutorial 1 Cadence Virtuoso Schematic Composer Introduction 1.0 Introduction The purpose of the first lab tutorial is to help you become familiar with the schematic editor, Virtuoso Schematic
CAD4 The ALU Fall 2009 Assignment. Description
CAD4 The ALU Fall 2009 Assignment To design a 16-bit ALU which will be used in the datapath of the microprocessor. This ALU must support two s complement arithmetic and the instructions in the baseline
ESE 150 Lab 07: Digital Logic
LAB 07 In this lab we will do the following: 1. Investigate basic logic operations (AND, OR, INV, XOR) 2. Implement an ADDER on an FPGA 3. Implement a simple Finite- State Machine on an FPGA Background:
ECE 551 Digital System Design and Synthesis. Instructor: Kewal K. Saluja. Midterm Exam
Last (family) name: First (given) name: Student I.D. #: Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE 551 Digital System Design and Synthesis Instructor: Kewal
FPGA Matrix Multiplier
FPGA Matrix Multiplier In Hwan Baek Henri Samueli School of Engineering and Applied Science University of California Los Angeles Los Angeles, California Email: chris.inhwan.baek@gmail.com David Boeck Henri
EXPERIMENT NUMBER 7 HIERARCHICAL DESIGN OF A FOUR BIT ADDER (EDA-2)
7-1 EXPERIMENT NUMBER 7 HIERARCHICAL DESIGN OF A FOUR BIT ADDER (EDA-2) Purpose The purpose of this exercise is to explore more advanced features of schematic based design. In particular you will go through
! Design Methodologies. " Hierarchy, Modularity, Regularity, Locality. ! Implementation Methodologies. " Custom, Semi-Custom (cell-based, array-based)
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 12, 2016 VLSI Design and Variation Lecture Outline Design Methodologies Hierarchy, Modularity, Regularity, Locality Implementation
Midterm Exam ECE 448 Spring 2014 Monday, March 3 (15 points)
ECE8 Midterm Midterm Exam ECE 8 Spring 2 Monday, March 3 (5 points) Instructions: Zip all your delierables into an archie .zip and submit it through lackboard no later than Monday, March 3,
Overview. Design flow. Principles of logic synthesis. Logic Synthesis with the common tools. Conclusions
Logic Synthesis Overview Design flow Principles of logic synthesis Logic Synthesis with the common tools Conclusions 2 System Design Flow Electronic System Level (ESL) flow System C TLM, Verification,
University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering
University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Examination ECE 241F - Digital Systems Examiners: S. Brown,
Verilog Module 1 Introduction and Combinational Logic
Verilog Module 1 Introduction and Combinational Logic Jim Duckworth ECE Department, WPI 1 Module 1 Verilog background 1983: Gateway Design Automation released Verilog HDL Verilog and simulator 1985: Verilog
EE 330 Laboratory Experiment Number 11
EE 330 Laboratory Experiment Number 11 Design and Simulation of Digital Circuits using Hardware Description Languages Fall 2017 Contents Purpose:... 3 Background... 3 Part 1: Inverter... 4 1.1 Simulating
Lab Manual for COE 203: Digital Design Lab
Lab Manual for COE 203: Digital Design Lab 1 Table of Contents 1. Prototyping of Logic Circuits using Discrete Components...3 2. Prototyping of Logic Circuits using EEPROMs...9 3. Introduction to FPGA