model System under Development NIU HW description in Verilog Port NIU Monitor Program in C++ NIU Firmware in C++ SPARC model other device model

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5 System under Development Co-simulation Environment NIU Firmware in C++ Interface functions Co-simulation support library NIU HW description in Verilog Port model SPARC model IPC tasks Verilog-XL other device model Builtin tasks NIU Monitor Program in C++ Interface functions Co-simulation support library Unix Unix Unix Network

6 Verilog simulator software process2 software process1 Unix sockets Application-specific hardware module hardware process1 hardware process2 Bus interface module Verilog PLI

7 System Graph Model Ariadne DLX Assembly Code Gate-Level Description DLX Simulator POSEIDON Mercury

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9 UNIX sockport Wrapper Simulation Workstation Ethernet VxWorks Interface Library msgsend() msgreceive() Server Process Remote Process Single-Board Computer Custom Board Remote Process Interface Library msgsend() msgreceive()

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11 data bus GPD application program FESPA addr read write RAM sen_act LATCH FL2BITV sen_val LATCH BITV2FL act_val or VHDL processor model I/O time INTER_CTR strb time INTER error PROUESSE electromechanical systems simulator

12 scheduler Virtual System (simulation) Prototype System (emulation) interface FPGA pod

13 Simulator Simulator Simulator network Scheduler software interface SCSI bus Pod (xilinx) hardware interface Aptix FPCB prototyping board Pod (xilinx) hardware interface

14 Application code Debugger interface Instruction set simulator Data-space state Interrupts Data accesses Instruction timing Configuration manager Co-simulation kernel BIM state Bus cycle requests Bus interface models Hardware simulation interface Hardware simulation kernel Hardware design Memory models

15 system model design flow C-program VHDL model HW model (FPGA) communication channel

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17 C program... write_socket() top-level entity of VHDL description HW core decoder/ signal register channel unit IPC handler... read_socket()... HW prototype standard device or HW prototype write_socket() {... } IPC routines Socket IPC read_socket() {... } from generator from library user-given

18 Sparc CPU SW CAD tools HW (Inspire) custom board HW (FPGA) device driver SBUS interface SBUS

19 migration from VHDL sim. to HW prototype VHDL-simulated (incremental part) HW-prototyped function of HW component HW function is completely defined and prototyped time

20 co-simulation co-synthesis C-program VHDL model (running on Inspire) C-program Refined VHDL model with Decoder IPC routines Socket IPC foreign IPC procedures DD calls I/O calls Comm. Ch. IF HW model IF simulation model library/ generator comm. protocol of target architecture IF synthesis model library/ generator

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23 target binary simulation compiler host binary target binary simulation compiler C program C compiler host binary Modify the intermediate C program for profiling

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25 HW events & elements SW instruction SW clock period (*n) bcnd _loopstart, LT lacl var

26 HW Model (VHDL) procedure sw_code attribute foreign of sw_code is C timing : postponed process begin sw_code(address,data,t_time); wait for t_time - now; end postponed process; 1. call 3. return SW Processor Model void sw_code(int*,int*,int*) {... ISR(); asm[pc].func(); } * Good performance with a limitation of single-processor co-simulation 2. call _main ldp 6 setc NO_SXM splk tick, NO_PRD opl timer_imr, IMR splk trb, NO_TCR splk timer_ifr, IFR _iloop lacl one b _iloop

27 SW HW (est. 3~6 clk s) checkpoint job done time IPC overhead

28 time SW HW t C t e min sw (i) t e max sw (i) t O t e min hw (j) t e max hw (j)

29 SW HW or t O t a SW Initiate HW thread j+1

30 SW HW re-execution t C or or rollback or t a SW t a HW t O

31 HW Model (VHDL) procedure socket_read; attribute foreign of socket_read is C ; procedure socket_write; attribute foreign of socket_write is C ; timing : postponed process begin if now = t_time or hw2sw_intr then -- send intr or ready msg to SW socket_write(address, data, now); -- receive a next t_time from SW; socket_read(address, data, t_time); end if; wait for t GCD ; end postponed process; Unix socket SW Processor Model void main() { while(1) { if (mode == SYNC) // set mode = ASYNC // in socket_read() socket_read(); // roll back if needed... ISR(); asm[pc].func(); } } if (mode == SYNC) socket_write();

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33 synchronous optimistic IPC-based Non-IPC (sec)

34 synchronous Optimistic IPC-based Non-IPC (sec)

35 LP(A) Task A I(A,i) Task B I(B,j) LP(B) Task C (HW) I(C,i) (interrupt, timestamp) I(C,i+1) LP(C) initiation from other Task(s) I(A,i+1)

36 Time Task A Task B Stored States T c (k) I(A,i) A1 I(B,j) B1 LP(A) LP(B) A1 B1 T c (k+1) T c (k+2) T c (k+3) I(A,i+1) A2 A3 B2 B3 A2 A2 A3 B2 B3 B3

37 init read interrupt write An instance of HW task

38 HW simulator Optimistic cosim. init Synchronous cosim. based on GVT SW (C50) simulator Motor simulator straggler rollback 30 us time time time

39 SW Motor IPC HW Total Sync Opt (SW) 80(HW) Run-time (sec) Simple SS(HW) Task-based SS(HW) State Size (kbyte) Simple SS(SW) Task-based SS(SW)

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41 coded bitstreams VLD Frame Store Reconstructor Forward Predictor Merger Backward Predictor IQ VLD : Variable Length Decoder IQ : Inverse Quantizer Zigzag Buffer IDCT + video output

42 P(0) P(1) P(n) User Programs SRAM DOS FPGA (Control and StatusRegister) FPGA (IDCT) Buffer ISA BUS

43 codes send data IDCT_start IDCT IDCT_done receive result time (usec) interface overhead

44 External control Coding control Source coder Video multiplex coder Transmission buffer Transmission coder Video signal a) Video encoder Coded bit stream Source decoder Video multiplex decoder Receiving buffer Receiving decoder b) Video decoder

45 Coding control Video in - DCT Q IQ IDCT + ME/MC motion vector

46 % Time Run time(second) Program SAD_Macroblock mcount umul umul_8bit FindHalfPel MotionEstimation Dct idctref Quant umul_4bit Subprograms for Motion Estimation 49.4% of total run time!!!

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48 C-program VHDL model IPC routine socket IPC foreign IPC procedures

49 Cutter Trajectory Desired Trajectory contour error 10mm Origin 15mm

50 CNC Controller Motor Simulator procedure sw_code attribute foreign of sw_code is C foreign postponed process interface sw_code(address,data,t_time) wait for t_time-now; multi-func module 1 VHDL simulator Hardware Engines multi-func module 3 C50 compiled model void sw_code(int*,int*,int*) { if TIME % 300 == 0 socket_rw(); } ISR(); asm[pc].func(); Unix socket void main() { do { if TIME % 300 == 0 { socket_wr(); plant_x(); plant_y(); } TIME++; } while(1); }

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