Floating-Point to Field-Tests: A Unified Development Environment for Algorithm Research
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1 Floating-Point to Field-Tests: A Unified Development Environment for Algorithm Research Jared Dulmage Dr. Michael P. Fitz University of California, Los Angeles Annual Research Review 1/13/2008
2 Traditional Hardware Development Process Floating-pt Fixed-pt HW design HW bench test HW field test Matlab HLL (C,C++) debugger HLL (C,C++) compiler Batch tools/scripting Conversion tools/libraries Fixed-point C,C++ model HDL editor/ulator Schematic capture Synthesis tools Hardware probes Test equipment HDL batch tools/scripts Signal visualizations Test vector generator 3+ programming languages 3+ tool chains Slide 2
3 UnWiReD Hardware Development Tools Floating-pt Fixed-pt HW design HW sync co HW async co Matlab Batch scripts Parameter computation Post-processing Off-line analysis General environment and I/O Simulink Long-run, floating-point ulation Source generation Signal visualizations On-line analysis Library of prebuilt functions 2 languages, 1 integrated tool System Generator Hardware design and ulation Automatic synthesis HW-in-the-loop interfaces for hw co- Library of prebuilt hardware functions Slide 3
4 Generic Environment for SW/HW Development Design may be arbitrarily partitioned between hardware and software Non-real-time Single sample interface Limited performance Synchronous interface Fine-grained control plifies debugging Straightforward implementation Software Programmable Advanced debug Access PC resources Relatively static Limited debug Access hardware resources Hardware Real-time capable High performance Block data interface Asynchronous interface Real-time operation for access to external hardware (e.g. ADC/ DAC) Slide 4
5 Development Methodology Floating-pt Fixed-pt Hw design Each subsystem generally evolves according to the diagramed stages A testbench is created in the first stage and used in each subsequent stage Subsystem integration follows the same progression The final collection of models provides a consistent and comprehensive development history HW sync co HW async co Slide 5
6 Fixed point, cycle-true ulation Implemented with System Generator blocks Determine bit widths and precisions Estimate performance degradation Debug hardware design using single-sample interfaces Determine latency properties of design Slide 6
7 Fixed point synchronous co-ulation Hardware co-ulation block generated from fixed-point DUT model Ensure timing closure and correct synthesis Determine resource usage Faster, comprehensive performance testing Slide 7
8 Fixed point asynchronous co-ulation Hardware co-ulation block generated from fixed-point DUT model using shared-memory interfaces Integrate with block data interface Run real-time/accelerated tests ASYNC DUT model Slide 8
9 Conclusions Unified software/hardware development environment improves efficiency Fewer tools means shorter learning curve for developers Abstracted block-diagram interface reduces required expertise Consistent environment facilitates inter-stage coordination among engineering teams Hybrid software/hardware architecture facilitates rapid system development Single, consistent testbench across all design iterations reduces duplicated effort Combines flexibility of general purpose processing (GPP) and high performance of programmable hardware (FPGA) Slide 9
10 Floating Point Simulation Implemented with Simulink blocks Debug algorithms, define data interfaces Measure performance baseline Slide 10
11 DSRC Testbed Hardware Architecture Host PC RF front-end PCI RX I/Q FPGA ADC board DAC coax TX I/Q RF Slide 11
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