This training course provides additional details about the CPU architecture of the MCUs in the M16C/2x and M16C/6x series.

Size: px

Start display at page:

Download "This training course provides additional details about the CPU architecture of the MCUs in the M16C/2x and M16C/6x series."

Frederick Powell
6 years ago
Views:

1 Course Introduction Purpose This training course provides additional details about the CPU architecture of the MCUs in the M16C/2x and M16C/6x series. Objectives Understand the instruction set and addressing modes. Learn about Near and Far memory locations. Discover specialized instructions in the CISC core that reduce code size and increase system performance. Content 22 pages 4 questions Learning Time 33 minutes 1

2 Format of Instructions Op-code Mnemonic Size Specifier Jump-distance Specifier Format Specifier MOV.size.length:format Operation src, dest Operand Example: MOV.W:G Operation R0, R1 Operand 2

3 Memory-Memory Operation Load-Store Register-memory operation is available. M16C Memory-Memory Operation Register-register, register-memory, and memory-memory operations are available. RAM1 1 Reg RAM RAM1 RAM PUSH Reg LDA Reg, RAM1 AND Reg, RAM2 STA Reg, RAM2 Pop Reg 1 AND.B RAM1[SB], RAM2[SB] 6-byte 4-byte

4 Read-Modify-Write Operation Typical MCU Operation LDA Port1, Reg AND #7, Reg STA Reg, Port1 If an interrupt occurs between instruction 1 and instruction 3, the value in Port1 could be changed by another function prior to data being written back. M16C Read-Modify-Write Operation 1 AND.B #7, Port1 Since this is a single instruction, an interrupt will not be accepted until the instruction is completed. Thus, another function won t be able to modify the port content.

5 PROPERTIES On passing, 'Finish' button: On failing, 'Finish' button: Allow user to leave quiz: User may view slides after quiz: User may attempt quiz: Goes to Next Slide Goes to Slide After user has completed quiz After passing quiz Unlimited times

6 Instruction Set Types of Operations Instructions Data Transfer (14) Arithmetic (21) MOV,MOVA,PUSH,PUSHM,PUSHA,POP,POPM,LDE, STE,MOVDir,XCHG,STZ,STNZ,STZX ADD,ADC,ADCF,SUB,SBB,MUL,MULUU, DIV,DIVU,DIVX,DADD,DADC.DSUB,DSBB, INC,DEC,RMPA,CMP,ABS,EXTS,NEG Shift/Logic (10) Branch/Jump (10) Bit Manipulation (14) AND,OR,XOR,NOT,TST,SHL,SHA,ROT,RORC,ROLC JMP,JCnd,JMPI,JMPS,JSR,JSRI,JSRS,RTS,ADJNZ, SBJNZ BCLR,BSET,BNOT,BTST,BNTST,BAND,BNAND, BOR,BNOR,BXOR,BXNOR,BCmd,BTSTS,BTSTC String Instructions (3) Control/ Other Instructions (19) SMOVF,SMOVB,SSTR LDC,STC,LDINTB,LDIPL,PUSHC,POPC,FSET,FCLR LDCTX,STCTX,ENTER,EXITD,BRK,REIT,INT,INTO, UND,WAIT,NOP 6

7 Addressing Modes Addressing Mode Symbol Comment Immediate #imm:8/16 Operands are data to work with. Absolute abs16,abs20 Operands are 16 or 20-bit addresses. Register Direct Rn Operand is register to work on. Address Register Indirect [An] Pointer is formed using value in register indicated in operand. Address Register Relative dsp:8[an] dsp:16[an] dsp:20[an] Same as Address Register Indirect, but with an offset value added to contents of register. SB Relative dsp:8[sb] dsp:16[sb] Pointer is formed by value in SB register plus unsigned displacement. FB Relative dsp:8[fb] Pointer is formed by value in FB register plus signed displacement. SP Relative dsp:8[sp] Pointer is formed by value in SP register plus signed displacement. Program-Counter Relative (special addressing mode) Jump commands 7

Far and Near Memory All address registers are 16 bits wide in the M16C CPU core. MOV instructions can only access Near memory (first 64KB). MOV.B [A0],-1H[FB] MOV.

8 Far and Near Memory All address registers are 16 bits wide in the M16C CPU core. MOV instructions can only access Near memory (first 64KB). MOV.B [A0],-1H[FB] MOV.W -1H[FB],R0 LDE and STE instructions are used to access Far memory (addresses outside the first 64KB). Extended instructions use a 20-bit operand, or a 20-bit operand plus address register, to access total memory area. LDE.B #D0000H[A0],422H LDE.W #D0000H[A0],R0 STE.B R0, #D0000H Extended instructions can also use A1A0 combined to form the address. STE.W 422H, [A1A0] 8

9 High-Speed Operations 60.0% 50.0% 50.8% 60.0% 50.0% There are 10,222 combinations of instructions and addressing modes for the M16C CPU core. 40.0% 30.0% 40.0% 30.0% 20.0% 18.0% 20.0% 11.3% 10.0% 10.0% 2.1% 0.0% 3.3% 3.0% 4.2% 2.4% 3.2% 0.2% 1.4% 0.0% 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7cycle 8 cycle 9 cycle 10 cycle 11cycle more

10 PROPERTIES On passing, 'Finish' button: On failing, 'Finish' button: Allow user to leave quiz: User may view slides after quiz: User may attempt quiz: Goes to Next Slide Goes to Slide After user has completed quiz After passing quiz Unlimited times

11 Specialized Instructions CISC cores have specialized instructions for common tasks that increase the efficiency of the MCU in typical embedded applications. Some of the special instructions that the M16C devices provide are: Multiply Divide Bit Manipulation String Move Forward ENTER/EXITD PUSHM/POPM RMPA SMOVF 11

12 Multiply Instruction MUL.size src, dest dest dest x src src ROL/RO ROH/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] abs16 dest ROL/RO R1 R1L A0/A0 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] abs16 #IMM If you select (.W) for the size specifier, then src and dest both are operated on in 16 bits and the result is stored in 32 bits. If you specified R0, R1, or A0 for dest, then the result is stored in R2R0, R3R1, or A1A0 accordingly. If you select (.B) for the size specifier and the source is an address register, the operation is performed on the address register s eight low-order bits. Examples MUL.B MUL.W MUL.B MUL.W A0, ROL #3, R0 R0L, R1L R0, [A0] Multiplies lower byte of A0 and lower byte of R0 and stores result R0 (16 bits). Multiplies 16 bit R0 by 3 and stores result R2R0 (32 bits). Multiplies lower bytes of R0 and R1 and stores the result in R1. Multiplies value in R0 with value in memory pointed to by A0 and stores the 32-bit result in the location pointed to by A0. 12

13 Divide Instruction DIV.size src src ROL/RO ROH/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] abs16 #IMM If you select (.W) for the size specifier, R0 (quotient), R2 (remainder) R2R0 src If you select (.B) for the size specifier, R0L (quotient), R0H (remainder) R0 src If you select (.B) for the size specifier and source is address register, the operation is performed on the address register s eight low-order bits. Examples DIV.B A0 DIV.W A1 DIV.B -2H[FB] DIV.W -2H[FB] Divides value in R0 by lower byte of A0; R0L is quotient and R0H is remainder. Divides value in R2R0 by word in A1; R0 is quotient and R2 is remainder. Divides R0 by byte in memory (FB register -2); R0L is quotient and R0H is remainder. Divides R2R0 by word in memory (FB register -2); R0 is quotient and R2 is remainder. 13

14 Bit Manipulation Instruction BSET dest BCLR dest Bits can be addressed within a byte, or directly from an offset in a 64Kbit (8KB) range. b7 b0 Example BCLR 3,RAM BCLR 1,R0 BCLR [A0] Operation BSET 42,RAM RAM RAM Set this bit Or BSET 2,RAM+5 RAM

15 String Move Forward Instruction SMOVF.size SIZE = W OR B Repeat M(A1) M(2^16 X R1H + A0) A0 A0 +2 (increments by 1 if size = B) A1 A1 +2 ( increments by 1 is size = B) R3 R3-1 Until R3 = 0 1. If A0 overflows, R1H is incremented. 2. If R3 is set to 0, this instruction is ignored. 3. Only the source can be Far data. 4. If an interrupt occurs, the interrupt will be acknowledged after one data transfer. Note: The M16C architecture also has a SMOVB instruction that decrements the address pointers. 15

16 PROPERTIES On passing, 'Finish' button: On failing, 'Finish' button: Allow user to leave quiz: User may view slides after quiz: User may attempt quiz: Goes to Next Slide Goes to Slide After user has completed quiz After passing quiz Unlimited times

17 Push Multiple Instructions PUSHM src This instruction saves the registers selected by src to the stack area. Registers are saved to the stack area in the following order: b7 b0 FB SB A1 A0 R3 R2 R1 R0 Saved sequentially beginning with FB PUSHM R2,R1,R0 PUSHM FB,SB In this example, the data in R0, R1, and R2 are being saved to the stack and the actual operand value would be 7. In this example, the operand value would be C0 hex. The PUSHM and POPM instructions are also useful when register information must be stored before an operation; e.g., as part of a subroutine call. 17

18 Pop Multiple Instructions POPM dest This instruction restores the registers selected by dest from the stack area. The registers are restored in the following order: b7 b0 FB SB A1 A0 R3 R2 R1 R0 Restored sequentially beginning with R0 POPM R2,R1,R0 In this example, R0, R1, and R2 are being restored from the stack and the operand would be 7. POPM FB,SB In this example, the operand would be C0 hex. 18

19 Optimized C Language Instructions ENTER and EXITD Creates Stack Frame main( ) { } int i, j ; i = j = 0 ; i = j + 5 ;. ENTER #4 [3-byte SP instruction] 2 int. areas (total of 4 bytes) EXITD [2-byte instruction] Return from function. FB Return address PC saved by JSR i j FB Return address SP SP FB Return address Save FB FB Return address FB Removes Stack Frame SP FB Return address Put SP to FB Return address SP FB SP i j FB Return address Move SP by 4 bytes Remove Auto Area Restore FB Return (Restore PC)

20 Sum-of-Products Instruction RMPA.size Multiplicand address : A0 Multiplier address : A1 Sum-of product calculation number : R3 Sum-of products register (result of operation) : R2R0 ( if.w is specified); R0 ( if.b is specified) Example: RMPA.W R2 R0 A0 x a + = R2 R0 Result of operation a R3 x b + = R2 R0 Result of operation b x c + = R2 R0 Result of operation c x d + = R2 R0 Result of operation d A1 If an overflow occurs during operation, the O flag is set to terminate the operation. If an interrupt request is received during instruction execution, the interrupt is acknowledged after the sum-of products addition has been completed. 20

21 PROPERTIES On passing, 'Finish' button: On failing, 'Finish' button: Allow user to leave quiz: User may view slides after quiz: User may attempt quiz: Goes to Next Slide Goes to Slide After user has completed quiz After passing quiz Unlimited times

22 Course Summary Instruction set and addressing modes Execution instruction times Near and Far memory Powerful instructions of the M16C core Multiply Divide Bit Manipulation ENTER/EXITD PUSHM/POPM RMPA SMOVF 22

R8C/Tiny Series Software Manual

Z 16 R8C/Tiny Series Software Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER Rev. 2.00 Revision date: Oct 17, 2005 www.renesas.com Keep safety first in your circuit designs! 1. Renesas Technology Corp.