FP&A Simulation. A Complete Step-by-Step Guide. Ray Salemi

Transcription

1 FP&A Simulation A Complete Step-by-Step Guide Ray Salemi

2 Contents Acknowledgments vii Foreword ix Preface xi The Boiled Frog 1 A Boiled Story 3 Root Cause Analysis 4 The "Verification Complete" Milestone 5 What do you mean by "Verification Complete?" 5 Taking it Step by Step 6 The Quest for the Ultimate Test Bench 6 The Seven Steps to the Ultimate Test Bench 7 Summary 9 Code Coverage 11 The Code Coverage Goal 12 Our Example Design: The TinyCache State Machine 12 FPGA SIMULATION XV

3 Statement Coverage 13 Branch Coverage 15 Condition Coverage 16 Expression Coverage 18 Finite State-Machine Coverage 19 Toggle Coverage 22 Exclusions 22 Summary 23 Test Planning 25 The Virtue of Planning 26 Capture DUT Functionality 27 Listing the DUT Channels 28 Channel Transactions 29 Functionality List 30 Describing Stimulus and Response 32 Defining Stimulus Procedures 33 Describing Output Transactions 34 Create the Test List 36 Summary 37 Introduction to Assertions 39 Introduction to Assertions 40 Implementing Immediate Assertions 40 Immediate Assertions with the assert Statement 42 The SystemVerilog assert 42 Creating an assert in Verilog 45 VHDL assert and report Statements 45 Multicycle Assertions 47 XVI A COMPLETE STEP-BY-STEP GUIDE

4 How to Place Assertions 47 Creating Assertion Blocks 48 Firewall Assertions 49 Protocol Monitors 51 Summary 52 5 The Open Verification Library 53 Checkers vs. Assertions 54 OVL Languages 55 Downloading the OVL 56 6 Verilog Library Primer 59 Verilog Modules 60 Port Mapping in Verilog 60 Verilog Parameters 61 The -y and +iibext+ Command Line Options 62 Verilog include Files 64 Verilog Macros 66 Conditional Compilation 68 The-f Command Line Option 71 Summary 72 FPGA SIMULATION XVII

5 7 Using the OVL with Verilog and SVA 75 The Assertion Module 76 Instantiating OVL Modules 77 Testing the Three- Bit Counter with the OVL 77 Using a Multicycle Checker 82 Compiling with the OVL 87 The OVL Library Information 87 The OVL Include File Information 88 OVL Control Macros 88 The Compiler Option File 88 Summary 89 8 Using the VHDL OVL 91 VHDL Library Management 92 Compiling the VHDL OVL 93 Instantiating VHDL Checkers 94 The OVL Control Record 96 Summary 99 9 Using Assertions in the Lab 101 Synthesizable OVL Checkers 102 The OVL Error Signal 102 Synthesizing Verilog Checkers 103 Synthesizing VHDL Checkers 103 The error Signal 104 Multiple Checkers in One Block 107 Building an Error Tree 109 XVIII A COMPLETE STEP-BY-STEP GUIDE

6 Combining Block Error Signals 110 Creating the Top Level 111 Removing Assertion Hardware 113 Turning Off Assertions in Verilog 114 Removing Assertions in VHDL 115 Summary Introduction to Transactions 119 Transaction-Level Test Benches 120 The TinyALU 121 TinyALU Functional Spec 121 The TinyALU Test Plan 123 TinyALU Transaction-Level Test Bench 124 Summary Creating Transactions 127 Hello, SystemVerilog! 127 Why use SystemVerilog 128 What are Objects? 129 Defining Transactions 132 Common Methods in Transactions 132 Defining Transactions for TinyALU Request Channel 133 Creating Transactions 135 Summary 137 FPGA SIMULATION XIX

7 12 Threads and FIFOs 139 Creating Multiple Threads 140 The Open Verification Methodology (OVM) 143 Downloading and Compiling the OVM 143 Synchronizing Threads 144 Transaction-Level Modules 146 Summary OVM Reporting Tools 151 Basic OVM Reporting Methods 152 Advanced Reporting Control 155 Actions 156 Log Files 157 Controlling OVM Reporting 159 Global Reporting Methods 160 Controlling Actions per Severity and ID 160 Controlling Files per Severity and ID 161 Example of Reporting 162 Summary Moving Transactions in Test Bench 167 A Handle Hazard 168 The Top Level 168 The Producer Module 170 The Consumer Module 172 Running Our Example 173 xx A COMPLETE STEP-BY-STEP GUIDE

8 Safe Handle Handling 173 Fixing the Bug in producer/consumer 176 Choosing When to Clone 178 Summary Creating an RTL Test Bench 181 The RTL Test Bench Architecture 182 The tester Module 183 The responder Module 184 The try_put () end try_get() Methods 187 The driver Module 187 Transaction Printer 192 The TinyALU Top Level 194 Running the TinyALU RTL Test Bench 196 Summary Creating a Transaction Predictor 199 Creating a Transaction-Level Predictor 201 Creating the TinyALU Predictor 202 The predictor Module 203 Running the Simulation 206 Summary 206 FPGA SIMULATION XXI

9 17 Creating a Self-Checking Test Bench 209 Top Level of the Self-Checking Test Bench 210 The tlmf ifo Naming Convention 211 Implementing the Top Level in Code 212 Running the Test Bench 214 Implementing the TinyALU Comparator 215 Summary Introduction to Automatic Stimulus 219 Constrained Random Stimulus Random Numbers in Verilog ' $ random The Mother of all Randomization 226 Tmncating and Sign-Extending $ random 227 Advanced Random-Number Generation 230 Summary 232 XXII A COMPLETE STEP-BY-STEP GUIDE

10 20 Randomizing Objects in SystemVerilog 233 The randomize () Method 234 Declarations with rand and randc 235 The rand Qualifier 236 The randc Qualifier 236 Modifying randomize () Behavior 239 Seeding Randomization 241 Setting the Seed at Runtime 242 Setting the Seed in an Object 242 Turning Randomization On and Off 244 Summary Constraining Random Variables 249 SystemVerilog Constraints 250 The with Keyword 251 Using the with Statement 252 Simple Expressions in Constraints 252 Constraining Random Variables with Sets 255 Ranges in Sets 257 Distribution Constraints 261 Summary 266 FPGA SIMULATION XXIII

11 22 Conditional Randomization 269 The Implication Operator: -> 270 The Implication Operator's Surprising Behavior 271 The solve...before Constraint 275 Controlling Constraints with if...else 277 Summary Constraining Arrays 281 Randomizing Fixed-Size Arrays 281 Randomizing Multidimensional Arrays 285 Randomizing Dynamic Arrays 287 Summary Using Constraints in Objects 291 Adding Constraints to Objects 292 Creating Families of Classes 293 Extending Objects with Constraints 295 Summary 298 XXIV A COMPLETE STEP-BY-STEP GUIDE

12 25 The Constrained Random Test Bench 299 Using the Test Bench 299 The tester Module 302 The run.do Script 304 Examining the Output 306 Limiting Simulation Output 306 The debug Folder 307 Summary Introduction to Functional Coverage 311 What is Functional Coverage? 312 Coverage-Driven Testing 314 Understanding Coverpoints 315 Implementing Coverpoints 316 Summary Signal Coverpoints with the OVL 319 Coverpoints in the OVL 320 OVL Coverage Levels 323 Instantiating OVL Checkers for Coverage 324 Compiling OVL with Functional Coverage 326 FPGA SIMULATION XXV

13 Simulating with OVL Functional Coverage 326 Summary Introduction to Covergroups 329 Understanding Covergroups 330 Covergroups, Coverpoints, and Bins 330 Adding a Covergroup to the tester 331 Defining the Covergroup 332 Creating a New Covergroup 333 Sampling Data with a Covergroup 333 Simulating with Covergroups 334 Summary Defining Data Bins 339 Using Automatic Bins in Numeric Coverpoints 340 Defining Data Bins 341 Bins with Ranges of Values 343 Generating Automatic Bins from Ranges 345 Summary 348 xxvi A COMPLETE STEP-BY-STEP GUIDE

14 30 Transition Coverage 349 Single-Value Transitions 350 Multiple-Value Transitions 352 Testing the Pipeline 354 Repetition Coverage 355 Consecutive Repetition 356 Nonconsecutive Repetition 357 Summary Cross Coverage 361 Basic Cross Coverage 362 Cross Coverage and the TinyALU 366 Combining Cross-Coverage Bins 368 Combining binsof Operations 371 Ignore Bins 373 The intersect Qualifier 374 Implementing the TinyALU Coverpoints 376 Summary Take the First Step 381 Simulate Today! 382 Lousy First Drafts 383 Join the Community 383 Summary 384 Index 385 FPGA SIMULATION XXVII