SystemVerilog For Design Second Edition

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1 SystemVerilog For Design Second Edition A Guide to Using SystemVerilog for Hardware Design and Modeling by Stuart Sutherland Simon Davidmann Peter Flake Foreword by Phil Moorby 4y Spri ringer

Table of Contents Foreword Preface Target audience Topics covered About the examples in this book Obtaining copies of the examples Example testing Other sources of information Acknowledgements xxi

2 Table of Contents Foreword Preface Target audience Topics covered About the examples in this book Obtaining copies of the examples Example testing Other sources of information Acknowledgements xxi xxiii xxiii xxiv xxv xxvi xxvi xxvii xxx Chapter 1: Introduction to SystemVerilog SystemVerilog origins Generations of the SystemVerilog Standard Donations to SystemVerilog Key SystemVerilog enhancements for hardware design Summary 6 Chapter 2: SystemVerilog Declaration Spaces Packages Package definitions Referencing package contents Synthesis guidelines Sunit compilation-unit declarations Coding guidelines SystemVerilog identifier search rules Source code order Coding guidelines for importing packages into Sunit Synthesis guidelines Declarations inunnamed Statement blocks Local variables in unnamed blocks Simulation time units and precision Verilog's timescale directive Time values with time units Scope-level timeunit and precision 31

2.4.4 Compilation-unit time units and precision 32 2.5 Summary 34 Chapter 3: SystemVerilog Literal Values and Built-in Data Types 37 3.1 Enhanced literal value assignments 38 3.

3 2.4.4 Compilation-unit time units and precision Summary 34 Chapter 3: SystemVerilog Literal Values and Built-in Data Types Enhanced literal value assignments 'define enhancements Macro argument Substitution within strings Constructing identifier names from macros SystemVenlog variables Object types and data types System Verilog 4-state variables System Verilog 2-state variables Explicit and implicit variable and net data types Synthesis guidelines Using 2-state types in RTL modeis state type characteristics state types versus 2-state Simulation Using 2-state types with case Statements Relaxation of type rules Signed and unsigned modifiers Static and automatic variables Static and automatic variable initialization Synthesis guidelines for automatic variables Guidelines for using static and automatic variables Deterministic variable initialization Initialization determinism Initializing sequential logic asynchronous inputs Type casting Static (compile time) casting Dynamic casting Synthesis guidelines Constants Summary 72 Chapter 4: System Verilog User-Deflned and Enumerated Types User-defmed types Local typedef defmitions Shared typedef defmitions Naming Convention for user-defmed types Enumerated types Enumerated type label sequences 83 viii

4.2.2 Enumerated type label scope 83 4.2.3 Enumerated type values 84 4.2.4 Base type of enumerated types 85 4.2.5 Typed and anonymous enumerations 86 4.2.6 Streng typing on enumerated type Operations 86 4.

4 4.2.2 Enumerated type label scope Enumerated type values Base type of enumerated types Typed and anonymous enumerations Streng typing on enumerated type Operations Casting expressions to enumerated types Special System tasks and methods for enumerated types Printing enumerated types Summary 93 Chapter 5: SystemVerilog Arrays, Structures and Unions Structures Structure declarations Assigning values to structures Packed and unpacked structures Passing structures through ports Passing structures as arguments to tasks and functions Synthesis guidelines Unions Unpacked unions Tagged unions Packed unions Synthesis guidelines An example of using structures and unions Arrays Unpacked arrays Packed arrays Using packed and unpacked arrays Initializing arrays at declaration Assigning values to arrays Copying arrays Copying arrays and structures using bit-stream casting Arrays of arrays Using user-defined types with arrays Passing arrays through ports and to tasks and functions Arrays of structures and unions Arrays in structures and unions Synthesis guidelines An example of using arrays The foreach array looping construct 130 ix

5.5 Array querying System functions 132 5.6 The Sbits "sizeof System function 134 5.7 Dynamic arrays, associative arrays, sparse arrays and strmgs 135 5.

5 5.5 Array querying System functions The Sbits "sizeof System function Dynamic arrays, associative arrays, sparse arrays and strmgs Summary 136 Chapter 6: SystemVerilog Procedural Blocks, Tasks and Functions Verflog general purpose always procedural block SystemVerilog specialized procedural blocks Combinational logic procedural blocks Latched logic procedural blocks Sequential logic procedural blocks Synthesis guidelines Enhancements to tasks and functions Implicit task and function Statement grouping Returning function values Returning before the end of tasks and functions Void functions Passing task/function arguments by name Enhanced function formal arguments Functions with no formal arguments Default formal argument direction and type Default formal argument values Arrays, structures andunions as formal arguments Passing argument values by reference instead of copy Named task and function ends Empty tasks and functions Summary 166 Chapter 7: SystemVerilog Procedural Statements New Operators Increment and decrement Operators Assignment Operators Equality Operators with don't care wildcards Set membership Operator inside Operand enhancements Operations on 2-state and 4-state types Type casting Size casting Sign casting Enhanced for loops Local variables within for loop declarations 183 x

7.3.2 Multiple for loop assignments 185 7.3.3 Hierarchically referencing variables declared in for loops 185 7.3.4 Synthesis guidelines 186 7.4 Bottom testing do...while loop 186 7.4.1 Synthesis guidelines 188 7.

6 7.3.2 Multiple for loop assignments Hierarchically referencing variables declared in for loops Synthesis guidelines Bottom testing do...while loop Synthesis guidelines The foreach array looping construct Newjump Statements break, continue, return The continue Statement The break Statement The return Statement Synthesis guidelines Enhanced block names Statement labeis Enhanced case Statements Unique case decisions Priority case Statements Unique and priority versus parallel_case and full_case Enhanced if...else decisions Unique if...else decisions Priority if decisions Summary 206 Chapter 8: Modeling Finite State Machines with SystemVerilog Modeling State machines with enumerated types Representing State encoding with enumerated types Reversed case Statements with enumerated types Enumerated types and unique case Statements Specifying unused State values Assigning State values to enumerated type variables Performing Operations on enumerated type variables Using 2-state types in FSM modeis Resetting FSMs with 2-state and enumerated types Summary 221 Chapter 9: SystemVerilog Design Hierarchy Module prototypes Prototype and actual definition Avoidingport declaration redundancy Named ending Statements Named module ends Named code block ends 226 xi

9.3 Nested (local) module declarations 227 9.3.1 Nested module name visibility 230 9.3.2 Instantiating nested modules 231 9.3.3 Nested module name searchrules 232 9.

7 9.3 Nested (local) module declarations Nested module name visibility Instantiating nested modules Nested module name searchrules Simplified netlists of module instances Implicit.name port connections Implicit.* port connection Netaliasing Alias rules Implicit net declarations Using aliases with.name and.* Passing values through module ports All types canbe passed through ports Module port restrictions in System Verilog Reference ports Reference ports as shared variables Synthesis guidelines Enhanced port declarations Verilog-1995 port declarations Verilog-2001 port declarations SystemVerilog port declarations Parameterized types Summary 261 Chapter 10: SystemVerilog Interfaces Interface concepts Disadvantages of Verilog's module ports Advantages of SystemVerilog interfaces SystemVerilog interface contents Differences between modules and interfaces Interface declarations Source code declaration order Global and local interface defmitions Using interfaces as module ports Explicitly named interface ports Generic interface ports Synthesis guidelines Instantiating and connecting interfaces Referencing signals within an interface Interface modports 281 xii

10.6.1 Specifying which modport view to use 282 10.6.2 Using modports to define different sets of connections 286 10.7 Using tasks and functions in interfaces 288 10.7.1 Interface methods 289 10.7.2 Importing interface methods 289 10.

8 Specifying which modport view to use Using modports to define different sets of connections Using tasks and functions in interfaces Interface methods Importing interface methods Synthesis guidelines for interface methods Exporting tasks and functions Using procedural blocks in interfaces Reconfigurable interfaces Verification with interfaces Summary 299 Chapter 11: A Complete Design Modeled with SystemVerilog SystemVerilog ATM example Data abstraction Interface encapsulation Design top level: squat Receivers and transmitters Receiver State machine Transmitter State machine Testbench Summary 327 Chapter 12: Behavioral and Transaction Level Modeling Behavioral modeling What is a transaction? Transaction level modeling in SystemVerilog Memory Subsystem example Transaction level modeis via interfaces Bus arbitration Transactors, adapters, andbus functional modeis Master adapter as module Adapter in an interface More complex transactions Summary 354 Appendix A: The SystemVerilog Formal Definition (BNF) 355 Appendix B: Verilog and SystemVerilog Reserved Keywords 395 Appendix C: A History of SUPERLOG, the Beginning of SystemVerilog 401 Index 415 xiii

SystemVerilog Essentials Simulation & Synthesis

SystemVerilog Essentials Simulation & Synthesis Course Description This course provides all necessary theoretical and practical know-how to design programmable logic devices using SystemVerilog standard