Post processing techniques to accelerate assertion development Ajay Sharma
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1 Post processing techniques to accelerate assertion development Ajay Sharma 2014 Synopsys, Inc. All rights reserved. 1
2 Agenda Introduction to Assertions Traditional flow for using ABV in Simulations/Emulation/Prototyping Post processing Assertions using a structured and open events database. Summary and Conclusions 2014 Synopsys, Inc. All rights reserved. 2
3 Assertion Based Verification Historical Perspective Assertions are not new! Widely used in software development (Java // assert <expr> ; ) Designers frequently add verification code //synopsys translate_off if(full & new_req) $display ( Error: buffer overflow. ); //synopsys translate_on VHDL includes the keyword assert The Accellera Open Verification Library 2014 Synopsys, Inc. All rights reserved. 3
4 What is an Assertion? A piece of verification code used to check a property correct/illegal behavior assumptions/constraints coverage goals Examples: Interface A must follow the PCI protocol Bus B must be one-hot The FIFO must never overflow I want to see back-to-back reads/writes Write will follow read after 3 cycles 2014 Synopsys, Inc. All rights reserved. 4
5 Why Use Assertions in Verification? Traditional Flow Has Multiple Entry Points For Introducing Bugs Specs (text and timing diagrams) Write checking code Create monitors Ad hoc definition/methods Rewrite properties Simulation Testbench Coverage Formal analysis Text and timing diagrams are not tool consumable Separate manual conversion for every tool Involves multiple persons, assumptions made Need better way to communicate Spec to Verification tools 2014 Synopsys, Inc. All rights reserved. 5
6 Why Use Assertions in Verification? Concise Description of Temporal Behavior Fewer lines of code, faster to write Reduced chance of error Error Localization White-box assertions may be placed close (physically and temporally) to possible bug sources Faster debug of failures Block-to-System Portability White-box and interface checks are carried along with the RTL as it is integrated into a system. Maximize re-use of block-level verification efforts Formal, Simulation, & Hardware Usage Use in both static and dynamic environments maximizes the chance of finding errors Portable to emulation and FPGA s 2014 Synopsys, Inc. All rights reserved. 6
7 ABV Challenges SW and HW Intent Understanding and integrating assertions at intended part of the design How easy and quick is it to correct mistakes? Statistics Getting the overall metric report from the run. Debugging? Why did the assertion FAIL Speed For large designs, slow run time for simulation/emulation Resource Capacity constraints on FPGA s used for Prototyping 2014 Synopsys, Inc. All rights reserved. 7
8 Debug Assertion checks using FSDB Traditional Assertions Design - RTL Simulator FSDB Evaluator Statistics Emulator Prototyping Vendor independent FSDB format Supports all SVA types Easy to Debug Source/Waves/Statistics Root cause Analysis Assertions Errors Design 2014 Synopsys, Inc. All rights reserved. 8
9 Assertions in Simulation 2014 Synopsys, Inc. All rights reserved. 9
10 Synthesizable assertions in Emulation Subset of the SVA language is synthesizable SVA can consume lot of hardware resources Live-Processed (like simulator) or Post processing available Enable SVA support Select which SVA to synthesize 2014 Synopsys, Inc. All rights reserved. 10
11 Zebu Emulation : Simulator-like Debug RTL & Gate-Level Hierarchical Debug Full visibility (RTL & gate level) All registers, nodes, memories Run-time assertions control No recompiles required Open standard support FSDB, VCD, etc. Runtime Control 2014 Synopsys, Inc. All rights reserved. 11
12 Hi-Speed Transport IP Protolink: Full visibility from Prototype PCIe Card (x8 Lane) Fiber Cable HAPS & Custom Boards Protolink Controller Samtec Cable Workstation Link ProtoLink Interface Card Probe Bus Prototype Board Debug Interface HW Transport IP 2014 Synopsys, Inc. All rights reserved. 12
13 Protolink Advance Probes Assertion-based Create a probe based on an assert property Merge assertion triggers on the PLC 2014 Synopsys, Inc. All rights reserved. 13
14 Protolink Advance Probes Assertion based Simulation result: ProtoRun dump: Probe shows high when the assertion fails 2014 Synopsys, Inc. All rights reserved. 14
15 Advanced Assertions Debug Platform 2014 Synopsys, Inc. All rights reserved. 15
16 Assertion Statistics Overall assertion result view for the simulation run Support Multi-FSDB Gives you a hint for the design quality Detail information for the property Check assertion fail/success along the time Sync with waveform Quick access to Assertion Analyzer Text report for further re-use Statistics 2014 Synopsys, Inc. All rights reserved. 16
17 Assertion Analyzer Assertion Analyzer Industry leading assertion debugging environment Intuitive way to debug assertion fail Analyze sub expressions in assertion statement Display variable value with different time on the same expression Insert related waveform into waveform window Direct link to HDL debug environment Assertion Analyzer Related waveforms 2014 Synopsys, Inc. All rights reserved. 17
18 Debug Post processing Assertion Checks Assertions FSDB Evaluator Statistics Root cause Analysis Design - RTL Simulator Emulator Prototyping Post processing of assertions on functionally correct events database (FSDB) Speed no need to re-compile design Check low-level implementation assertions with short TAT Flexibility Vendor Independent Evaluated fsdb Assertions Errors Design 2014 Synopsys, Inc. All rights reserved. 18
19 Assertion Manager Assertion Manager Manage assertion in the design Table View Hierarchy Tree View Control which assertion need to be checked Active and inactive number for assertion check Hierarchical View Table view 2014 Synopsys, Inc. All rights reserved. 19
20 Post processing Assertion Evaluator FSDB from Sim/Emulation/prototyping run Assertion Evaluation Engine Assertion source code Complete Assertion and Design waveform Assertion check control Virtual FSDB Post processing Assertion Check Reduce simulation time Quick way to get assertion result Check the assertion need to be checked Transparent Virtual FSDB No database merge needed 2014 Synopsys, Inc. All rights reserved. 20
21 Complete Assertion Debug Flow Verdi provides complete Assertion solution From assertion evaluate to HDL debug A full debug loop from assertion to HDL Quicker assertion eval. Engine No re-simulate needed Shorten assertion develop time Quicker debug cycle Better assertion visualization Help to analyze assertion Locate the problem quicker and easier HDL debug Assertion Analysis and debug Assertion Evaluation Engine Complete Assertion and HDL waveform Assertion Statistics 2014 Synopsys, Inc. All rights reserved. 21
22 Conclusions Writing assertions finds spec ambiguities Methodology transparent Having a common platform for analysing and Debugging ABV methodology is a huge productivity boost Speed up in iterations time in qualifying new assertions can be achieved using the post processing methods 2014 Synopsys, Inc. All rights reserved. 22
23 2014 Synopsys, Inc. All rights reserved. 23
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