Embedded system functionality aspects

Transcription

1 INTERFACING

2 Introduction Embedded system functionality aspects Processing Transformation of data Implemented using processors Storage Retention of data Implemented using memory Communication Transfer of data among processors, memories or I/O devices Implemented using buses(serial, etc.) Called interfacing

3 Interfacing

4 Interfacing Communication a process of transferring information from one entity to another I/O interfacing a process of transferring information between a processor and an I/O interface Why we need an interface logic? I/O devices usually includes some non-digital components Data usually has a different format and not synchronized to the CPU I/O device (interface) Memory interface CPU memory CPU status reg data reg mechanism I/O interface CPU status reg data reg status reg data reg mechanism CPU status reg data reg Network comm status reg data reg CPU

5 Communication Means of transferring bits Wired or Wireless Physical connectivity scheme Serial or Parallel Protocol A set of rules which is used by computers to A set of rules which is used by computers to communicate with each other

6 Advanced communication principles Layering Break complexity of communication protocol into pieces easier to design and understand Lower levels provide services to higher level Lower level might work with bits while higher level might work with packets of data Physical layer Lowest level in hierarchy Medium to carry data from one actor (device or node) to another Parallel communication Physical layer capable of transporting multiple bits of data Serial communication Physical layer transports t one bit of data at a time Wireless communication No physical connection needed for transport at physical layer

7 Parallel communication Multiple l data, control, and possibly power wires One bit per wire High data throughput with short distances Typically used when connecting devices on same IC or same circuit board Bus must be kept short long parallel l wires result in high h capacitance values which h requires more time to charge/discharge Data misalignment between wires increases as length increases Higher cost, bulky

8 Serial communication Single data wire, possibly also control and power wires Words transmitted by one bitatatime a time Higher data throughput with long distances Less average capacitance, so more bits per unit of time Cheaper, less bulky More complex interfacing logic and communication protocol Sender needs to decompose word into bits Receiver needs to recompose bits into word Control signals often sent on same wire as data increasing protocol complexity

9 Interfacing between CPU and Peripherals

10 How to communicate with the registers in the interface A microprocessor communicates with other devices using some of its pins Port-based I/O Processor has one or more N-bit ports Processor s software reads and writes a port just like a register E.g., P0 = 0xFF; v = P1.2; -- P0 and P1 are 8-bit ports Bus-based I/O Processor has address, data and control ports that form a single bus Communication protocol is built into the processor A single instruction carries out the read or write protocol on the bus CPU status reg data reg me echanism

11 Ports Conducting device on periphery Connects bus to processor or memory Often referred to as apin Actual pins on periphery of IC package that plug into socket on printedcircuit board Single wire or set of wires with single function E.g., 12-wire address port rd'/wr Processor Memory port enable addr[0-11] or Peripherals (I/O devices) data[0-7] bus

12 Compromises/extensions Processor Memory Parallel I/O peripheral When processor only supports busbased I/O but parallel I/O needed Each port on peripheral connected to a register within peripheral that t is read/written by the processor System bus Parallel I/O peripheral Extended parallel I/O When processor supports portbased I/O but more ports needed One or more processor ports interface with parallel I/O peripheral extending total number of ports available for I/O e.g., extending 4 ports to 6 ports in figure Port A Port B Port C Adding parallel I/O to a busbased I/O processor Processor Port 0 Port 1 Port 2 Port 3 Parallel I/O peripheral Port A Port B Port C Extended parallel I/O

13 Bus-based I/O (a simple bus) Wires: Uni-directional or bi-directional One line may represent multiple wires Processor Memory Bus enable Set of wires with a single function Address bus, data bus Or, entire collection of wires Address, data and control Associated protocol: rules for communication rd'/wr addr[0-11] data[0-7] bus bus structure or Peripherals (I/O devices)

14 Timing Diagrams Most common method for describing a communication protocol Time proceeds to the right on x-axis Control signal: low or high May be active low (e.g., go, /go, or go_l) Use terms assert (active) and deassert Asserting ggo means go=0 Data signal: not valid or valid Protocol may have subprotocols Called bus cycle, e.g., read and write Each may be several clock cycles Read example rd /wr set low,address placed on addr for at least t setup time before enable asserted, enable triggers memory to place data on data wires by time t read rd'/wr enable addr data rd'/wr enable addr data t setup t read read protocol t setup t write write protocol

15 Basic protocol concepts Actor: master initiates, servant (slave) respond Direction: sender, receiver Addresses: special kind of data Specifies a location in memory, a peripheral, p or a register within a peripheralp Time multiplexing Share a single set of wires for multiple pieces of data Saves wires at expense of time Master data(15:0) req Time-multiplexed data transfer Servant Master data(15:0) req Servant addr data addr data mux data(8) demux mux addr/data demux req req data 15:8 7:0 addr/data addr data data serializing address/data muxing

16 Basic protocol concepts: control methods Master req Servant Master req Servant ack data data req 1 3 req 1 3 data 2 4 ack 2 4 data t access 1. Master asserts req to receive data 2. Servant puts data on bus within time t access 3. Master receives data and deasserts req 1. Master asserts req to receive data 2. Servant puts data on bus and asserts ack 3. Master receives data and deasserts req 4. Servant ready for next request 4. Servant ready for next request Strobe protocol Handshake protocol

17 A strobe/handshake compromise Master req wait data Servant req wait 1 3 req 5 t access data 2 4 data t access 1. Master asserts req to receive data 1. Master asserts req to receive data 2. Servant puts data on bus within time t access (wait line is unused) 3. Master receives data and deasserts req 4. Servant ready for next request 2. Servant can't put data within t access, asserts wait ack 3. Servant puts data on bus and deasserts wait 4. Master receives data and deasserts req 5. Servant ready for next request wait Fast-response case Slow-response case

18 ISA bus protocol memory access ISA: Industry Standard Architecture Common in 80x86 s Features 20-bit address Compromise strobe/handshake control 4 cycles default Unless CHRDY deasserted resulting in additional wait cycles (up to 6) Microprocessor Memory I/O Device ISA bus memory-read bus cycle CYCLE C1 C2 WAIT C3 C4 CLOCK D[7-0] A[19-0] ALE /MEMR CHRDY CYCLE CLOCK D[7-0] A[19-0] ALE /MEMW CHRDY ADDRESS memory-write bus cycle C1 C2 WAIT C3 C4 ADDRESS DATA DATA

19 PCI Bus protocol PCI Bus (Peripheral Component Interconnect) t) High performance bus originated at Intel in the early 1990 s Standard adopted by industry and administered by PCISIG (PCI Special Interest Group) Interconnects chips, expansion boards, processor memory subsystems Data transfer rates of to Mbits/s and 32-bit addressing Later extended to 64-bit while maintaining compatibility with 32-bit schemes Synchronous bus architecture t Multiplexed data/address lines

20 Multilevel bus architectures Don t want one bus for all communication Peripherals would need high-speed, processor-specific bus interface excess gates, power consumption, and cost; less portable Too many peripherals slows down bus Processor-local bus High speed, wide, most frequent communication High speed, wide, most frequent communication Connects microprocessor, cache, memory controllers, etc. Peripheral bus Lower speed, narrower, less frequent communication Typically industry standard bus (ISA, PCI) for portability

21 Multilevel bus architectures, cont d Bridge Single-purpose processor converts communication between busses Microprocessor Cache Memory controller DMA controller Processor-local bus Peripheral Peripheral Peripheral Bridge Peripheral bus

22 ARM Bus protocol ARM Bus Designed and used internally by ARM Corporation Interfaces with ARM line of processors Many IC design companies have own bus protocol 32-bit addressing AMBA (Advanced Microcontroller Bus Architecture) Advanced High-performance Bus (AHB) Advanced System Bus (ASB) Advanced Peripheral Bus (APB)

23 Types of bus-based I/O: memory-mapped I/O and standard d I/O Processor talks to both memory and peripherals using same bus two ways to talk to peripherals Memory-mapped I/O Peripheral registers occupy addresses in same address space as memory e.g., Bus has 16-bit address lower 32K addresses may correspond to memory upper 32k addresses may correspond to peripherals Standard d I/O (I/O-mapped I/O) Additional pin (M/IO) on bus indicates whether a memory or peripheral access e.g., Bus has 16-bit address all 64K addresses correspond to memory when M/IO set to 0 all 64K addresses correspond to peripherals when M/IO set to 1

24 Advantages and disadvantages Memory-mapped I/O Requires no special instructions Assembly instructions involving memory like MOV and ADD work with peripherals as well Standard I/O requires special instructions (e.g., IN, OUT) to move data between peripheral registers and memory Standard I/O No loss of memory addresses to peripherals Simpler address decoding logic in peripherals possible When number of peripherals much smaller than address space then high-order address bits can be ignored smaller and/or faster comparators

25 ISA bus ISA supports standard I/O /IOR distinct from /MEMR for peripheral read /IOW used for writes 16-bit address space for I/O vs. 20-bit address space for memory Otherwise very similar il to memory protocol CYCLE CLOCK D[7-0] A[15-0] ALE /IOR CHRDY ISA I/O bus read protocol C1 C2 WAIT C3 C4 ADDRESS DATA

26 Modes of Transfer Suppose a peripheral intermittently itt tl receives data, which must be serviced by the processor The processor can poll the peripheral regularly to see if data has arrived wasteful The peripheral can interrupt the processor when it has data Modes of Transfer Data transfer under program control (Programmed I/O) Busy-waiting, Polling Interrupt DMA transfer

27 Programmed I/O Two types of instructions can support I/O Standard I/O special-purpose I/O instructions Memory-mapped I/O memory-mapped load/store instructions Intel x86 provides in, out instructions Most other CPUs use memory-mapped I/O I/O instructions do not preclude memory-mapped I/O

28 Busy/wait output Simplest way to program device Use instructions to test when device is ready current_char = mystring; while (*current_char!= \0 ) { poke(out_char,*current_char); while (peek(out_status)!= 0); current char++; }

29 ARM memory-mappedmapped I/O Define location for device: DEV1 EQU 0x1000 Read/write code: LDR r1,#dev1 ; set up device adrs LDR r0,[r1] ; read DEV1 LDR r0,#8 ; set up value to write STR r0,[r1] ; write value to device

30 Interrupt-driven I/O Busy/wait is very inefficient (Why?) CPU can t do other work while testing device Hard to do simultaneous I/O Interrupts allow a device to change the flow of control in the CPU Causes subroutine call to handle device

31 Interrupt interface IR CPU PC intreq intack data/address status reg data reg mechanis sm Requires extra pins: intreq, intack If intreq is 1, processor suspends current program, jumps to an Interrupt Service Routine, or ISR Known as interrupt-driven I/O Essentially, polling of the interrupt pin is built-into the hardware, so no extra time!

32 Interrupt sequence CPU acknowledges request Device sends vector CPU calls ISR Execution of ISR CPU restores state to foreground program

33 Priorities and vectors Two mechanisms allow us to make interrupts more specific: Priorities determine what interrupt gets CPU first Vectors determine what code is called for each type of interrupt Mechanisms are orthogonal: most CPUs provide both

34 Interrupts - Vectors What is the address (interrupt address vector) of the ISR? Fixed interrupt Address built into microprocessor, cannot be changed Either ISR stored at address or a jump to actual ISR stored if not enough bytes available Vectored interrupt Peripheral must provide the address Common when microprocessor has multiple peripherals p connected by a system bus Compromise: interrupt address table

35 Interrupt-driven I/O using vectored interrupt t Time 1(a): μp is executing its main program. 1(b): P1 receives input data in a register with address 0x : After completing instruction at 100, μp sees Int asserted, saves the PC s value of 100, and asserts Inta. 2: P1 asserts Int to request servicing by the microprocessor. 4: P1 detects Inta and puts interrupt address vector 16 on the data bus. 5(a): μp jumps to the address on the bus (16). The ISR there reads data from 0x8000, modifies the data, and writes the resulting data to 0x (b): After being read, P1 deasserts Int. 6: The ISR returns, rns thus restoring PC to 100+1=101, where μp resumes executing.

36 Interrupt-driven I/O using vectored interrupt t 1(a): P is executing its main program 1(b): P1 receives input data in a register with address 0x8000. Program memory μp ISR 16: MOV R0, 0x : # modifies R0 18: MOV 0x8001, R0 19: RETI # ISR return... Inta Main program Int... PC 100: instruction 101: instruction 100 Data memory System bus P1 P2 16 0x8000 0x8001

37 Interrupt-driven I/O using vectored interrupt t 2: P1 asserts Int to request servicing by the microprocessor Program memory μp ISR 16: MOV R0, 0x : # modifies R0 18: MOV 0x8001, R0 19: RETI # ISR return... Inta Main program Int... PC 100: instruction 101: instruction Data memory System bus P1 P2 16 0x8000 0x8001

38 Interrupt-driven I/O using vectored interrupt t 3: After completing instruction at 100, μp sees Int asserted, saves the PC s value of 100, and asserts Inta Program memory μp Data memory ISR 16: MOV R0, 0x : # modifies R0 System bus 18: MOV 0x8001, R0 19: RETI # ISR return... Inta 1 P1 P2 Main program Int... PC : instruction 0x8000 0x : instruction 100

39 Interrupt-driven I/O using vectored interrupt t 4: P1 detects Inta and puts interrupt address vector 16 on the data bus Program memory μp Data memory ISR 16: MOV R0, 0x : # modifies R0 16 System bus 18: MOV 0x8001, R0 19: RETI # ISR return... Inta P1 P2 Main program Int... PC : instruction 0x8000 0x : instruction 100

40 Interrupt-driven I/O using vectored interrupt t 5(a): PC jumps to the address on the bus Program memory μp Data memory (16). The ISR there reads data from ISR 0x8000, modifies the data, and writes the 16: MOV R0, 0x8000 System bus resulting data to 0x : # modifies R0 18: MOV 0x8001, R0 19: RETI # ISR return... Inta 5(b): After being read, P1 deasserts Int. P1 P2 Main program Int... PC : instruction 0x8000 0x : instruction 100

41 Interrupt-driven I/O using vectored interrupt t 6: The ISR returns, thus restoring the PC to 100+1=101, where the μp resumes Program memory μp ISR 16: MOV R0, 0x : # modifies R0 18: MOV 0x8001, R0 19: RETI # ISR return... Int Main program... PC 100: instruction 101: instruction Data memory System bus P1 P2 0x8000 0x8001

42 Interrupt address table Compromise between fixed and vectored interrupts One interrupt pin Table in memory holding ISR addresses (maybe 256 words) Peripheral doesn t provide ISR address, but rather index into table Fewer bits are sent by the peripheral Can move ISR location without changing peripheral

43 Additional interrupt issues Maskable vs. non-maskable interrupts t Maskable: programmer can set bit that causes processor to ignore interrupt Important when in the middle of time-critical code Non-maskable: a separate interrupt pin that can t be masked Typically y reserved for drastic situations, like power failure requiring immediate backup of data to non-volatile memory Jump to ISR Some microprocessors treat jump same as call of any subroutine Complete state saved (PC, registers) may take hundreds of cycles Others only save partial state, like PC only Thus, ISR must not modify registers, or else must save them first Assembly-language programmer must be aware of which registers stored

44 Arbitration: Priority arbiter Consider the situation where multiple peripherals request service from single resource (e.g., microprocessor, DMA controller) simultaneously - which gets serviced first? Pi Priorityit arbiter Single-purpose processor Peripherals make requests to arbiter, arbiter makes requests to resource Arbiter connected to system bus for configuration only Microprocessor Inta Int 5 3 System bus Priority arbiter Ireq1 Iack1 Ireq2 6 7 Peripheral1 Peripheral2 2 2 Iack2

45 Arbitration using a priority arbiter Microprocessor Inta Int 5 3 System bus Priority arbiter Ireq1 Iack1 Ireq2 6 7 Peripheral1 Peripheral2 2 2 Iack Microprocessor is executing its program Peripheral1 needs servicing so asserts Ireq1. Peripheral2 also needs servicing so asserts Ireq Priority arbiter sees at least one Ireq input asserted, so asserts Int Microprocessor stops executing its program and stores its state Microprocessor asserts Inta Priority arbiter asserts Iack1 to acknowledge Peripheral Peripheral1 puts its interrupt address vector on the system bus Microprocessor jumps to the address of ISR read from data bus, ISR executes and returns 9. (and completes handshake with arbiter) Microprocessor resumes executing its program.

46 Arbitration: Priority arbiter Types of priority i Fixed priority each peripheral has unique rank highest rank chosen first with simultaneous requests preferred when clear difference in rank between peripherals Rotating priority (round-robin) priority changed based on history of servicing better distribution of servicing especially among peripherals with similar priority demands

47 Arbitration: Daisy-chain arbitration Arbitration done by peripherals Built into peripheral or external logic added req input and ack output added to each peripheral Peripherals connected to each other in daisy-chain manner One peripheral connected to resource, all others connected upstream Peripheral s req flows downstream to resource, resource s ack flows upstream to requesting peripheral Closest peripheral has highest priority P System bus Inta Int Peripheral1 Ack_in Ack_out Req_out Req_in Peripheral2 Ack_in Ack_out Req_out Req_in 0 Daisy-chain aware peripherals

48 Arbitration: Daisy-chain arbitration Microprocessor Inta Int Pros/cons Easy to add/remove peripheral - no system redesign needed Does not support rotating priority One broken peripheral can cause loss of access to other peripherals System bus P Priority arbiter Peripheral 1 Peripheral 2 Inta Peripheral1 Ack_in Ack_out Peripheral2 Ack_in Ack_out Ireq1 Int Req_out Req_in Req_out Req_in Iack1 Ireq2 Iack2 Daisy-chain aware peripherals System bus 0

49 Intel 8259 programmable priority controller D[7..0] A[0..0] RD WR INT INTA CAS[2..0] SP/EN Intel 8259 IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 Signal D[7..0] A[0..0] WR Descrip tion These wires are connected to the system bus and are used by the microprocessor to write or read the internal registers of the This pin actis in cunjunction with WR/RD signals. It is used by the 8259 to decipher various command words the microprocessor writes and status the microprocessorrocessor wishes to read. When this write signal is asserted, the 8259 accepts the command on the data line, i.e., the microprocessor writes to the 8259 by placing a command on the data lines and asserting this signal. RD When this read signal is asserted, the 8259 provides on the data lines its status, i.e., the microprocessor reads the status of the 8259 by asserting this signal and reading the data lines. INT This signal is asserted whenever a valid interrupt request is received by the 8259, i.e., it is used to interrupt the microprocessor. INTA This signal, is used to enable 8259 interrupt-vector data onto the data bus by a sequence of interrupt acknowledge pulses issued by the microprocessor. IR An interrupt request is executed by a peripheral device when one of these signals is ,1,2,3,4,5,6,7 asserted. CAS[2..0] SP/EN These are cascade signals to enable multiple 8259 chips to be chained together. This function is used in conjunction with the CAS signals for cascading purposes.

50 Sources of interrupt overhead ISR execution time Interrupt mechanism overhead Register save/restore Pipeline-related penalties Cache-related penalties

51 ARM interrupts ARM7 supports two types of interrupts: Fast interrupt requests (FIQs) Interrupt requests (IRQs) Exception table starts at location 0 0xFFFF0000 if high vector address is defined

52 Exception processing modes Exception type Mode Normal address High vector address Reset Supervisor 0x xFFFF0000 Undefined instructions Undefined 0x xFFFF0004 SWI Supervisor 0x xFFFF0008 Prefetch Abort Abort 0x C 0xFFFF000C Data Abort Abort 0x xFFFF0010 IRQ IRQ 0x xFFFF0018 FIQ FIQ 0x C 0xFFFF001C

53 Priorities priority highest 1 exception Reset 2 Data Abort 3 FIQ 4 IRQ 5 Prefetch Abort lowest 6 Undefined, SWI

54 ARM interrupt procedure CPU actions: Save PC. Copy CPSR to SPSR Force bits in CPSR to record interrupt Force PC to vector Handler responsibilities: Restore proper PC Restore CPSR from SPSR Clear interrupt disable flags

55 Interrupt request exception IRQ is generated externally by asserting the IRQ input on the processor Lower priority than FIQ 6 7 N Z C V Q I F T M 4 M 3 M 2 M 1 M 0 I bit : disable IRQ when it is set F bit: disable FIQ when it is set

56 IRQ R14_irq = address of next instruction ti to be executed + 4 SPSR_irq = CPSR CPSR[4:0] = 0b10010 /* enter IRQ mode */ CPSR[5] = 0 /* execute in ARM state */ /*CPSR[6] is unchanged */ CPSR[7] = 1 /* disable normal interrupt */ If high vectors configured then PC = 0xFFFF0018 else PC = 0x To return SUBS PC, R14, #4 /* PC from R14_irq, CPSR from SPSR_irq */

57 FIQ R14_fiq = address of next instruction to be executed + 4 SPSR_fiq = CPSR CPSR[4:0] = 0b10001 /* enter FIQ mode */ CPSR[5] = 0 /* execute in ARM state */ CPSR[6] = 1 /* disable fast interrupt */ CPSR[7] = 1 /* disable normal interrupt */ If high vectors configured then PC = 0xFFFF001C else PC = 0x C To return SUBS PC, R14, #4 /* PC from R14_fiq, CPSR from SPSR_fiq*/ * The FIQ handler can be placed directly at address 0x C or 0xFFFF001C, without requiring a branch instruction from the vector.

58 ARM interrupt latency Worst-case latency to respond to interrupt is 27 cycles: Two cycles to synchronize external request Up to 20 cycles to complete current instruction Three cycles for data abort Two cycles to enter interrupt handling state

59 Direct memory access Buffering Temporarily storing data in memory before processing Data accumulated in peripherals commonly buffered Microprocessor could handle this with ISR Storing and restoring microprocessor state inefficient Regular program must wait DMA controller more efficient Separate single-purpose processor Microprocessor relinquishes control of system bus to DMA controller Microprocessor can meanwhile execute its regular program No inefficient storing and restoring state due to ISR call Regular program need not wait unless it requires the system bus Harvard archictecture processor can fetch and execute instructions as long as they don t access data memory if they do, processor stalls

60 Peripheral to memory transfer with DMA Time 1(a): μp is executing its main program. It has already configured the DMA ctrl registers. 1(b): P1 receives input data in a register with address 0x : After executing instruction 100, μp sees Dreq asserted, releases the system bus, asserts Dack, and resumes execution. μp stalls only if it needs the system bus to continue executing. 3: DMA ctrl asserts Dreq to request control of system bus. 5: (a) DMA ctrl asserts ack (b) reads data from 0x8000 and (b) writes that data to 0x : P1 asserts req to request servicing by DMA ctrl. 7(a): μp de-asserts Dack and resumes control of the bus. 6:. DMA de-asserts Dreq and ack completing handshake with P1. 7(b): P1 de-asserts req.

61 Peripheral to memory transfer with DMA (cont ) 1(a): P is executing its main program. It has already configured the DMA ctrl registers Program memory μp 0x0000 Data memory 0x0001 1(b): P1 receives input data in a register with address 0x8000. No ISR needed! System bus... Dack Main program... Dreq 100: instruction PC 101: instruction 100 DMA ctrl 0x0001 ack 0x8000 req P1 0x8000

62 Peripheral to memory transfer with DMA (cont ) 2: P1 asserts req to request servicing by DMA ctrl. Program memory μp 0x0000 Data memory 0x0001 3: DMA ctrl asserts Dreq to request control of system bus No ISR needed! System bus... Dack Main program... Dreq 100: instruction PC 101: instruction DMA ctrl 0x0001 0x8000 ack req 1 P1 0x8000

63 Peripheral to memory transfer with DMA (cont ) 4: After executing instruction 100, P sees Dreq asserted, releases the system bus, asserts Dack, and resumes execution, P stalls only if it needs the system bus to continue executing. Program memory No ISR needed! μp 0x0000 Data memory 0x0001 System bus... Dack 1 Main program... Dreq 100: instruction PC 101: instruction 100 DMA ctrl 0x0001 ack 0x8000 req P1 0x8000

64 Peripheral to memory transfer with DMA (cont ) 5: DMA ctrl (a) asserts ack, (b) reads data from 0x8000, and (c) writes that data to 0x0001. (Meanwhile, processor still executing if not stalled!) Program memory No ISR needed! μp... Dack Main program... Dreq 100: instruction PC 101: instruction 100 Data memory 0x0000 0x0001 System bus DMA ctrl P1 1 0x0001 ack 0x8000 req 0x8000

65 Peripheral to memory transfer with DMA (cont ) 6: DMA de-asserts Dreq and ack completing the handshake with P1. Program memory μp 0x0000 Data memory 0x0001 No ISR needed! System bus... Dack Main program... Dreq 100: instruction PC 101: instruction DMA ctrl 0x0001 0x8000 ack req 0 P1 0x8000

66 ISA bus DMA cycles Processor Memory R A DMA ISA-Bus R A I/O Device DMA Memory-Write Bus Cycle DMA Memory-Read Bus Cycle CYCLE CLOCK C1 C2 C3 C4 C5 C6 C7 CYCLE CLOCK C1 C2 C3 C4 C5 C6 C7 D[7-0] DATA D[7-0] DATA A[19-0] ADDRESS A[19-0] ADDRESS ALE ALE /IOR /MEMR /MEMW /IOW CHRDY CHRDY

67 Intel 8237 DMA controller D[7..0] A[19..0] ALE MEMR MEMW IOR IOW HLDA HRQ Intel 8237 REQ 0 ACK 0 REQ 1 ACK 1 REQ 2 ACK 2 REQ 3 ACK 3 Signal D[7..0] A[19..0] ALE* MEMR* MEMW* Description These wires are connected to the system bus (ISA) and are used by the microprocessor to write to the internal registers of the These wires are connected to the system bus (ISA) and are used by the DMA to issue the memory location where the transferred data is to be written to. The 8237 is This is the address latch enable signal. The 8237 use this signal when driving the system bus (ISA). This is the memory write signal issued by the 8237 when driving the system bus (ISA). This is the memory read signal issued by the 8237 when driving the system bus (ISA). IOR* This is the I/O device read signal issued by the 8237 when driving the system bus (ISA) in order to read a byte from an I/O device IOW* This is the I/O device write signal issued by the 8237 when driving the system bus (ISA) in order to write a byte to an I/O device. HLDA This signal (hold acknowledge) is asserted by the microprocessor to signal that it has relinquished the system bus (ISA). HRQ This signal (hold request) is asserted by the 8237 to signal to the microprocessor a request to relinquish the system bus (ISA). REQ 0,1,2,3 An attached device to one of fthese channels asserts this signal lto request a DMA transfer. ACK 0,1,2,3 The 8237 asserts this signal to grant a DMA transfer to an attached device to one of these channels. *See the ISA bus description in this chapter for complete details.

68 Serial I/O interfacing

69 8251 CPU interface Parallel communication Serial communication CPU status (8 bit) data (8 bit) 8251 xmit/ rcv serial port

70 Example : 8251 UART Universal asynchronous receiver transmitter (UART) : provides serial communication 8251 functions are integrated into standard PC interface chip Allows many communication parameters to be programmed

71 Serial communication Characters are transmitted separately: no char start bit 0 bit 1... bit n-1 stop time

72 Serial communication parameters Baud (bit) rate Number of bits per character Parity/no parity Even/odd parity Length of stop bit (1, 1.5, 2 bits)

73 Networking for Embedded Systems

74 Networking for Embedded Systems Why we use networks? Network abstractions Example networks

75 Network elements distributed computing platform: PE PE network communication link PEs may be CPUs or ASICs PE

76 Networks in embedded systems PE more processing initial processing PE sensor PE actuator

77 Why distributed? Higher performance at lower cost Physically y distributed activities---time constraints may not allow transmission to central site Improved debugging---use use one CPU in network to debug others May buy subsystems that have embedded processors

78 Network abstractions International Standards Organization (ISO) developed the Open Systems Interconnection (OSI) model to describe networks: 7-layer model Provides a standard way to classify network components and operations

79 OSI model application presentation session transport network data link physical end-use interface data format application dialog control connections end-to-end service reliable data transport mechanical, electrical

80 OSI layers Physical: connectors, bit formats, etc Data link: error detection and control across a single link (single hop) Network: end-to-end multi-hop data communication Transport: provides connections; may optimize Transport: provides connections; may optimize network resources

81 OSI layers, cont d. Session: services for end-user applications: data grouping, checkpointing, etc Presentation: data formats, transformation services Application: interface between network and end- user programs

82 Error detection and correction Often part of protocol Error detection: ability of receiver to detect errors during transmission Error correction: ability of receiver and transmitter to cooperate to correct problem Typically done by acknowledgement/retransmission protocol Bit error: single bit is inverted Burst of bit error: consecutive bits received incorrectly Parity: extra bit sent with word used for error detection Odd parity: data word plus parity bit contains odd number of 1 s Even parity: data word plus parity bit contains even number of 1 s 1s Always detects single bit errors, but not all burst bit errors Checksum: extra word sent with data packet of multiple words e.g., g, extra word contains XOR sum of all data words in packet

83 Hardware architectures Many different types of networks: topology scheduling of communication routing Types of physical media Parallel Serial Wireless

84 Point-to-point to networks One source, one or more destinations, no data switching (parallel or serial port): PE 1 PE 2 PE 3 link 1 link 2

85 Bus networks Common physical connection: PE 1 PE 2 PE 3 PE 4 header address data ECC packet format

86 Bus arbitration Fixed: Same order of resolution every time Fair: every PE has same access over long periods round-robin: rotate top ppriority among PEs fixed A B C A B C round-robin A B C B C A ABC A,B,C A,B,C

87 Crossbar out4 out3 out2 out1 in1 in2 in3 in4

88 Crossbar characteristics Non-blocking Can handle arbitrary multi-cast combinations Size proportional to n 2 small n

89 Multi-stage networks Use several stages of switching elements Often blocking Often smaller than crossbar

90 Serial Protocols

91 Serial protocols: I 2 C bus Designed for low-cost, medium data rate applications Inter-Integrated Circuit (I 2 C) Bus Designed by Philips nearly 20 years ago Enables peripheral ICs to communicate using simple comm HW Characteristics: Two-wire serial bus multiple-master Data transfer rates up to 100 kbits/s and 7-bit addressing possible in normal mode 3.4 Mbits/s and 10-bit addressing in fast-mode fixed-priority arbitration Several microcontrollers come with built-in I 2 C controllers Common devices capable of interfacing to I 2 C bus: EPROMS, Flash, and some RAM memory, real-time clocks, watchdog timers, and microcontrollers

92 I 2 C physical layer SCL SDA serial clock line serial data line Microcontroller EEPROM Temp. LCD- (servant) Sensor controller (master) (servant) (servant) < 400 pf Addr=0x01 Addr=0x02 Addr=0x03 SDA SDA SDA SDA SCL SCL SCL SCL Start condition Sending 0 Sending 1 Stop condition From Servant From receiver D C S T A R T A 6 A 5 A 0 R / w A C K D 8 D 7 D 0 A C K S T O P Typical read/write cycle

93 I 2 C electrical interface Open collector/open drain interface: + SDL Assert data Data in + SCL Assert clock Clock in

94 I 2 C signaling Sender pulls down bus for 0 Sender listens to bus---if it tried to send a 1 and heard a 0, someone else is simultaneously transmitting Transmissions occur in 8-bit bytes

95 I 2 C data link layer Every device has an address (7 bits in standard, 10 bits in extension) Bit 8 of address signals read or write S 7 bits r/w General call address allows broadcast Address : general call

96 I 2 C data format SCL SDL... start MSB 8-bit byte The receiver sets the SDL to 0 if it properly receive the byte ack stop

97 I 2 C bus arbitration Sender listens while sending address When sender hears a conflict, it stops signaling g Low-priority senders relinquish control early enough in clock cycle to allow bit to be transmitted reliably

98 I 2 C transmissions multi-byte write S adrs 0 data data P read dfrom slave S adrs 1 data P stop write, then read from slave S adrs 0 data S adrs 1 data P from slave

99 Serial protocols: CAN CAN (Controller area network) Protocol for real-time applications Developed by Robert Bosch GmbH Oi Originally i for communication among components of cars Applications now using CAN include: elevator controllers, copiers, telescopes, production-line control systems, and medical instruments Data transfer rates up to 1 Mbit/s and 11-bit addressing Common devices interfacing with CAN: 8051-compatible 8592 processor and standalone CAN controllers Actual physical design of CAN bus not specified in protocol Requires devices to transmit/detect dominant and recessive signals to/from bus e.g., 1 = dominant, 0 = recessive if single data wire used Bus guarantees dominant signal prevails over recessive signal if asserted simultaneously

100 USB Universal Serial Bus Compaq, DEC, IBM, Intel, Microsoft, etc. Spec 1.0 published in Jan. 96 Spec 2.0 in 00 USB Mbps (full-speed), 1.5 Mbps (low-speed) USB Mbps

101 USB, cont d Tiered star topology Point-to-point connection between a host and a hub or function Host scheduled, tokenbased protocol Plug-and-Play

102 USB physical layer Differential current drive Tiered star topology

103 USB data flow type Control transfers Used to configure a device at attach time Bulk data transfers Generated and consumed in relatively large and bursty quantities Interrupt data transfers Used for timely but reliable delivery of data Isochronous transfers Occupy a prenegotiated amount of USB bandwidth with a prenegotiated delivery latency

104 USB protocol layer Byte/Bit ordering LSb first, LSB first in multiple byte fields SYNC field All packets begin with a SYNC field Packet identifier field (PID) Immediately follows the SYNC field

105 PID types

106 Address field + endpoint number Address field 128 addressed ADDR<6:0> 0 : reserved as the default address Endpoint field ENDP<3:0> Permit more flexible addressing of functions in which more than one endpoint is required

107 Other fields Frame number field Incremented by the host on a per-frame basis 0-7FF Sent only in SOF tokens at the start of each (miro)frame Data field Zero to 1,024 bytes CRCs Token CRCs Data CRCs

108 Packet formats Token packets Split transactions Start-split (SSPLIT) Complete-split (CSPLIT)

109 Packet formats, cont d Start t of frame 1ms for FS 125s forhs Data Packets

110 Packet formats, cont d Handshake packets Ack, Nack, etc. Only a PID

111 Serial protocols: FireWire FireWire (a.k.a. I-Link, Lynx, IEEE 1394) High-performance serial bus developed by Apple Computer Inc. Designed for interfacing independent electronic components e.g., Desktop, scanner Data transfer rates from 12.5 to 400 Mbits/s, 64-bit addressing Plug-and-play capabilities Packet-based layered design structure Applications using FireWire include: disk drives, printers, scanners, cameras

112 IEEE 1394 Capable of supporting a LAN similar il to Ethernett 64-bit address: 10 bits for network ids, 1023 subnetworks 6 bits for node ids, each subnetwork can have 63 nodes 48 bits for memory address, each node can have 281 terabytes of distinct locations 1394b draft 3.2 Gigabit meters distances

113 Wireless communication Infrared (IR) Electronic wave frequencies just below visible light spectrum Diode emits infrared light to generate signal Infrared transistor detects signal, conducts when exposed to infrared light Cheap to build Need line of sight, limited range Radio frequency (RF) Electromagnetic wave frequencies in radio spectrum Analog circuitry and antenna needed on both sides of transmission Line of sight not needed, transmitter power determines range

114 Wireless protocols: IrDA IrDA Protocol suite that supports short-range point-to-point infrared data transmission i Created and promoted by the Infrared Data Association (IrDA) Data transfer rate of 9.6 kbps and 4 Mbps IrDA hardware deployed in notebook computers, printers, PDAs, digital cameras, public phones, cell phones Lack of suitable drivers has slowed use by applications Windows 2000/98 now include support Becoming available on popular embedded OS s

115 Wireless protocols: Bluetooth Bluetooth New, global standard for wireless connectivity Based on low-cost, short-range radio link Connection established when within 10 meters of each other No line-of-sight required e.g., Connect to printer in another room

116 Wireless Protocols: IEEE IEEE Proposed standard for wireless LANs Specifies parameters for PHY and MAC layers of network PHY layer physical layer handles transmission i of data between nodes provisions for data transfer rates of 1 or 2 Mbps operates in 2.4 to GHz frequency band (RF) or 300 to 428,000 GHz (IR) MAC layer medium access control layer protocol responsible for maintaining order in shared medium collision avoidance/detection

117 Ethernet Dominant non-telephone LAN Versions: 10 Mb/s, 100 Mb/s, 1 Gb/s Goal: reliable communication over an unreliable medium

118 Ethernet topology Bus-based system, several possible physical layers: A B C

119 CSMA/CD Carrier sense multiple access with collision detection: sense collisions exponentially back off in time retransmit

120 Ethernet packet format preamble start frame source adrs dest adrs length data payload padding CRC

121 Ethernet performance Quality-of-service tends to non-linearly decrease at high load levels. Can t guarantee real-time deadlines. However, may yprovide very ygood service at proper p load levels.

122 Internet Protocol Internet Protocol (IP) is basis for Internet. Provides an internetworking standard: between two Ethernets, Ethernet and token ring, etc. Higher-level services are built on top of IP.

123 IP in communication application presentation session transport network data link physical node A IP network data link physical router application presentation session transport network data link physical node B

124 IP packet Includes: version, service type, length time to live, protocol source and destination address data payload Maximum data payload is 65,535 bytes.

125 IP addresses 32 bits in early IP, 128 bits in IPv (about 3.4 x10 38 ) unique addresses Surface area of the earth (land and sea) Approximately 5.1 x m 2 Volume of the biosphere (20 km thick) About 1.0 x m 3 Density of available address 3.4 x /cm 3 Enough to uniquely identify every grain of sand and drop of water in the world Typically written in form xxx.xx.xx.xx. Typically written in form xxx.xx.xx.xx. Names (foo.baz.com) translated to IP address by domain name server (DNS).

126 Internet routing Best effort routing: doesn t guarantee data delivery at IP layer. Routing can vary: session to session; packet to packet.

127 Higher-level Internet services Transmission Control Protocol (TCP) provides connection-oriented service Quality-of-service (QoS) guaranteed services are under development

128 The Internet service stack FTP HTTP SMTP telnet SNMP TCP IP UDP User Datagram Protocol