Computer architecture Assignment 3

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Peregrine Moore
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1 Computer architecture Assignment 3 1- An instruction at address 14E in the basic computer has I=0, an operation code of the AND instruction, and an address part equal to 109(all numbers are in hexadecimal). The memory word at address 109 contains the operand 1F86 and the content of AC is B214. Determine the contents of PC, AR, DR, AC, and IR at the end of the execute phase. 2- An instruction at address 109 in the basic computer has I=0, an operation code of the LDA instruction, and an address part equal to 560(all numbers are in hexadecimal). The memory word at address 560 contains the operand 176F and the content of AC is 1A42. Determine the contents of PC, AR, DR, AC, and IR at the end of the execute phase 3- An instruction at address 28C in the basic computer has I=0, an operation code of the ADD instruction, and an address part equal to 304(all numbers are in hexadecimal). The memory word at address 304 contains the operand 109F and the content of AC is 51F1. Determine the contents of PC, AR, DR, AC, and IR at the end of the execute phase. 4- The following program is stored in the memory unit of the basic computer. Show the contents of the AC, PC, and IR (in hexadecimal), at the end, after each instruction is executed. All numbers listed below are in hexadecimal. Location Instruction ADD BUN AND BUN C1A C6 5-The following program is a list of instructions in hexadecimal code. The computer executes the instructions starting from address 100. What are the content of AC and the memory word at address 103 when the computer halts? Location Instruction C103

2 6-a) Explain what the following program accomplishes when it is executed. What is the value of location CTR when the computer halts? AGN, WRD,HEX 62C1 b) List the address symbol table obtained during the first pass of the assembler c) List the hexadecimal code of the translated program. 7- A bus-organized CPU has 16 registers with 32 bits in each, an ALU, and a destination decoder. a. How many multiplexers are there in the A bus (or B bus), and what is the size of each multiplexers. b. How many selection inputs are needed for MUX A and MUX B? c. How many inputs and outputs are there in the decoder? d. How many inputs and outputs are there in the ALU for data, including input and output carries? e. Formulate a control word for the system assuming that ALU has 35 operations. 8- The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format with four fields: - an operation code field, - a mode field to specify one of seven addressing modes. - a register address field to specify one of 60 processor registers. - a memory address for the specified memory unit. Specify the instruction format and the number of bits in each field if the instruction is in one memory word. 9- An instruction is stored at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contain the number 200. Evaluate the effective address if the addressing mode of the instruction is : 1- Direct address mode 2- Immediate mode 3- Relative address mode. 4- Register indirect address mode

3 5- Index address mode with R1 as the index register. 10--a) Derive the control gates associated with the program counter PC in the basic computer. b) What happens during the first pass of the assembler if the line of code that has a pseudoinstruction ORG or also has a label? Modify the flowchart to include an error message if this occurs. 11- a) Derive the control gates associated with the Accumulator AC in the basic computer. b) A line of code in an assembly language program is as follows: HEX 35 Show that four memory words are required to store the line of code and give their binary content. Show that one memory word stores the binary translated code and give its binary content. 12- a) Derive the control gates associated with the Address register AR in the basic computer. b) Modify the flowchart of the second pass to include an error message when a symbolic address is not defined by a label. 13-a) Derive the control gates for the write input of the memory in the basic computer. b) Hexadecimal numbers do not take a negative sign. Modify the flowchart of the first pass to check for that error. 14-a) Show the complete logic of the interrupt flip-flop R in the basic computer. Use a JK flip-flop and minimize the number of gates. AGN,

4 15-a) Derive the control gates for the read input of the memory in the basic computer. b) Explain in words what the following program accomplishes when it is executed and obtain the Then list the translated program LDA SUB INC ADD MIN STA DIF MIN, DEC 83 SUB, DEC -23 DIF, HEX 0 16-a) Show the complete logic of the interrupt enable flip-flop IEN in the basic computer. Use a JK flip-flop and minimize the number of gates. Then list the translated program LDA X BSA OR HEX 3AF6 STA Y X, HEX 7B95 Y, HEX 0 OR, HEX 0 STA TMP LDA OR I AND TMP ISZ OR BUN OR I TMP, HEX 0 17-a) Derive the Boolean logic expression for x 2. Show that x 2 can be generated with one AND gate and one OR gate. b) What happens during the first pass of the assembler if the line of code that has a pseudoinstruction ORG or also has a label? Modify the flowchart to include an error message if this occurs. 18-a) Derive the Boolean logic expression for x 1. b) A line of code in an assembly language program is as follows:

5 HEX 35 Show that four memory words are required to store the line of code and give their binary content. Show that one memory word stores the binary translated code and give its binary content. 19-a) Derive the Boolean logic expression for x 3. b) Modify the flowchart of the second pass to include an error message when a symbolic address is not defined by a label. 20-a) Derive the Boolean logic expression for x 4. b) Hexadecimal numbers do not take a negative sign. Modify the flowchart of the first pass to check for that error. 21-a) Derive the Boolean logic expression for x 5. Then list the translated program LDA SUB INC ADD MIN STA DIF MIN,DEC 83 SUB,DEC -23 DIF, HEX 0 22-a) Derive the Boolean logic expression for x 6. AGN,

6 23-a) Derive the Boolean logic expression for x 7. AGN, 24-a) Derive the Boolean expression for the gate structure that clears the sequence counter SC to 0.Draw the logic diagram of the gates and show how the output is connected to the INR and CLR inputs of SC. Minimize the number of gates. AGN,

7 25-a) Show the complete logic of One stage of adder and logic circuit. Then list the translated program LDA SUB INC ADD MIN STA DIF MIN,DEC 83 SUB,DEC -23 DIF, HEX 0

Chapter 5. Computer Architecture Organization and Design. Computer System Architecture Database Lab, SANGJI University

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