2002 Mixed Signal Products SLAU056B

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1 User s Guide 22 Mixed Signal Products SLAU56B

2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box Dallas, Texas Copyright 22, Texas Instruments Incorporated

3 How to Use This Manual Preface Read This First About This Manual The MSP43x4xx user s guide is intended to assist in the development of MSP43x4xx family products by assembling together and presenting hardware and software information in a manner that is easy for engineers and programmers to use. This manual discusses modules and peripherals of the MSP43x4xx family of devices. Each discussion presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals may differ in their exact implementation between device families, or may not be fully implemented on an individual device or device family. Therefore, a user must always consult the data sheet of any device of interest to determine what peripherals and modules are implemented, and exactly how they are implemented on that particular device. How to Use This Manual This document contains the following chapters and appendixes: Chapter Introduction Chapter 2 Architectural Overview Chapter 3 System Resets, Interrupts, and Operating Modes Chapter 4 Memory Chapter 5 6-Bit CPU Chapter 6 Hardware Multiplier Chapter 7 FLL+ Clock Module Chapter 8 Digital I/O Configuration Chapter 9 Watchdog Timer iii

4 Related Documentation From Texas Instruments Chapter Basic Timer Chapter Timer_A Chapter 2 Timer_B Chapter 3 USART Peripheral Interface, UART Mode Chapter 4 USART Peripheral Interface, SPI Mode Chapter 5 Comparator_A Chapter 6 Liquid Crystal Display Drive Chapter 7 ADC2 Appendix A Peripheral File Map Appendix B Instruction Set Description Appendix C Flash Memory Notational Conventions This document uses the following conventions. Program listings, program examples, and interactive displays are shown in a special typeface similar to a typewriter s. Here is a sample program listing: 5.field, field 3, field 6, even Related Documentation From Texas Instruments For related documentation see the web site FCC Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 5 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. iv

5 Contents Contents Introduction Features and Capabilities x Devices x Devices x Devices Architectural Overview Introduction Central Processing Unit Program Memory Data Memory Operation Control Peripherals Oscillator and Clock Generator System Resets, Interrupts, and Operating Modes System Reset and Initialization Introduction Device Initialization After System Reset Global Interrupt Structure MSP43 Interrupt-Priority Scheme Operation of Global Interrupt Reset/NMI Operation of Global Interrupt Oscillator Fault Control Interrupt Processing Interrupt Control Bits in Special-Function Registers (SFRs) Interrupt Vector Addresses Operating Modes Low-Power Modes and (LPM and LPM) Low-Power Modes 2 and 3 (LPM2 and LPM3) Low-Power Mode 4 (LPM4) Basic Hints for Low-Power Applications Memory Introduction Data in the Memory Internal ROM Organization Processing of Memory Tables Computed Branches and Calls RAM and Peripheral Organization v

6 Contents 4.4. Random Access Memory Peripheral Modules Address Allocation Peripheral Modules Special Function Registers (SFRs) Bit CPU CPU Registers The Program Counter (PC) The System Stack Pointer (SP) The Status Register (SR) The Constant Generator Registers CG and CG Addressing Modes Register Mode Indexed Mode Symbolic Mode Absolute Mode Indirect Mode Indirect Autoincrement Mode Immediate Mode Clock Cycles, Length of Instruction Instruction Set Overview Double-Operand (Format I) Instructions Single-Operand (Format II) Instructions Conditional Jumps Short Form of Emulated Instructions Miscellaneous Instruction Map Hardware Multiplier Hardware Multiplier Module Support Hardware Multiplier Operation Multiply Unsigned, 6 6 bit, 6 8 bit, 8 6 bit, 8 8 bit Multiply Signed, 6 6 bit, 6 8 bit, 8 6 bit, 8 8 bit Multiply Unsigned and Accumulate, 6 6 bit, 6 8 bit, 8 6 bit, 8 8 bit Multiply Signed and Accumulate, 6 6 bit, 6 8 bit, 8 6 bit, 8 8 bit Hardware Multiplier Registers Hardware Multiplier Special Function Bits Hardware Multiplier Software Restrictions Hardware Multiplier Software Restrictions Address Mode Hardware Multiplier Software Restrictions Interrupt Routines Hardware Multiplier Software Restrictions MACS FLL+ Clock Module The FLL+ Clock Module LFXT Oscillator Digitally-Controlled Oscillator (DCO) and Frequency-Locked Loop FLL+Operation Modulator Operation DCO Frequency Range Disabling the FLL MCLK Stability Oscillator Fault Detection vi

7 Contents 7.5 FLL+ Operating Modes Starting From Power Up Clear (PUC) Adjusting the FLL+ Frequency FLL+ Features for Low-Power Applications Buffered Clock Output FLL+ Module Control Registers MCLK/SMCLK Frequency Control Special-Function Register Bits Digital I/O Configuration Introduction Ports P, P Port P, Port P2 Control Registers Port P, Port P2 Schematic Port P, P2 Interrupt Control Functions Ports P3, P4, P5, P Port P3 P6 Control Registers Port P3 P6 Schematic Watchdog Timer The Watchdog Timer Watchdog Timer Register Watchdog Timer Interrupt Control Functions Watchdog Timer Operation Basic Timer Basic Timer Basic Timer Registers Special Function Register Bits Basic Timer Operation Basic Timer Operation: Signal flcd Timer_A Introduction Timer_A Operation Timer Mode Control Clock Source Select and Divider Starting the Timer Timer Modes Timer Stop Mode Timer Up Mode Timer Continuous Mode Timer Up/Down Mode Capture/Compare Blocks Capture/Compare Block Capture Mode Capture/Compare Block Compare Mode Output Unit Output Modes Output Control Block Output Examples Timer_A Registers Timer_A Control Register TACTL Timer_A Register TAR vii

8 Contents.5.3 Capture/Compare Control Register CCTLx Timer_A Interrupt Vector Register Timer_A UART Timer_B Introduction Similarities and Differences From Timer_A Timer_B Operation Timer Length Timer Mode Control Clock Source Select and Divider Starting the Timer Timer Modes Timer Stop Mode Timer Up Mode Timer Continuous Mode Timer Up/Down Mode Capture/Compare Blocks Capture/Compare Block Capture Mode Capture/Compare Block Compare Mode The Output Unit Output Control Block Output Examples Timer_B Registers Timer_B Control Register TBCTL Timer_B Register TBR Capture/Compare Control Register TBCCTLx Timer_B Interrupt Vector Register USART Peripheral Interface, UART Mode USART Peripheral Interface USART Peripheral Interface, UART Mode UART Serial Asynchronous Communication Features Asynchronous Operation Asynchronous Frame Format Baud Rate Generation in Asynchronous Communication Format Asynchronous Communication Formats Idle-Line Multiprocessor Format Address-Bit Multiprocessor Format Interrupt and Enable Functions USART Receive Enable Bit USART Transmit Enable Bit USART Receive Interrupt Operation USART Transmit Interrupt Operation Control and Status Registers USART Control Register UCTL, UCTL Transmit Control Register UTCTL, UTCTL Receiver Control Register URCTL, URCTL Baud Rate Select and Modulation Control Registers Receive-Data Buffer URXBUF, URXBUF Transmit Data Buffer UTXBUF, UTXBUF viii

9 Contents 3.6 Utilizing Features of Low-Power Modes Receive-Start Operation From UART Frame Maximum Utilization of Clock Frequency vs Baud Rate UART Mode Support of Multiprocessor Modes for Reduced Use of MSP43 Resources Baud Rate Considerations Bit Timing in Transmit Operation Typical Baud Rates and Errors Synchronization Error USART Peripheral Interface, SPI Mode USART Peripheral Interface USART Peripheral Interface, SPI Mode SPI Mode Features Synchronous Operation Master SPI Mode Slave SPI Mode Interrupt and Control Functions USART Receive/Transmit Enable Bit, Receive Operation USART Receive/Transmit Enable Bit, Transmit Operation USART Receive-Interrupt Operation Transmit-Interrupt Operation Control and Status Registers USART Control Register Transmit Control Register UTCTL, UTCTL Receive Control Register URCTL, URCTL Baud Rate Select and Modulation Control Registers Receive Data Buffer URXBUF, URXBUF Transmit Data Buffer UTXBUF, UTXBUF Comparator_A Comparator_A Overview Comparator_A Description Input Analog Switches Input Multiplexer The Comparator The Output Filter The Voltage Reference Generator Comparator_A Interrupt Circuitry Comparator_A Control Registers Comparator_A, Control Register CACTL Comparator_A, Control Register CACTL Comparator_A, Port Disable Register CAPD Comparator_A in Applications Analog Signals at Digital Inputs Comparator_A Used to Measure Resistive Elements Measuring Two Independent Resistive Element Systems Comparator_A Used to Detect a Current or Voltage Level Comparator_A Used to Measure a Current or Voltage Level Measuring the Offset Voltage of Comparator_A Compensating for the Offset Voltage of Comparator_A ix

10 Contents Adding Hysteresis to Comparator_A Liquid Crystal Display Drive LCD Drive Basics LCD Controller/Driver LCD Controller/Driver Features LCD Timing Generation LCD Voltage Generation LCD Outputs LCD Control Register LCD Memory Code Examples Example Code for Static LCD Example Code for Two MUX, /2-Bias LCD Example Code for Three MUX, /3-Bias LCD Example Code for Four MUX, /3-Bias LCD ADC Introduction ADC2 Description and Operation ADC Core Reference Analog Inputs and Multiplexer Analog Multiplexer Input Signal Considerations Using the Temperature Diode Conversion Memory Conversion Modes Single-Channel, Single-Conversion Mode Sequence-of-Channels Mode Repeat-Single-Channel Mode Repeat-Sequence-of-Channels Mode Switching Between Conversion Modes Power Down Conversion Clock and Conversion Speed Sampling Sampling Operation Sample Signal Input Selection Sampling Modes Using the MSC Bit Sample Timing Considerations ADC2 Control Registers Control Registers ADC2CTL and ADC2CTL Conversion-Memory Registers ADC2MEMx Control Registers ADC2MCTLx ADC2 Interrupt Flags ADC2IFG.x and Interrupt-Enable Registers ADC2IEN.x ADC2 Interrupt Vector Register ADC2IV A/D Grounding and Noise Considerations Peripheral File Map A- A. Overview A-2 x

11 Contents A.2 Special Function Register of MSP43x4xx Family, Byte Access A-3 A.3 Digital I/O, Byte Access A-3 A.4 Basic Timer Registers, Byte Access A-5 A.5 FLL+ Registers, Byte Access A-5 A.6 SVS Register, Byte Access A-5 A.7 Comparator_A Registers, Byte Access A-5 A.8 USART, USART, UART Mode (Sync=), Byte Access A-6 A.9 USART, USART, SPI Mode (Sync=), Byte Access A-7 A. ADC2 Registers, Byte and Word Access A-8 A. LCD Registers, Byte Access A- A.2 Watchdog/Timer, Word Access A-2 A.3 Flash Control Registers, Word Access A-2 A.4 Hardware Multiplier, Word Access A-3 A.5 Timer_A Registers, Word Access A-4 A.6 Timer_B Registers, Word Access A-6 9 Instruction Set Description B- B. Instruction Set Overview B-2 B.. Instruction Formats B-4 B..2 Conditional and Unconditional Jumps (Core Instructions) B-5 B..3 Emulated Instructions B-6 B.2 Instruction Set Description B-8 2 Flash Memory C- C. Flash Memory Organization C-2 C.. Why Is a Flash Memory Module Divided Into Several Segments? C-5 C.2 Flash Memory Data Structure and Operation C-5 C.2. Flash Memory Basic Functions C-6 C.2.2 Flash Memory Block Diagram C-6 C.2.3 Flash Memory, Basic Operation C-6 C.2.4 Flash Memory Status During Code Execution C-8 C.2.5 Flash Memory Status During Erase C-8 C.2.6 Flash Memory Status During Write (Programming) C- C.3 Flash Memory Control Registers C-3 C.3. Flash Memory Control Register FCTL C-3 C.3.2 Flash Memory Control Register FCTL C-5 C.3.3 Flash Memory Control Register FCTL C-6 C.4 Flash Memory, Interrupt and Security Key Violation C-8 C.4. Example of an NMI Interrupt Handler C-2 C.4.2 Protecting One-Flash Memory-Module Systems From Corruption C-2 C.5 Flash Memory Access via JTAG and Software C-22 C.5. Flash Memory Protection C-22 C.5.2 Program Flash Memory Module via Serial Data Link Using JTAG Feature.. C-22 C.5.3 Programming a Flash Memory Module via Controller Software C-22 xi

12 Contents Figures 2 MSP43 System Configuration Bus Connection of Modules/Peripherals Brownout/Reset, SVS, Reset, and Power-Up Clear Schematic Block Diagram of Brownout and SVS Circuits Brownout Circuit Operating Levels Operating Levels for SVS and Brownout/Reset Circuit Interrupt Priority Scheme Block Diagram of NMI Interrupt Sources RST/NMI Mode Selection Interrupt Processing Return From Interrupt Status Register (SR) MSP43x3xx Family Operating Modes Typical Current Consumption vs Operating Modes Memory Map of Basic Address Space Memory Data Bus Bits, Bytes, and Words in a Byte-Organized Memory ROM Organization Byte and Word Operation Register-Byte/Byte-Register Operations Example of RAM/Peripheral Organization Program Counter System Stack Pointer Stack Usage PUSH SP and POP SP Status Register Bits Operand Fetch Operation Double Operand Instruction Format Single Operand Instruction Format Conditional-Jump Instruction Format Core Instruction Map Connection of the Hardware Multiplier Module to the Bus System Block Diagram of the MSP43 6y6-Bit Hardware Multiplier Registers of the Hardware Multiplier Frequency-Locked Loop Principle of LFXT Oscillator Digitally-Controlled Oscillator Fractional Tap Frequency Required Modulator Hop Patterns xii

13 Contents 7 6 Schematic of Clock Buffer SCFQCTL Register SCFI and SCFI Registers FLL+ Control Registers and Port P, Port P2 Configuration Schematic of One Bit in Port P, P Ports P3 P6 Configuration Schematic of Bits Pn.x Schematic of Watchdog Timer Watchdog Timer Control Register Reading WDTCTL Writing to WDTCTL Basic Timer Configuration Basic Timer Control Register Basic Timer Control Register Function Basic Timer Counter BTCNT Basic Timer Counter BTCNT Timer_A Block Diagram Mode Control Schematic of 6-Bit Timer Schematic of Clock Source Select and Input Divider Timer Up Mode Up Mode Flag Setting New Period > Old Period New Period < Old Period Timer Continuous Mode Continuous Mode Flag Setting Output Unit in Continuous Mode for Time Intervals Timer Up/Down Mode Output Unit in Up/Down Mode (II) Timer Up/Down Direction Control Up/Down Mode Flag Setting Altering CCR Timer in Up/Down Mode Capture/Compare Blocks Capture Logic Input Signal Capture Signal Capture Cycle Software Capture Example Output Unit Output Control Block Output Examples Timer in Up Mode Output Examples Timer in Continuous Mode Output Examples Timer in Up/Down Mode (I) Timer_A Control Register TACTL TAR Register Capture/Compare Control Register CCTLx Capture/Compare Interrupt Flag Schematic of Capture/Compare Interrupt Vector Word Vector Word Register UART Implementation xiii

14 Contents 34 Timer_A UART Timing Timer_B Block Diagram Mode Control Schematic of 6-Bit Timer Schematic of Clock Source Select and Input Divider Timer Up Mode Up Mode Flag Setting New Period > Old Period New Period < Old Period Timer Continuous Mode Continuous Mode Flag Setting Output Unit in Continuous Mode for Time Intervals Timer Up/Down Mode Output Unit in Up/Down Mode (II) Timer Up/Down Direction Control Up/Down Mode Flag Setting Altering TBCL Timer in Up/Down Mode Capture/Compare Blocks Capture Logic Input Signal Capture Signal Capture Cycle Software Capture Example Output Unit Output Control Block Output Examples Timer in Up Mode Output Examples Timer in Continuous Mode Output Examples Timer in Up/Down Mode (I) Timer_B Control Register TBCTL TBR Register Capture/Compare Control Register TBCCTLx Capture/Compare Interrupt Flag Schematic of Capture/Compare Interrupt Vector Word Vector Word Register Block Diagram of USART Block Diagram of USART UART Mode Asynchronous Frame Format Asynchronous Bit Format. Example for n or n + Clock Periods Typical Baud-Rate Generation Other Than MSP MSP43 Baud Rate Generation. Example for n or n + Clock Periods Idle-Line Multiprocessor Format USART Receiver Idle Detect Double-Buffered WUT and TX Shift Register USART Transmitter Idle Generation Address-Bit Multiprocessor Format State Diagram of Receiver Enable State Diagram of Transmitter Enable Receive Interrupt Operation Transmit Interrupt Operation USART Control Register UCTL, UCTL Transmitter Control Register UTCTL, UTCTL xiv

15 Contents 3 8 Receiver-Control Register URCTL, URCTL USART Baud Rate Select Register USART Modulation Control Register USART Receive Data Buffer URXBUF, URXBUF Transmit Data Buffer UTXBUF, UTXBUF Receive-Start Conditions Receive-Start Timing Using URXS Flag, Start Bit Accepted Receive Start Timing Using URXS Flag, Start Bit Not Accepted Receive Start Timing Using URXS Flag, Glitch Suppression MSP43 Transmit Bit Timing MSP43 Transmit Bit Timing Errors Synchronization Error Block Diagram of USART Block Diagram of USART SPI Mode MSP43 USART as Master, External Device With SPI as Slave Serial Synchronous Data Transfer Data Transfer Cycle MSP43 USART as Slave in Three-Pin or Four-Pin Configuration State Diagram of Receiver Enable Operation MSP43 as Master State Diagram of Receive/Transmit Enable MSP43 as Slave, Three-Pin Mode State Diagram of Receive Enable MSP43 as Slave, Four-Pin Mode State Diagram of Transmit Enable MSP43 as Master State Diagram of Transmit Enable MSP43 as Slave Receive Interrupt Operation Receive Interrupt State Diagram Transmit-Interrupt Operation USART Control Register Transmit Control Register UTCTL, UTCTL USART Clock Phase and Polarity Receive Control Register URCTL, URCTL USART Baud-Rate Select Register USART Modulation Control Register Receive Data Buffer URXBUF, URXBUF Transmit Data Buffer UTXBUF, UTXBUF Schematic of Comparator_A RC-Filter Response at the Output of the Comparator Comparator_A Interrupt System Transfer Characteristic and Power Dissipation in a CMOS Inverter/Buffer Transfer Characteristic and Power Dissipation in a CMOS Gate Application Example With One Active(Driving R3) and Three Passive Pins With Applied Analog Signals Temperature Measurement Systems Timing for Temperature Measurement Systems Two Independent Temperature Measurement Systems Temperature Measurement Via Temperature Sensor R(meas) Temperature Measurement Via Temperature Sensor R2(meas) Detect a Voltage Level Using an External Reference Level Detect a Current Level Using an Internal Reference Level Measuring a Current Source Timing for Measuring a Current Source A/D Converter for Voltage Sources xv

16 Contents 5 7 A/D Converter for Voltage Sources, Conversion Timing Measuring the Offset Voltage of the Comparator, CAEX = Offset Voltage of the Comparator, CAEX = Measuring the Offset Voltage of the Comparator, CAEX = Offset Voltage of the Comparator, CAEX = Use CAOUT at an External Pin to Add Hysteresis to the Reference Level Static Wave-Form Drive Two-MUX Wave-Form Drive Three-MUX Wave-Form Drive Four-MUX Wave-Form Drive LCD Controller/Driver Block Diagram External LCD Module Analog Voltage LCD Control and Mode Register Information Control Display Memory Bits Attached to Segment Lines in 4xx Family Example With the Static Drive Mode Example With the Two-MUX Mode Example With the 3-MUX Mode Example With the Four-MUX Mode ADC2 Schematic ADC Core, Input Multiplexer, and Sample-and-Hold Analog Multiplexer Channel Stopping Conversion With ENC Bit Single-Channel, Single-Conversion Mode Example Conversion-Memory Setup ENC Does Not Effect Active Sequence Sequence-of-Channels Mode Sequence-of-Channels Mode Flow Sequence-of-Channels Mode Example Repeat-Single-Channel Mode Repeat-Sequence-of-Channels Mode The Conversion Clock ADC2CLK The Sample-and-Hold Function Sample and Conversion, Basic Signal Timing Synchronized Sample and Conversion Signal With Enable Conversion Conversion Timing, Pulse-Sample Mode Pulse-Sample Mode Example Configuration Pulse-Sample Mode Example Timing Conversion Timing for Extended-Sample Mode Extended-Sample Mode Example Configuration Extended-Sample Mode Example Timing Use of MSC Bit With Nonrepeated Modes Use of MSC Bit With Repeated Modes Equivalent Circuit A/D Grounding and Noise Considerations B Double-Operand Instructions B-4 B 2 Single-Operand Instructions B-5 B 3 Conditional and Unconditional Jump Instructions B-5 B 4 Decrement Overlap B-26 B 5 Main Program Interrupt B-46 xvi

MSP430FG4618 Programming Reference Revision 3

MSP430FG4618/F2013 Experimenter Board MSP430FG4618 Programming Reference Revision 3 George Mason University 1. CPU Registers The CPU incorporates sixteen 20-bit registers. R0, R1, R2 and R3 have dedicated