MIDTERM EXAM March 28, 2018

Transcription

1 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL Comp 541 Digital Logic and Computer Design Spring 2018 MIDTERM EXAM March 28, 2018 Pledge: I have neither given nor received unauthorized aid on this exam, and I have followed the instructions below. (signed) Instructions: Please write your answers in this booklet. The exam is open-book and open-notes. Use of a calculator is allowed. You may use a laptop computer for basic calculator functions and for accessing materials on, or downloaded from, the class website (including Verilog references), but you may not consult other people or other resources on the Internet. Point values are in parentheses. Total is 50 points. To pace yourself, you may want to spend only a little more than one minute per point. Partial credit will be given where appropriate. The exam duration is 1 hour 15 min (1:25 pm to 2:40 pm). 1 of 8

2 1) (12 points) In class and lab, we discussed and implemented a ripple-carry adder, which is what is called an iterative design: a full adder component, which performs addition over one column, is tiled to form an adder that can operate on multi-bit operands. In this question, you are to design an iterative comparator, which takes two unsigned N-bit inputs A[N-1:0] and B[N-1:0], and indicates if A == B, or if A < B, or if A > B. Below is the block diagram for a full comparator (single-bit) component (i.e., for a single column) that we want to design, along with a diagram of the N-bit iterative comparator. Assume the numbers are unsigned (i.e., positive, with no sign bit). Similar to the adder, the computation proceeds from right to left. Our full comparator component, accordingly, receives inputs from the right, and passes outputs to the left. But, instead of a single-bit carry-in and carry-out, we now have three inputs eq in, lt in and gt in and three outputs eq out, lt out and gt out which represent equal, less than and greater than, respectively. Exactly one of these three inputs will be 1, others will be 0. Similarly for the outputs. The input eq in is 1 if and only if the comparison of all the bits to the right of component i yields a partial result of equal, i.e., A[i-1:0] == B[i-1:0]. Similarly, the input lt in or gt in is 1 if the comparison of substrings to the right indicates that A[i-1:0] is less than or greater than B[i- 1:0], respectively. Note that if a higher-order bit determines that A < B or A > B, then the contribution of the lower-order bits is effectively overridden. The final result of the entire comparison is the set of three outputs of the leftmost column. Please answer the questions that follow. 2 of 8

3 a) [6] Boolean Equations: Write the expressions for the three outputs of the full comparator single-bit component in terms of its inputs (A i, B i, eq in, lt in and gt in ). It will be much easier to develop these equations directly by thinking of the relationship between the inputs and the outputs than by using truth tables. eq!"# = lt!"# = gt!"# = b) [3] Which three values (each 0 or 1) must be fed into the rightmost component as its eq in, lt in and gt in? eq!" (rightmost) = lt!" (rightmost) = gt!" (rightmost) = c) [3] Suppose now that we want to modify the design to handle signed numbers in 2 scomplement notation. The numbers A and B are still N bits wide, but the leftmost bit now carries a negative connotation. The remaining bits still represent positive quantities. Thus, the leftmost column will have a slightly different component, but the remaining columns will use the component you designed above. Write the Boolean expressions for the three outputs of the leftmost component. eq!"# (leftmost) = lt!"# (leftmost) = gt!"# (leftmost) = 3 of 8

4 2) (5 points) The figure shows the top half of a CMOS gate. Draw its bottom half. What Boolean function does this represent? Y = 4 of 8

5 3) (6 points) Suppose a processor consumes 80W dynamic power and 20W static power. The engineering team manages to redesign it (using smaller transistors) so that it now has half the capacitive load and runs on half the supply voltage, but, as a result, the processor runs only half as fast (i.e., half the clock or switching frequency). Also, the redesigned processor has half the leakage current (I DD ). a) [2] Calculate the dynamic and static power consumption of the redesigned processor. b) [2] Calculate the ratio (dynamic power / static power) for the original processor, and also for the redesigned version. c) [2] Suppose a software task took 100 seconds on the original processor. Assume both the original and the redesigned processor execute one instruction per clock cycle. How long will the same software task take on the redesigned processor (assume all time is spent on computation)? How much total energy was consumed in running this task on the original vs. the redesigned processor? 4) (4 points) Refer to the picture of a D latch below (not an edge-triggered flipflop), along with the waveforms representing its clock and data inputs. Draw its output Q, which starts out at 0. Assume that propagation delays are negligible and there is no rejection time. 5 of 8

6 5) (5 points) The truth table below specifies a function Y on four inputs, A, B, C, and D. Fill the entries in the Karnaugh Map on the right, draw the ovals for an optimal implementation of Y. (Tip: Observe the orderings of the columns and rows in the K-map are Gray coded.) (Only draw the ovals needed in implementation) Using the K-map, express Y as an optimal sum-of-products Boolean formula. Y = 6 of 8

7 6) (6 points) Consider the circuit below with the following propagation delays: 10 ns for the combinational logic, and 5 ns for each of the flipflops. The contamination delays are: 3 ns for the combinational logic and 1 ns for each flipflop. Each flipflop has a setup time of 5 ns and a hold time of 2 ns. a) [2] If there is no clock skew, what is the maximum clock frequency at which the circuit can operate? (Please use units of Hz, MHz, etc. for answer.) b) [2] If there is a clock skew of 10 ns, what is the maximum clock frequency at which the circuit can operate? c) [2] How much skew can the circuit tolerate before it experiences a hold time violation? 7 of 8

8 7) (5 points) Draw the state diagram of a Moore finite-state machine (FSM) that receives an input X, and produces an output Y that is 1 if and only if it has just now seen the following pattern: One or more 1 s, followed by one or more 0 s, followed by one or more 1 s, followed by one or more 0 s, followed by one or more 1 s. If you are familiar with regular expressions, this sequence can be represented as Assume that the tail of one sequence overlaps with the start of another sequence. Only show the state diagram (i.e., circles and arrows), properly labeled with inputs and outputs. There is no need to show the state transition tables, K-maps, logic equations or circuits. Your FSM should be a Moore style machine. 8) (7 points) For the MIPS processor discussed in class (and partially designed in Lab 8), complete the control signals in the table below for the instructions shown. Instr werf wdsel wasel asel bsel sext wr alufn pcsel SRAV XORI JALR END 8 of 8