REVISIONS LTR DESCRIPTION DATE APPROVED. A Correct terminal connections in figure 2. - PHN Thomas M. Hess

Transcription

1 REVISIONS LTR DESCRIPTION DTE PPROVED Correct terminal connections in figure 2. - PHN Thomas M. Hess CURRENT DESIGN CTIVITY CGE CODE HS CHNGED NMES TO: DL LND ND MRITIME Prepared in accordance with SME Y14.24 Vendor item drawing REV PGE REV PGE REV STTUS OF PGES REV PGE PMIC N/ Original date of drawing YY MM DD PREPRED BY Phu H. Nguyen CHECKED BY Phu H. Nguyen PPROVED BY Charles F. Saffle CODE IDENT. NO TITLE MICROCIRCUIT, DIGITL, CMOS HEX VOLTGE LEVEL SHIFTER FOR TTL TO CMOS OR CMOS TO CMOS OPERTION, MONOLITHIC SILICON REV PGE 1 OF 8 MSC N/ 5962-V039-13

2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance CMOS hex voltage level shifter for TTL to CMOS or CMOS to CMOS operation microcircuit, with an operating temperature range of -55 C to +125 C. 1.2 Vendor Item Drawing dministrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: Device type(s) X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) Device type Generic Circuit function 01 CD4504B-EP CMOS hex voltage level shifter for TTL to CMOS or CMOS to CMOS operation Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 JEDEC MO-153 Plastic small outline package Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator B C D E Z Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other 1.3 bsolute maximum ratings. DC supply voltage range, Voltage referenced to VSS terminal (V DD) V to V Input voltage range, all inputs V to V CC V Maximum DC input current, any one input... ±10 m Maximum power dissipation per package, (PD): T = -55 C to +100 C mw T = +100 C to +125 C... 1/ Maximum device dissipation per output transistor, for T = full package temperature range (all package types) mw Operating temperature range, (T ) C to +125 C Maximum package thermal impedance (θ J) C/W 2/ Storage temperature range, (T STG) C to +150 C Maximum lead temperature (during soldering), at distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max C 1/ Derate linearly at 12 mw/ C to 200 nw. 2/ The package thermal impedance is calculated in accordance with JESD REV PGE 2

3 1.4. Recommended operating conditions. 3/ 4/ Supply voltage range, (for T = full package temperature range) (V DD) V to V 2. PPLICBLE DOCUMENTS JEDEC SOLID STTE TECHNOLOGY SSOCITION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at or from JEDEC Solid State Technology ssociation, 3103 North 10th Street, Suite 240 S, rlington, V ). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer s part number as shown in 6.3 herein and as follows:. Manufacturer s name, CGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer s part number and with items and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams Case outline(s). The case outline(s) shall be as shown in and figure Terminal connections. The terminal connections shall be as shown in figure Block diagram. The block diagram shall be as shown in figure 3. 3/ For maximum reliability, nominal operating conditions should be selected so that operation is always within the recommended range. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the user s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. REV PGE 3

4 TBLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Limits at indicated temperatures ( C) Unit Quiescent device current, I DD max and I CC in CMOS-CMOS mode Quiescent device current, I CC max TTL-CMOS mode Output low (sink) current, I OL min Output low (source) current, I OH min Output voltage: low level, V OL max Output voltage: high level, V OH min Input low voltage, V IL max 3/ Input high voltage, V IH min 3/ V O V IN V CC V CC Min Max 0, m 0, , µ 0, , m 0, , , m 0.5 0, , , , , , , V 0, , , , , TTL-CMOS TTL-CMOS CMOS-CMOS CMOS-CMOS CMOS-CMOS TTL-CMOS TTL-CMOS CMOS-CMOS CMOS-CMOS CMOS-CMOS Input current, I IN max 0, ±0.1 ±0.1 ±1 ±1 ±0.1 µ See footnote at end of the table. REV PGE 4

5 TBLE I. Electrical performance characteristics. 1/ Propagation delay: high to low Propagation delay: high to low Transition time Test Symbol Conditions 4/ From TTL to CMOS From CMOS to CMOS From CMOS to CMOS From TTL to CMOS From CMOS to CMOS From CMOS to CMOS V CC V DD Min Limits Max t PHL V DD > V CC ns V DD > V CC V CC > V DD t PLH V DD > V CC ns V DD > V CC V CC > V DD ll modes ns t THL, t TLH Input capacitance C IN ny input 7.5 pf 1. Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2. Over recommended operating free air temperature range (unless otherwise noted). 3. pplies to the six input signals. For mode control (P13), only the CMOS-CMOS ratings apply.. 4. T = 25 C, Input t r, t f = 20 ns, C L = 50 pf, R L = 200 Ω. Unit REV PGE 5

6 Case X Dimensions Symbol Min Max Symbol Min Max 1.20 e 0.65 BSC E b E c 0.15 NOM L D Notes: 1. ll linear dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion not to exceed Fall within JEDEC MO-153. FIGURE 1. Case outlines. REV PGE 6

7 Pin No. Signal name Pin No. Signal name 1 V CC 16 V DD 2 OUT 15 F OUT 3 IN 14 F IN 4 B OUT 13 SELECT 5 B IN 12 E OUT 6 C OUT 11 E IN 7 C IN 10 D OUT 8 V SS 9 D IN FIGURE 2. Terminal connections. FIGURE 3. Block diagram. REV PGE 7

8 4. VERIFICTION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPRTION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DL Land and Maritime maintains an online database of all current sources of supply at Vendor item drawing administrative control number 1/ Device manufacturer CGE code Vendor part number Top side marking -01XE CD4504BMPWREP 4504BEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CGE code Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box Dallas, TX Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX REV PGE 8