Low-Capacitance, 2/3/4/6-Channel, ±15kV ESD Protection Arrays for High-Speed Data Interfaces

Transcription

1 9-739; Rev 5; 6/ General Description The are low-capacitance ±5kV ESD-protection diode arrays designed to protect sensitive electronics attached to communication lines. Each channel consists of a pair of diodes that steer ESD current pulses to VCC or. The protect against ESD pulses up to ±5kV Human Body Model, ±8kV Contact Discharge, and ±5kV Air-Gap Discharge, as specified in IEC These devices have a 5pF capacitance per channel, making them ideal for use on high-speed data I/O interfaces. The MAX30E is a two-channel device intended for USB and USB.0 applications. The MAX303E is a triple-esd structure intended for USB On-the-Go (OTG) and video applications. The MAX304E is a quad-esd structure designed for Ethernet and FireWire applications, and the MAX306E is a six-channel device designed for cell phone connectors and SVGA video connections. All devices are available in tiny 4-bump (.05mm x.05mm), 6-bump (.05mm x.57mm), 9-bump (.5mm x.5mm), 6-pin (3mm x 3mm) TDFN, and -pin (4mm x 4mm) TQFN packages and are specified for -40 C to +85 C operation. USB USB.0 Ethernet FireWire PART Applications Video Cell Phones SVGA Video Connections Selector Guide ESD-PROTECTED I/O PORTS MAX30EEWS+T MAX30EETT-T MAX303EEWT+T 3 MAX303EETT-T 3 MAX304EEBT-T 4 MAX304EETT-T 4 MAX306EEBL-T 6 MAX306EETC 6 Pin Configurations appear at end of data sheet. Features High-Speed Data Line ESD Protection ±5kV Human Body Model ±8kV IEC , Contact Discharge ±5kV IEC , Air-Gap Discharge Tiny Package Available Low 5pF Input Capacitance Low na (max) Leakage Current Low na Supply Current +0.9V to +5.5V Supply Voltage Range -, 3-, 4-, or 6-Channel Devices Available Ordering Information PART PIN-PACKAGE TOP MARK MAX30EEWS+T 4 +AA MAX30EETT+T 6 TDFN-* +ADQ MAX303EEEWT+T 6 +BG MAX303EETT+T 6 TDFN-* +ADO MAX304EEWT+T 6 +AL MAX304EETT+T 6 TDFN-* +ADP MAX306EEWL+T 9 +AQ MAX306EETC+ TQFN-* +AACA * = Exposed pad. Note: All devices operate over -40 C to +85 C temperature range. +Denotes a lead(pb)-free/rohs-compliant package. 0.µF Typical Operating Circuit PROTECTED CIRCUIT I/0 I/0_ 0.µF MAX30E MAX304E MAX306E MAX308E FireWire is a registered trademark of Apple Computer, Inc. Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim's website at

2 ABSOLUTE MAXIMUM RATINGS to v to +7.0V I/O_ to v to ( + 0.3V) Continuous Power Dissipation (T A = +70 C) (derate.5mw/ C above +70 C)...90mW 3 (derate.3mw/ C above +70 C)...984mW 3 3 (derate 4.mW/ C above +70 C)...8mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note ) 4 Junction-to-Ambient Thermal Resistance (θ JA )...87 C/W 6 Junction-to-Ambient Thermal Resistance (θ JA )...84 C/W 9 Junction-to-Ambient Thermal Resistance (θ JA )...7 C/W ELECTRICAL CHARACTERISTICS 6-Pin TDFN (derate 4.4mW/ C above +70 C)...95mW -Pin TQFN (derate 6.9mW/ C above +70 C)...349mW Operating Temperature Range C to +85 C Storage Temperature Range C to +50 C Junction Temperature C Lead Temperature (soldering, 0s) C Soldering Temperature (reflow) C ( = +5V ±5%, T A = T MIN to T MAX, unless otherwise noted. Typical values are at = +5V and T A = +5 C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V Supply Current I CC 00 na Diode Forward Voltage V F I F = 0mA V Channel Clamp Voltage (Note 3) V C T A = +5 C, ±5kV Positive transients + 5 Human Body Model, I F = 0A Negative transients -5 T A = +5 C, ±8kV Positive transients + 60 Contact Discharge (IEC ), I F = 4A Negative transients -60 T A = +5 C, ±5kV Positive transients + 00 Air-Gap Discharge (IEC ), I F = 45A Negative transients -00 Channel Leakage Current T A = 0 C to +50 C (Note 4) - + na Channel Input Capacitance = 5V, bias of / 5 7 pf ESD PROTECTION 6 TDFN Junction-to-Ambient Thermal Resistance (θ JA )...4 C/W Junction-to-Case Thermal Resistance (θ JC )...9 C/W TQFN Junction-to-Ambient Thermal Resistance (θ JA )...4 C/W Junction-to-Case Thermal Resistance (θ JC )...6 C/W Note : Package thermal resistances were obtained using the method described in JEDEC specification JESD5-7, using a fourlayer board. For detailed information on package thermal considerations, refer to Human Body Model ±5 kv V IEC Contact Discharge IEC Air-Gap Discharge ±8 kv ±5 kv Note : Limits over temperature are guaranteed by design, not production tested. Note 3: Idealized clamp voltages (L = L = L3 = 0) (Figure ); see the Applications Information section for more information. Note 4: Guaranteed by design. Not production tested.

3 ( = +5V, T A = +5 C, unless otherwise noted.) CLAMP VOLTAGE (V) PIN/BUMP MAX30E MAX303E MAX304E MAX306E TDFN- A, B 3, 6 CLAMP VOLTAGE vs. DC CURRENT DC CURRENT (ma) A, A, B3 TDFN-,, 4 A, A, B, B3 TDFN-,, 4, 5 A, A3, B, B3, C, C3 Typical Operating Characteristics TQFN-,, 3, 7, 8, 9 NAME A 4 B 3 B 3 A 5 Ground I/O_ Pin/Bump Description FUNCTION ESD-Protected Channel B A3 6 A3 6 C Power-Supply Input. Bypass to with a 0.µF ceramic capacitor., 5 5 MAX30E toc0 LEAKAGE CURRENT (pa) 4, 6, 0, LEAKAGE CURRENT vs. TEMPERATURE LEAKAGE CURRENT PER CHANNEL TEMPERATURE ( C) MAX30E toc0 INPUT CAPACITANCE (pf) INPUT CAPACITANCE vs. INPUT VOLTAGE = 3.3V = 5.0V INPUT VOLTAGE (V) No Connection. Not internally connected. Exposed Pad. Connect to. Only for TDFN and TQFN packages. MAX30E toc03 3

4 Detailed Description The are diode arrays designed to protect sensitive electronics against damage resulting from ESD conditions or transient voltages. The low input capacitance makes these devices ideal for high-speed data lines. The MAX30E, MAX303E, MAX304E, and MAX306E protect two, three, four, and six channels, respectively. The are designed to work in conjunction with a device s intrinsic ESD protection. The MAX30E/MAX303E/MAX304E/ MAX306E limit the excursion of the ESD event to below ±5V peak voltage when subjected to the Human Body Model waveform. When subjected to the IEC waveform, the peak voltage is limited to ±60V when subjected to Contact Discharge and ±00V when subjected to Air-Gap Discharge. The device that is being protected by the MAX30E/MAX303E/ MAX304E/MAX306E must be able to withstand these peak voltages plus any additional voltage generated by the parasitic board. Applications Information Design Considerations Maximum protection against ESD damage results from proper board layout (see the Layout Recommendations section and Figure ). A good layout reduces the parasitic series inductance on the ground line, supply line, and protected signal lines. The ESD diodes clamp the voltage on the protected lines during an ESD event and shunt the current to or. In an ideal circuit, the clamping voltage, V C, is defined as the forward voltage drop, V F, of the protection diode plus any supply voltage present on the cathode. For positive ESD pulses: VC = VCC + VF For negative ESD pulses: VC = -V F In reality, the effect of the parasitic series inductance on the lines must also be considered (Figure ). For positive ESD pulses: V V V L x di ( ESD) C = CC + FD + L ( ) dt + For negative ESD pulses: V V L x di ( ESD) L x d ( C = FD + ( ) dt + I 3 ESD ) dt where I ESD is the ESD current pulse. PROTECTED LINE POSITIVE SUPPLY RAIL L L3 D I/O_ D GROUND RAIL Figure. Parasitic Series Inductance L PROTECTED LINE NEGATIVE ESD CURRENT PULSE PATH TO GROUND D D I/O_ L L V C ( ) x di ESD dt PROTECTED CIRCUIT L3 Figure. Layout Considerations 4

5 During an ESD event, the current pulse rises from zero to peak value in nanoseconds (Figure 3). For example, in a 5kV IEC-6000 Air-Gap Discharge ESD event, the pulse current rises to approximately 45A in ns (di/dt = 45 x 0 9 ). An inductance of only 0nH adds an additional 450V to the clamp voltage. An inductance of 0nH represents approximately 0.5in of board trace. Regardless of the device s specified diode clamp voltage, a poor layout with parasitic inductance significantly increases the effective clamp voltage at the protected signal line. A low-esr 0.µF capacitor must be used between and. This bypass capacitor absorbs the charge transferred by an +8kV IEC-6000 Contact Discharge ESD event. Ideally, the supply rail ( ) would absorb the charge caused by a positive ESD strike without changing its regulated value. In reality, all power supplies have an effective output impedance on their positive rails. If a power supply s effective output impedance is Ω, then by using V = I R, the clamping voltage of V C increases by the equation V C = I ESD x R OUT. An +8kV IEC ESD event generates a current spike of 4A, so the clamping voltage increases by V C = 4A Ω, or V C = 4V. Again, a poor layout without proper bypassing increases the clamping voltage. A ceramic chip capacitor mounted as close to the MAX30E/ MAX303E/MAX304E/MAX306E pin is the best choice for this application. A bypass capacitor should also be placed as close to the protected device as possible. ±5kV ESD Protection ESD protection can be tested in various ways; the are characterized for protection to the following limits: IPEAK I 00% 90% ±5kV using the Human Body Model ±8kV using the Contact Discharge method specified in IEC ±5kV using the IEC Air-Gap Discharge method ESD Test Conditions ESD performance depends on a number of conditions. Contact Maxim for a reliability report that documents test setup, methodology, and results. Human Body Model Figure 4 shows the Human Body Model, and Figure 5 shows the current waveform it generates when discharged into a low impedance. This model consists of a 00pF capacitor charged to the ESD voltage of interest, which is then discharged into the device through a.5kω resistor. HIGH- VOLTAGE DC SOURCE R C MΩ CHARGE-CURRENT- LIMIT RESISTOR Cs 00pF R D.5kΩ DISCHARGE RESISTANCE STORAGE CAPACITOR Figure 4. Human Body ESD Test Model AMPERES I P 00% 90% Ir DEVICE UNDER TEST PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) 36.8% 0% t R = 0.7ns to ns 30ns 60ns t 0% 0 0 t RL TIME t DL CURRENT WAVEFORM Figure 3. IEC ESD Generator Current Waveform Figure 5. Human Body Model Current Waveform 5

6 HIGH- VOLTAGE DC SOURCE R C 50Ω to 00Ω CHARGE-CURRENT- LIMIT RESISTOR Cs 50pF R D 330Ω DISCHARGE RESISTANCE STORAGE CAPACITOR Figure 6. IEC ESD Test Model DEVICE UNDER TEST IEC The IEC standard covers ESD testing and performance of finished equipment. The MAX30E/ MAX303E/MAX304E/MAX306E help users design equipment that meets Level 4 of IEC The main difference between tests done using the Human Body Model and IEC is higher peak current in IEC Because series resistance is lower in the IEC ESD test model (Figure 6) the ESD-withstand voltage measured to this standard is generally lower than that measured using the Human Body Model. Figure 3 shows the current waveform for the ±8kV IEC Level 4 ESD Contact Discharge test. The Air-Gap Discharge test involves approaching the device with a charged probe. The Contact Discharge method connects the probe to the device before the probe is energized. Layout Recommendations Proper circuit-board layout is critical to suppress ESDinduced line transients. The MAX30E/MAX303E/ MAX304E/MAX306E clamp to 00V; however, with improper layout, the voltage spike at the device is much higher. A lead inductance of 0nH with a 45A current spike at a dv/dt of ns results in an ADDITION- AL 450V spike on the protected line. It is essential that the layout of the PC board follows these guidelines: ) Minimize trace length between the connector or input terminal, I/O_, and the protected signal line. ) Use separate planes for power and ground to reduce parasitic inductance and to reduce the impedance to the power rails for shunted ESD current. 3) Ensure short ESD transient return paths to and. 4) Minimize conductive power and ground loops. 5) Do not place critical signals near the edge of the PC board. 6) Bypass to with a low-esr ceramic capacitor as close to as possible. 7) Bypass the supply of the protected device to with a low-esr ceramic capacitor as close to the supply pin as possible. 6

7 Table. Reliability Test Data Temperature Cycle TEST CONDITIONS DURATION FAILURES PER SAMPLE SIZE -35 C to +85 C, -40 C to +00 C 50 cycles, 900 cycles 0/0, 0/00 Operating Life T A = +70 C 40hr 0/0 Moisture Resistance -0 C to +60 C, 90% RH 40hr 0/0 Low-Temperature Storage -0 C 40hr 0/0 Low-Temperature Operational -0 C 4hr 0/0 Solderability 8hr steam age 0/5 ESD ±000V, Human Body Model 0/5 High-Temperature Operating Life T J = +50 C 68hr 0/45 I/O MAX30E I/O I/O PROCESS: BiCMOS MAX303E I/O I/O3 MAX304E I/O I/O I/O3 I/O4 Chip Information Functional Diagrams MAX306E I/O I/O I/O3 I/O4 I/O5 I/O6 7

8 I/0 TOP VIEW (BUMPS ON BOTTOM) I/O + 3 A MAX30E B MAX30E TDFN A B I/O I/0 = EXPOSED PADDLE. CONNECT TO. I/0 I/0 3 I/O3 A B I/O A MAX303E MAX303E A3 B3 I/O + + TDFN I/03 I/0 I/0 3 I/O3 A I/O A MAX304E I/O4 A3 B B B3 MAX304E TDFN I/O I/04 I/03 I/0 I/0 I/03 I/O3 I/O I/O Pin Configurations 3 + A B MAX306E B3 I/O TQFN A A3 I/O4 C C C3 I/O6 MAX306E Package Information For the latest package outline information and land patterns (footprints), go to Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 4 W4A Refer to Application Note 89 6 W6C Refer to Application Note 89 9 W9B Refer to Application Note 89 6 TDFN- T TQFN- T I/06 I/05 I/04 8

9 REVISION NUMBER REVISION DATE DESCRIPTION 3 /07 Added 30EEWS+T TDFN and TQFN packages, updated Package Information 4 /09 Corrected part numbers and pin packages in the Ordering Information table, Absolute Maximum Ratings, Selector Guide, Pin Description, and Pin Configurations. Revision History PAGES CHANGED,, 3, 4, 6, 8, 5 3, / Updated to show available packages as, not UCSP,, 3, 6, 8 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 0 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

10 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: MAX304EEWT+T MAX30EETT+T MAX303EETT+T MAX304EEBT+T MAX304EETT+T MAX306EETC+ MAX306EETC+T MAX303EEWT+T MAX30EETT-T MAX306EEWL+T