IMPLEMENTATION OF LOW POWER DATA ENCODING TECHNIQUES FOR NoC

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1 IMPLEMENTATION OF LOW POWER DATA ENCODING TECHNIQUES FOR NoC Swathi.Shivakumar 1 and Prasanna Kumar B. K 2 1,2 VLSI Design and Embedded Systems, Shridevi Institute of Engineering and Technology,Tumkur Abstract In this paper, a low-power data encoding scheme is proposed. In general, system-onchip (SoC) based system will have many disadvantages in power-dissipation as well as clock rate wise, such transfer of the data from one system to another system in on-chip. At the same time, a higher operated system does not support the lower operated bus network for data transfer. Unlike SoC, network on- chip (NoC) has so many advantages for data transfer. It has a special feature to transfer the data in on-chip named as transitional encoder. Its operation is based on transitions of input data. The proposed system yields lower dynamic power dissipation due to the reduction of switching activity and coupling switching activity when compared to existing system. Even-though many factors which are based on power dissipation, the dynamic power dissipation is only considerable for reasonable advantage. Besides, the proposed system will be extended up-to interlink PE communication (data transfer from one PE to other) with help of routers and PEs which are performed by various operations. Keywords Coupling switching activity, data encoding, interconnection on chip, low power, network-on-chip(noc), power analysis. I. INTRODUCTION As VLSI technologies continue to scale, wire densities increases to support ever-small transistor geometries and causes on-chip wires to present increasing latency and energy problem. In particular, the high latency of cross-chip communication can still limit total performance by increasing the delay between on-chip units. Such scalable bandwidth requirement can be satisfied by using on-chip packet-switched micro-network of interconnects, generally known as Network-on- Chip (NoC) architecture. The scalable and modular nature of NoC and their support for efficient on chip communication lead to the NoC-based system implementations. In order to meet typical SoCs or multicore processing and basic module of network interconnection like switching logic, routing algorithm and the packet definition should be light-weighted to result in easily implemental solutions. Another approach to exceed such a limitation of communication and overcome such an enormous wiring delay in future technology is to adopt network-like interconnections which is called Network-on- Chip (NoC) architecture. By applying network-like communication which inserts some routers in-between each communication object, the required wiring can be shortened. Therefore, the switch-based interconnection mechanism provides a lot of scalability and freedom from the limitation of complex wiring. Replacement of SoC buses by NoCs will follow the same path of data communications when the economics prove that the NoC either reduces SoC manufacturing cost, SoC time to market, SoC time to volume, and SoC design risk or increases SoC performance. According to the NoC approach has a clear advantage over traditional buses and most notably system throughput. The success of the NoC design depends on the research of the interfaces between processing elements of NoC and interconnection fabric. Bus interconnection composed of a large number of components in a network interface can cause slow interface time though the influence of sharing the bus. In addition their interconnection has a defect that power consumption is high on the score of connecting all objects in the communication. As a consequence, the performance of the NoC design relies greatly on the interconnection paradigm.though the network technology in computer network is already well developed, it is almost impossible to apply to a chip-level intercommunication environment without any modification or reduction. To be eligible for All rights Reserved 167

2 architecture, the basic functionality should be simple and light-weighted because the implemented component of NoC architecture should be small enough to be a basic component constructing a SoC. In order to be low powered one has to consider many parameters such as clock rate, operating voltages, power management. In this paper, we focus on techniques aimed at reducing the power dissipated by the network links. In fact, the power dissipated by the network links is as relevant as that dissipated by routers and network interfaces (NIs) and their contribution is expected to increase as technology scales. In particular, we present a set of data encoding schemes operating at flit level and on an endto-end basis, which allows us to minimize both the switching activity and the coupling switching activity on links of the routing paths traversed by the packets. The proposed encoding schemes, which are transparent with respect to the router implementation, are presented and discussed at both the algorithmic level and the architectural level, and assessed by means of simulation on synthetic and real traffic scenarios. The analysis takes into account several aspects and metrics of the design, including silicon area, power dissipation, and energy consumption. II. RELATED WORK The following papers were used for the study of this project. The below references give a detail and explains various techniques used for reducing the power in the links. These papers describe the schemes proposed in their paper and the power reducing in terms of the power and energy. The papers describe their efficiency in terms of performance and power functions. Paper [1]: In this paper the causes of power dissipation is discussed. The primary aim of the authors was to minimize the power dissipation at the network links. This paper gives concepts of data encoding system operating at end-to-end and flit level are discussed. Here the flits are encoded before they are transferred. With reference to the NoC fabrics the approached schemes were transparent and general. In this paper the proposed systems were sceptical with reference to the implicit NoC architecture that is the proposed scheme does not require modification neither in the links nor in the routers. The impact in decoder and encoder logic in the network interface was assessed by an extensive evaluation. Paper [2]: In this paper a set of data encryption strategy where introduced to diminish the energy and power consumption for intercommunication system in a Network-on-Chip (NoC). The on-chip interconnection depends on the certain part of the total power, energy budget which are preferable for shrinking of technology. New concepts and techniques were developed which focused on improvement of the on-chip intercommunication system not only in terms of power but in terms of performance also. There are mainly two types of activity that causes power dissipation in the communication system, first is coupling switching activity and switching activity. Here, they have presented an idea to minimize this power by encoding the data packets before they are transmitted into the network. Paper [3]: The overall system performance of a chip depends on the deep submicron technology interconnections in a System on chip design. A logic operation is performed with more input signals this is accomplished by number of interconnected logic gates in a digital circuit. An energy transition is generated whenever an input signal changes from high to low or vice versa, this change will be propagated through the gates. The power dissipation will be induced in the CMOS circuit due to the signal transition which causes to charge or discharge the capacitive load. In this paper they have described a novel Octo-coding method and they have shown that this is most effective and powerful method for enhancing the behavior of on-chip data buses. The results were analyzed and implemented Modelsim and Xilinx tools. Paper [4]: The authors proposed this paper for the diminution in power consumption that is seen in network links. In Network on Chips (NoC) dynamic power dissipation in the All rights Reserved 168

3 contributes major power consumption. In this paper they have focused on reducing power dissipation which occurs due to the 2 criteria, self-switching activity which occurs in the specific link and coupling activity which occurs mainly in the neighboring links. The proposed encoding methods were known as two stages encoding technique and it was approached to diminish power using up referable crosstalk and switching transition. III. METHODOLOGY In this section, present the proposed encoding scheme whose goal is to reduce power dissipation by minimizing the coupling transition activity on the links of the interconnection network. The different components of power dissipation of a link are of four types of coupling transitions. A Type I transition occurs when one of the lines switches when the other remains unchanged. In a Type II transition, one line switches from low to high, other makes transition from high to low.a Type III transition corresponds to the case where both lines switch simultaneously. Finally, in a Type IV transition both lines do not change. The effective switched capacitance varies from type to type and hence, the coupling transition activity is a weighted sum of different types of coupling transition contributions.here, we calculate the occurrence probability for different types of transitions. Consider that flit ( t 1) and flit (t ) refer to the previous flit which was transferred through the link and the flit is about to pass through the link, respectively. Note that the first bit is the value of the generic ith line of the link, whereas the second bit represents the value of its ( i + 1)th line. Three data encoding schemes designed for reducing the dynamic power dissipation of the network links along with a possible hardware implementation of the decoder is discussed. A.SCHEME I: In Scheme I, we focus on reducing Type I transitions while in Scheme II, both Types I and II transitions are taken into account for deciding between half and full invert, depending the amount of switching reduction. Finally, in Scheme III, we consider the fact that Type I transitions show different behaviours in the case of odd and even invert and make the inversion which leads to the higher power saving. TABLE I- EFFECT OF ODD INVERSION ON CHANGE OF TRANSITION TYPES Fig.1 Generic block diagram of Encoder Scheme In scheme I, we focus on reducing the numbers of Type I transitions (by converting them to Types III and IV transitions) and Type II transitions (by converting them to Type I transition). All rights Reserved 169

4 scheme compares the current data with the previous data one to decide whether odd inversion or no inversion of the current data can lead to the link power reduction. Table I reports, for each transition, the relationship between the coupling transition activities of the flit when transmitted and when its bits are odd inverted. Data are organized as follows. The first bit is the value of the generic i th line of the link, whereas the second bit represent the value of its ( i + 1)th line. For each partition, the first line represents the values at time t 1(t). As Table I shows, if the flit is odd inverted, Types II, III, and IV transitions convert to Type I transitions. In the case of Type I transitions, the inversion leads to one of Types II, III, or Type IV transitions. In particular, the transitions indicated as T 1, T 1,andT 1 in the table convert to Types II, III, and IV transitions, respectively. B.SCHEME II: In the proposed encoding scheme II, we make use of both odd and full inversion. The full inversion operation converts Type II transitions to Type IV transitions. The scheme compares the current data with the previous one to decide whether the odd, full, or no inversion of the current data can give rise to the link power reduction. Fig 2 Decoder architecture for scheme II The wth bit of the body flit is indicated by inv which shows if it was inverted (inv = 1) or left as it was (inv = 0). For the decoder, we only need to have the Ty block to determine which action has been taken place in the encoder. Based on the outputs of these blocks, the majority voter block checks the validity of the inequality given by. If the output is 0 ( 1 ) and the inv = 1, it means that half (full) inversion of the bits has been performed. Using this output and the logical gates, the inversion action is determined. If two inversion bits were used, the overhead of the decoder hardware could be substantially reduced. C.SCHEME III: In the proposed encoding Scheme III, we add even inversion to Scheme II. The reason is that odd inversion converts some of Type I (T 1) transitions to Type II transitions. As can be observed from Table II, if the flit is even inverted, the transitions indicated as T 1/ T 1 in the table are converted to Type IV/Type III transitions. Therefore, the even inversion may reduce the link power dissipation as well. The scheme compares the current data with the previous one to decide whether odd, even, full, or no inversion of the current data can give rise to the link power reduction. TABLE II- EFFECT OF EVEN INVERSION ON CHANGE OF TRANSITION All rights Reserved 170

5 delay in ns power in mw International Journal of Modern Trends in Engineering and Research (IJMTER) Fig 3. Encoder architecture Scheme III. IV. RESULTS The proposed data encoding schemes have been assessed by means of a cycle-accurate NoC simulator based on Noxim. The power estimation models of Noxim include NIs, routers, and links. Using the detailed simulations, when the flits traversed the NoC links, the corresponding self and coupling switching activities were calculated scheme I scheme II scheme I scheme II V. CONCLUSIONS In this paper, new technique of data encoding scheme have been implemented whose primary purpose is to decrease energy consumption and power dissipation of the links in the NoC. All rights Reserved 171

6 compared with the previous proposed schemes which are mentioned in the literature review, the proposed schemes focuses on reducing all four types of transitions made while transferring a data. In a DSM technology the main intension is on reducing link power which is contributed by coupling switching activity. The proposed design is sceptical with reference to the underneath NoC design, meaning that their application can be implemented in the present system without any significant changes either in the routers or in the interconnection. Upto 50% of power dissipation and 12% energy consumption is diminished significantly in the proposed design. The performance and area overhead is not at all degraded in the proposed designed. The proposed system is entirely developed, simulated and synthesized using Xilinx ISE simulator. The data encoding algorithm is implemented on Spartan 6 FPGA. REFERENCES [1] Nima Jafarzadeh, Maurizio Palesi, Member, IEEE, Ahmad Khademzadeh, and Ali Afzali-kusha, Senior Member, Data Encoding Techniques for Reducing Energy Consumption in NoC (Network-on-Chip), IEEE. March [2] S.R Mullainathan and Mr.S.Ramkumar Switching Reduction Through Data Encoding Techniques In NoC, September [3] N. Vithya Lakshmi and M. Rajaram, An Octo Coding Technique To Diminish Energy Transition In Low Power VLSI Circuits, November 2013 [4] Deepa N.Sarma, G. Lakshminarayanan and Suryakiran Chavali K.V.R., A Novel Encoding Scheme For Low Power In Network On Chip Links. [5] D. Anisha and R. Sarathbabu, Data Encoding Techniques for Lower Power Dissipation in Network on Chip. [6] N. Rajesh, SCDBI Encoding scheme for NoC Links,Oct 2013 [7] Naveena Pai G, M.B.Anand,Naveen.K.B Design and Synthesis of Bus Invert Encoding and Decoding technique Using Reversible logic,august 2013 [8] Gopaldas Sunil kumar, Patnam Department of Electronics and Communication RGMCET Nandyal, Kurnool, Efficient RC Low power bus encoding methods for crosstalk reduction, August [9] G. Kalyanchakarav,Nagarjuna.M,V.Ramakrishna, A Novel bus encoding scheme for reducing switching activity in vlsi interconnects June 2012 [10] A.sathish,M.Madhavilatha an Technique to diminish transition energy for data bus in DSM Technology,July 2011 [11] A.Sathish, M.Madhavi Lathand,K. Lalkishor Nandyal, Efficient Switching activity Reduction Technique for Onchip buses, July [12] P. P. Pande, H. Zhu, A. Ganguly, and C. Grecu, Energy reduction through crosstalk avoidance coding in NoC paradigm, in Proc.9th EUROMICRO Conf. Digit. Syst. Design Archit. Methods Tools, Sep. 2006, pp [13] K. W. Ki, B. Kwang Hyun, N. Shanbhag, C. L. Liu, and K. M. Sung, Coupling-driven signal encoding scheme for low-power interface design, in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, Nov. 2000, pp [14] L. Rung-Bin, Inter-wire coupling reduction analysis of bus-invert coding, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 7,pp , Aug [15] Z. Khan, T. Arslan, and A. T. Erdogan, Low power system on chip bus encoding scheme with crosstalk noise reduction capability, IEE Proc.Comput. Digit. Tech., vol. 153, no. 2, pp , Mar [16] Z. Yan, J. Lach, K. Skadron, and M. R. Stan, Odd/even bus invert with two-phase transfer for buses with coupling, in Proc. Int. Symp. Low Power Electron. Design, 2002, pp [17] C. P. Fan and C. H. Fang, Efficient RC low-power bus encoding methods for crosstalk reduction, Integr. VLSI J., vol. 44, no. 1, pp , Jan [18] S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, W. James, D. Finan, A. P. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. V. Hoskote, N. Y. Borkar, and S. Y. Borkar, An 80-tile Sub-100-W TeraFLOPS processor in 65-nm CMOS, IEEE J. Solid-State Circuits, vol. 43, no. 1, pp , Jan. All rights Reserved 172