EE680 Project Report Final 05/05/2010 Zhou Zhao USC ID:

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1 Group Formation Group member: Zhou Zhao, Raj Shah EE680 Project Report Final 05/05/2010 Zhou Zhao USC ID: Job Assignment My job is to design a intelligent FPGA intra router, which has following objective functions. 1. Global route one FPGA to detect track congestions. 2. Suggest global and detail placement modifications to make sure routability. 3. Detail route the FPGA to assign proper configurations for each via based on the result of global router. 4. Minimize routing length of critical paths such as clock signal and control signals. Algorithm and Heuristic Description Programming IDE: NetBeans 6.8 in Mac OS X Snow Leopard Programming Language: Java SE 6 with JUNG for graph visualization General approach for global and detail routing 1. Since both global and detail routing can me modeled as undirected sparse graph, a general approach is developed to maximize code re-usability. The approach includes two phases, which are initial routing to give a quick but unoptimized solution and optimization using simulated annealing (SA). At first, the program will do weight estimation based on netlist distribution. Then, the netlist is selected and routed in random order using weighted Lee algorithm for both two and multi-terminal nets. The characteristics of weighted Lee algorithm have the capabilities to avoid congestion or most frequently routed vertices on the graph. However, the situation of overlap still exist to route all nets. In the initial stage, the situations of overlap are permitted and the number of these congested areas are counted. 2. At the second stage of optimization process, the algorithm of simulated annealing is used. The common priority for both global and detail route is to minimize congestion. In the global routing, the congestion mean that the number of routed nets through one tack is higher than the track's maximum capacity. For the detail routing, only one net can go through one wire. In addition, the via at the cross-point of two wires is occupied, once the detail routing change from vertical to horizontal direction or vice versa. If the via is occupied, other net can not use the via. Therefore, the via violation is also considered in detail routing. The objective functions of global and detail routing are shown below,, in which Tov is the number of tracks which are congested. Tpl is the total path length of routed netlist and Tv is the number of used vias. Note than, there is an additional term Tf in the objective function of detail routing, which stands for the number of violated vias. The flowchart of intra routing is shown below,

2 In the global initial routing, the program will generate a first solution which permit congestion, then simulated annealing will minimize the number of congested tracks. If there is at least one congested track after optimization, the global router will feedback only the nets which are related to congested track to placement module. The process of global routing is quick in evaluating whether the placement can be routed and needs less memory resource without concerning FPGA details. However, there is possibility that the detail router will fail, though the global routing is successful. Therefore, the program will conduct detail routing based on the results of global routing. Between the processes of global and detail routing, the netlist will be assigned randomly along global routed paths. Note that, since there is no vias between adjacent switch-boxes. The assignment module will make sure net is at the same row or column between adjacent switch-boxes, but dog-legs are injected randomly. In the detail routing of each switch-boxes, the process is similar to the global routing, but the optimization process will minimize both wire and via congestions. Features of program 1. Regular expression is used for importing netlist. If the format of netlist is not consistent, the program can still import the netlist. 2. Recursive functions are constructed in back trace process of Lee algorithm and vertical constraint graph of leftedge algorithm. 3. Rip-up and re-route process employ weighted Lee algorithm to accelerate finding routing solution without congestion. The difference between initial weight estimation and re-route is that initial route is using rectangle to estimate congestion before netlist is routed. However, in the process of rip-up and re-route, the netlist has already been routed. Therefore, the weight is along each paths. Once one net is re-routed with different path, the distribution of weight is different, therefore other routing paths have probability to have different paths. Both process of simulated annealing and weighted Lee algorithm is to minimize congestion. Before showing the program output, the coordinates of vertices and edges used in graph model are described. For instance, a FPGA of 4*4 CLB array can be modeled by a simple graph shown below. For simplicity of explanation, the top-left and bottom-right vertices can be represented by Vx[0,0] and Vx[8,8], respectively. The x is the ID of vertices. The edge between vertices is represented by Ey[1,0] between V0[0,0] and V1[1,0]. Since some vertices are null, the annotation is only used for description, which is not consistent with practical data structure in programming. Otherwise, the memory resources are wasted.

3 The standard test case is shown below, with FPGA configuration file of LICOUNT=6, SICOUNT=4, LI_CLB_NUM_P1=5, LI_IO_PIN_NUM=3, LI_T1_TRACK_NUM=4, LI_T2_TRACK_NUM=3, LI_T3_TRACK_NUM=4, LI_T4_TRACK_NUM=3 INPUT_SIGNAL(G1) 26; INPUT_SIGNAL(G2) 34; INPUT_SIGNAL(G3) 42; INPUT_SIGNAL(G4) 18; INPUT_SIGNAL(G5) 40; OUTPUT_SIGNAL(G16) 24; OUTPUT_SIGNAL(G17) 23; G8 = NAND2(G1, G3) 1 1; G9 = NAND2(G3, G4) 1 2; G12 = NAND2(G2, G9) 2 2; G15 = NAND2(G9, G5) 2 3; G16 = NAND2(G8, G12) 3 1; G17 = NAND2(G12, G15) 4 3; The imported netlist will be processed into corresponding vertices in the graph model. For instance, net 1 has a input pin at 26 and is also a input signal of NAND gate at coordinates of 1,1. The corresponding vertices which need to be connected are V9(0,1) and V79(7,8) shown in bold below. {17=[V69(6,7), V71(8,7)], 16=[V47(2,5), V71(8,7)], 1=[V9(0,1), V79(7,8)], 2=[V73(1,8), V29(2,3)], 3=[V9(0,1), V45(0,5), V11(2,1)], 4=[V35(8,3), V11(2,1)], 5=[V31(4,3), V45(0,5)], 8=[V45(0,5), V11(2,1)], 9=[V31(4,3), V29(2,3), V13(4,1)], 12=[V31(4,3), V67(4,7), V45(0,5)], 15=[V67(4,7), V33(6,3)]} Th process of wave propagation and back track in Lee algorithm is shown below. For signal 8 which need to connect vertices V45(0,5) and V11(2,1) will greedily choose minimum weight from the target vertex back to source vertex. The vertices and edges along the path will be constructed on the return of each recursive call. The path of net 8 is V45(0,5), V36(0,4), V38(2,4), V29(2,3), V20(2,2), V11(2,1)], which is equivalent to [E153(0,9), E138(2,8), E123(4,7), E89(4,5), E55(4,3)]

4 The output of program during the process of Lee algorithm is shown below. Initial routing is starting... 2 node signal 17 is routed globally [V69(6,7), V60(6,6), V62(8,6), V71(8,7)] [E233(12,13), E218(14,12), E237(16,13)] 2 node signal 16 is routed globally [V47(2,5), V56(2,6), V58(4,6), V60(6,6), V62(8,6), V71(8,7)] [E191(4,11), E210(6,12), E214(10,12), E218(14,12), E237(16,13)] 2 node signal 1 is routed globally [V9(0,1), V18(0,2), V20(2,2), V22(4,2), V24(6,2), V26(8,2), V35(8,3), V44(8,4), V53(8,5), V62(8,6), V71(8,7), V80(8,8), V79(7,8)] [E51(0,3), E70(2,4), E74(6,4), E78(10,4), E82(14,4), E101(16,5), E135(16,7), E169(16,9), E203(16,11), E237(16,13), E271(16,15), E287(15,16)] 2 node signal 2 is routed globally [V73(1,8), V72(0,8), V63(0,7), V54(0,6), V45(0,5), V36(0,4), V38(2,4), V29(2,3)] [E273(1,16), E255(0,15), E221(0,13), E187(0,11), E153(0,9), E138(2,8), E123(4,7)] [V31(4,3), V40(4,4), V49(4,5), V58(4,6), V67(4,7), V38(2,4), V36(0,4), V45(0,5)] 2 node signal 15 is routed globally [V67(4,7), V58(4,6), V60(6,6), V51(6,5), V42(6,4), V33(6,3)] [E229(8,13), E214(10,12), E199(12,11), E165(12,9), E131(12,7)] After initial routing, the number of congested track = 1 In the end of global initial routing, the number of congested track is one, which is highlighted in ellipse. Its capacity is four according to T1 track, but there are five nets routed through it.

5 After optimization in global routing, random selected nets are rip-up and re-routed. The congestion is minimized with nets are assigned to each sides of switch-boxes for detail routing as shown below. N, S, E, W, stands for north, south, east, and west, respectively.

6 The results of global routing is shown below. {17=[V69(6,7), V78(6,8), V79(7,8), V80(8,8), V71(8,7)], 1=[V9(0,1), V18(0,2), V20(2,2), V22(4,2), V24(6,2), V33(6,3), V42(6,4), V51(6,5), V60(6,6), V69(6,7), V78(6,8), V79(7,8)], 16=[V71(8,7), V62(8,6), V60(6,6), V58(4,6), V56(2,6), V47(2,5)], 2=[V29(2,3), V38(2,4), V47(2,5), V56(2,6), V65(2,7), V74(2,8), V73(1,8)], 3=[V45(0,5), V36(0,4), V27(0,3), V18(0,2), V9(0,1), V20(2,2), V11(2,1)], 4=[V35(8,3), V26(8,2), V24(6,2), V22(4,2), V20(2,2), V11(2,1)], 5=[V31(4,3), V40(4,4), V38(2,4), V36(0,4), V45(0,5)], 8=[V45(0,5), V36(0,4), V27(0,3), V18(0,2), V20(2,2), V11(2,1)], 9=[V31(4,3), V22(4,2), V13(4,1), V40(4,4), V38(2,4), V29(2,3)], 12=[V31(4,3), V40(4,4), V49(4,5), V58(4,6), V67(4,7), V56(2,6), V54(0,6), V45(0,5)], 15=[V33(6,3), V42(6,4), V51(6,5), V60(6,6), V58(4,6), V67(4,7)]} The detail routing is split into two situations. Regularly, if switch-box has assigned signal on any sides, it will be routed in detail. If there is no net assigned to east and west sides of switch-box, I define this switch-box as channel. The situation of normal switch-box is shown below. The nets are North = 1, 0, 2, 0; South = 0, 3, 1, 0; East = 0, 2, 0, 0; West = 0, 0, 3, 0; {1=[Via0(0,0), Via14(2,3)], 2=[Via2(2,0), Via7(3,1)], 3=[Via8(0,2), Via13(1,3)]} The detail routing result in this switch-box is {1=[Via0(0,0), Via1(1,0), Via5(1,1), Via6(2,1), Via10(2,2), Via14(2,3)], 2=[Via2(2,0), Via3(3,0), Via7(3,1)], 3=[Via8(0,2), Via9(1,2), Via13(1,3)]} The example of channel routing is shown above with nets North=0, 1, 0, 4, 1, 0, 5, 3; South = 2, 4, 0, 2, 0, 3, 0, 5; The constructed interval is {1=[1, 4], 2=[0, 3], 3=[5, 7], 4=[1, 3], 5=[6, 7]} with nets = {1=[Via1(1,0), Via4(4,0)], 2=[Via32(0,4), Via35(3,4)], 3=[Via37(5,4), Via7(7,0)], 4=[Via33(1,4), Via3(3,0)], 5=[Via6(6,0), Via39(7,4)]} The result is {1=[Via1(1,0), Via9(1,1), Via10(2,1), Via11(3,1), Via12(4,1), Via4(4,0)], 2=[Via32(0,4), Via24(0,3), Via25(1,3), Via26(2,3), Via27(3,3), Via35(3,4)], 3=[Via37(5,4), Via29(5,3), Via21(5,2), Via13(5,1), Via14(6,1), Via15(7,1), Via7(7,0)], 4=[Via33(1,4), Via25(1,3), Via17(1,2), Via18(2,2), Via19(3,2), Via11(3,1), Via3(3,0)], 5=[Via6(6,0), Via14(6,1), Via22(6,2), Via23(7,2), Via31(7,3), Via39(7,4)]}