Chapter 6 Detailed Routing
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1 hapter 6 Detailed Routing 6.1 Terminology 6.2 Horizontal and Vertical onstraint Graphs Horizontal onstraint Graphs Vertical onstraint Graphs 6.3 hannel Routing lgorithms Left-Edge lgorithm Dogleg Routing 6.4 Switchbox Routing Terminology Switchbox Routing lgorithms 6.5 Over-the-ell Routing lgorithms OT Routing Methodology OT Routing lgorithms 6.6 Modern hallenges in Detailed Routing VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 1
2 6 Detailed Routing System Specification ENTITY test is port a: in bit; end ENTITY test; rchitectural Design Functional Design and Logic Design Partitioning hip Planning ircuit Design Placement Physical Design lock Tree Synthesis DR LVS ER Physical Verification and Signoff Fabrication Packaging and Testing Signal Routing Timing losure hip VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 2
3 6 Detailed Routing Routing Multi-Stage Routing of Signal Nets Global Routing Detailed Routing Timing-Driven Routing Large Single- Net Routing Geometric Techniques oarse-grain assignment of routes to routing regions (hap. 5) Fine-grain assignment of routes to routing tracks (hap. 6) Net topology optimization and resource allocation to critical nets (hap. 8) Power (VDD) and Ground (GND) routing (hap. 3) Non-Manhattan and clock routing (hap. 7) VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 3
4 6 Detailed Routing The objective of detailed routing is to assign route segments of signal nets to specific routing tracks, vias, and metal layers in a manner consistent with given global routes of those nets Detailed routing techniques are applied within routing regions, such as channels (Sec. 6.3), switchboxes (Sec. 6.4), and global routing cells (gcells, Sec. 6.5) Detailed routers must account for manufacturing rules and the impact of manufacturing faults (Sec. 6.6) VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 4
5 6 Detailed Routing Global Routing Detailed Routing N 3 N 1 N 2 N 3 N 1 N 2 N 3 N 3 N 3 N1 N 3 N1 N 1 N2 N 1 N2 Horizontal Segment Vertical Segment Via VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 5
6 6.1 Terminology hannel and Switchbox Routing D D E E Horizontal hannel Tracks E D Vertical hannel Tracks VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 6
7 6.1 Terminology hannel Routing External Pad Power Rail Standard ell Row hannel VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 7
8 6.1 Terminology Two-Layer hannel Routing Three-Layer OT Routing OT: Over the cell D ell rea D ell rea Metal1 Metal2 Metal3 Via 2011 Springer Verlag VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 8
9 6.1 Terminology olumns a b c d e f g 0 D Vertical Segment (ranch) Horizontal Segment (Trunk) hannel Height Tracks 0 Pin Locations 2011 Springer Verlag VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 9
10 6.1 Terminology Horizontal onstraint ssumption: one layer for horizontal routing horizontal constraint exists between two nets if their horizontal segments overlap Horizontally constrained Horizontally unconstrained 2011 Springer Verlag VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 10
11 6.1 Terminology Vertical onstraint vertical constraint exists between two nets if they have pins in the same column The vertical segment coming from the top must stop before overlapping with the vertical segment coming from the bottom in the same column Vertically constrained without conflict Vertically constrained with a vertical conflict 2011 Springer Verlag VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 11
12 6.2 Horizontal and Vertical onstraint Graphs 6.1 Terminology 6.2 Horizontal and Vertical onstraint Graphs Horizontal onstraint Graphs Vertical onstraint Graphs 6.3 hannel Routing lgorithms Left-Edge lgorithm Dogleg Routing 6.4 Switchbox Routing Terminology Switchbox Routing lgorithms 6.5 Over-the-ell Routing lgorithms OT Routing Methodology OT Routing lgorithms 6.6 Modern hallenges in Detailed Routing VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 12
13 6.2 Horizontal and Vertical onstraint Graphs The relative positions of nets in a channel routing instance can be modeled by horizontal and vertical constraint graphs These graphs are used to initially predict the minimum number of tracks that are required detect potential routing conflicts VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 13
14 6.3.1 Horizontal onstraint Graphs olumn a b c d e f g h i j k 0 D E F G 0 D 0 0 E E F H 0 H G S(b) = {,, } S(col) contains all nets that either (1) are connected to a pin in column col or (2) have pin connections to both the left and right of col Since horizontal segments cannot overlap, each net in S(col) must be assigned to a different track in column col S(col) represents the lower bound on the number of tracks in colum col; lower bound of the channel height is given by maximum cardinality of any S(col) VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 14
15 6.3.1 Horizontal onstraint Graphs olumn a b c d e f g h i j k 0 D E F G 0 D 0 0 E E F H 0 H G 0 D E F G 0 D 0 0 E D F G H E E F H 0 H G VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 15
16 6.3.1 Horizontal onstraint Graphs olumn a b c d e f g h i j k 0 D E F G 0 D 0 0 E E F H 0 H G S(a) S(b) S(c) S(d)S(e) S(f)S(g) S(h) S(i) S(j) S(k) 0 D E F G 0 D 0 0 E D F G H E E F H 0 H G VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 16
17 6.3.1 Horizontal onstraint Graphs olumn a b c d e f g h i j k 0 D E F G 0 D 0 0 E E F H 0 H G S(c) S(f)S(g) S(i) 0 D E F G 0 D 0 0 E D F G H S(c) S(f) S(g) S(i) G F H D E E E F H 0 H G VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 17
18 6.3.1 Horizontal onstraint Graphs olumn a b c d e f g h i j k 0 D E F G 0 D 0 0 E E F H 0 H G Lower bound on the number of tracks = 5 S(c) S(f) S(g) S(i) G F H D E VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 18
19 6.3.1 Horizontal onstraint Graphs olumn a b c d e f g h i j k 0 D E F G 0 D 0 0 E E F H 0 H G Graphical Representation G F D S(c) S(f) S(g) S(i) G F H D E H E VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 19
20 6.3.2 Vertical onstraint Graphs directed edge e(i,j) E connects nodes i and j if the horizontal segment of net i must be located above net j VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 20
21 6.3.2 Vertical onstraint Graphs 0 D E F G 0 D 0 0 E E F H 0 H G D G Vertical onstraint Graph (VG) E F Note: an edge that can be derived by transitivity is not included, such as edge (,) H VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 21
22 6.3.2 Vertical onstraint Graphs 0 Net splitting yclic conflict VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 22
23 6.3 hannel Routing lgorithms 6.1 Terminology 6.2 Horizontal and Vertical onstraint Graphs Horizontal onstraint Graphs Vertical onstraint Graphs 6.3 hannel Routing lgorithms Left-Edge lgorithm Dogleg Routing 6.4 Switchbox Routing Terminology Switchbox Routing lgorithms 6.5 Over-the-ell Routing lgorithms OT Routing Methodology OT Routing lgorithms 6.6 Modern hallenges in Detailed Routing VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 23
24 6.3.1 Left-Edge lgorithm ased on the VG and the zone representation, greedily maximizes the usage of each track VG: assignment order of nets to tracks Zone representation: determines which nets may share the same track Each net uses only one horizontal segment (trunk) VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 24
25 6.3.1 Left-Edge lgorithm Input: channel routing instance R Output: track assignments for each net curr_track = 1 nets_unassigned = Netlist while (nets_unassigned!= Ø) VG = VG(R) ZR = ZONE_REP(R) SORT(nets_unassigned,start column) // start with topmost track // while nets still unassigned // generate VG and zone // representation // find left-to-right ordering // of all unassigned nets for (i =1 to nets_unassigned ) curr_net = nets_unassigned[i] if (PRENTS(curr_net) == Ø && // if curr_net has no parent (TRY_SSIGN(curr_net,curr_track)) // and does not cause // conflicts on curr_track, SSIGN(curr_net,curr_track) // assign curr-_net REMOVE(nets_unassigned,curr_net) curr_track = curr_track + 1 // consider next track 2011 Springer Verlag VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 25
26 6.3.1 Left-Edge lgorithm Example 0 D E F G 0 D I J J E E F H I H G I VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 26
27 6.3.1 Left-Edge lgorithm Example 0 D E F G 0 D I J J E E F H I H G I 1. Generate VG and zone representation D J G E I G H I H F D J E F VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 27
28 6.3.1 Left-Edge lgorithm Example D J G E I G H I H F D J E F 2. onsider next track 3. Find left-to-right ordering of all unassigned nets If curr_net has no parents and does not cause conflicts on curr_track assign curr_net curr_track = 1: Net Net J 4. Delete placed nets (, J ) in VG and zone represenation VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 28
29 6.3.1 Left-Edge lgorithm Example D G E I G H I H F D E F 2. onsider next track 3. Find left-to-right ordering of all unassigned nets If curr_net has no parents and does not cause conflicts on curr_track assign curr_net curr_track = 2: Net D 4. Delete placed nets (D ) in VG and zone representation VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 29
30 6.3.1 Left-Edge lgorithm Example G E I G H I H F E F 2. onsider next track 3. Find left-to-right ordering of all unassigned nets If curr_net has no parents and does not cause conflicts on curr_track assign curr_net curr_track = 3: Net E Net G 4. Delete placed nets (E, G ) in VG and zone representation VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 30
31 6.3.1 Left-Edge lgorithm Example I H I H F F 2. onsider next track 3. Find left-to-right ordering of all unassigned nets If curr_net has no parents and does not cause conflicts on curr_track assign curr_net curr_track = 4: Net Net F Net I 4. Delete placed nets (, F, I ) in VG and zone representation VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 31
32 6.3.1 Left-Edge lgorithm Example H H 2. onsider next track 3. Find left-to-right ordering of all unassigned nets If curr_net has no parents and does not cause conflicts on curr_track assign curr_net curr_track = 5: Net Net H 4. Delete placed nets (, H ) in VG and zone representation VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 32
33 6.3.1 Left-Edge lgorithm Example 0 D E F G 0 D I J J curr_track = E E F H I H G I Routing result 2011 Springer Verlag VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 33
34 6.3.2 Dogleg Routing Improving left-edge algorithm by net splitting Two advantages: lleviates conflicts in VG Number of tracks can often be reduced Net splitting 0 Dogleg VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 34
35 6.3.2 Dogleg Routing onflict alleviation using a dogleg Springer Verlag VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 35
36 6.3.2 Dogleg Routing Track reduction using a dogleg VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 36
37 6.3.2 Dogleg Routing Splitting p-pin nets (p > 2) into p 1 horizontal segments Net splitting occurs only in columns that contain a pin of the given net fter net splitting, the algorithm follows the left-edge algorithm Net splitting 0 0 VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 37
38 6.3.2 Dogleg Routing hannel routing problem VG without net splitting 0 0 hannel routing solution Net splitting 1 VG with net splitting 0 0 hannel routing solution 2011 Springer Verlag VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 38
39 6.4 Switchbox Routing 6.1 Terminology 6.2 Horizontal and Vertical onstraint Graphs Horizontal onstraint Graphs Vertical onstraint Graphs 6.3 hannel Routing lgorithms Left-Edge lgorithm Dogleg Routing 6.4 Switchbox Routing Terminology Switchbox Routing lgorithms 6.5 Over-the-ell Routing lgorithms OT Routing Methodology OT Routing lgorithms 6.6 Modern hallenges in Detailed Routing VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 39
40 6.4 Switchbox Routing E E D E D Fixed dimensions and pin connections on all four sides Defined by four vectors TOP, OT, LEFT, RIGHT Switchbox routing algorithms are usually derived from (greedy) channel routing algorithms VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 40
![6.4 Switchbox Routing R = {0, 1, 2,, 8} x {0, 1, 2,, 7} TOP = (1, 2,, 7) = [0, D, F, H, E,, ] OT = (1, 2,, 7) = [0, 0, G, H,,, H] LEFT = (1, 2,, 6) = [, 0, D, F, G, 0] RIGHT = (1, 2,, 6) = [, H,,, E,](/docs-images/79/79831798/images/41-0.jpg "] olumn a 0 b c d e f g D F H E 0 D F H E Track 6 5 4 3 2 1 0 G F D 0 E H?")
41 6.4 Switchbox Routing R = {0, 1, 2,, 8} x {0, 1, 2,, 7} TOP = (1, 2,, 7) = [0, D, F, H, E,, ] OT = (1, 2,, 7) = [0, 0, G, H,,, H] LEFT = (1, 2,, 6) = [, 0, D, F, G, 0] RIGHT = (1, 2,, 6) = [, H,,, E, ] olumn a 0 b c d e f g D F H E 0 D F H E Track G F D 0 E H? 0 G F D 0 E H 0 0 G H H 0 0 G H H VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 41
42 6.4 Switchbox Routing Example TOP = (1, 2,, 7) = [0, D, F, H, E,, ] OT = (1, 2,, 7) = [0, 0, G, H,,, H] LEFT = (1, 2,, 6) = [, 0, D, F, G, 0] RIGHT = (1, 2,, 6) = [, H,,, E, ] a 0 olumn b c d e f g D F H E Track G F D 0 E H 0 0 G H H VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 42
43 6.4 Switchbox Routing Example TOP = (1, 2,, 7) = [0, D, F, H, E,, ] OT = (1, 2,, 7) = [0, 0, G, H,,, H] LEFT = (1, 2,, 6) = [, 0, D, F, G, 0] RIGHT = (1, 2,, 6) = [, H,,, E, ] olumn a 0 b c d e f g D F H E 0 D F H E Track G F D 0 E H 0 G F D 0 E H 0 0 G H H 0 0 G H H VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 43
44 6.5 Over-the-ell Routing lgorithms 6.1 Terminology 6.2 Horizontal and Vertical onstraint Graphs Horizontal onstraint Graphs Vertical onstraint Graphs 6.3 hannel Routing lgorithms Left-Edge lgorithm Dogleg Routing 6.4 Switchbox Routing Terminology Switchbox Routing lgorithms 6.5 Over-the-ell Routing lgorithms OT Routing Methodology OT Routing lgorithms 6.6 Modern hallenges in Detailed Routing VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 44
45 6.5 Over-the-ell Routing lgorithms Standard cells are placed back-to-back or without routing channels Metal layers are usually represented by a coarse routing grid made up of global routing cells (gcells) ack to back Without routing channels VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 45
46 6.5 Over-the-ell Routing lgorithms Standard cells are placed back-to-back or without routing channels Metal layers are usually represented by a coarse routing grid made up of global routing cells (gcells) gcells Metal3 Metal1 (ells: ack to back) Metal2 (ell ports) Metal4 etc. VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 46
47 6.5 Over-the-ell Routing lgorithms Standard cells are placed back-to-back or without routing channels Metal layers are usually represented by a coarse routing grid made up of global routing cells (gcells) gcells Metal3 Metal1 Metal2 (ell ports) (Without routing channels) Metal4 etc. VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 47
48 6.5 Over-the-ell Routing lgorithms Standard cells are placed back-to-back or without routing channels Metal layers are usually represented by a coarse routing grid made up of global routing cells (gcells) Layers that are not obstructed by standard cells are typically used for over-the-cell (OT) routing Nets are globally routed using gcells and then detail-routed VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 48
49 6.5 Over-the-ell Routing lgorithms Three-layer approach Metal3 is used for over-the-cell (OT) routing Metal1 (ells) Metal3 Metal2 (Ports) VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 49
50 6.5 Over-the-ell Routing lgorithms Three-layer approach Metal3 is used for over-the-cell (OT) routing ell rea D Metal3 Metal2 Metal1 ell rea VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 50
51 GND Standard cell (only ports shown) Metal1 Metal2 Metal3 Ports in Metal2 OT routing in Metal3 hannel hannel routing in Metal1, Metal2 and Metal Springer Verlag VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 51
52 6.6 Modern hallenges in Detailed Routing 6.1 Terminology 6.2 Horizontal and Vertical onstraint Graphs Horizontal onstraint Graphs Vertical onstraint Graphs 6.3 hannel Routing lgorithms Left-Edge lgorithm Dogleg Routing 6.4 Switchbox Routing Terminology Switchbox Routing lgorithms 6.5 Over-the-ell Routing lgorithms OT Routing Methodology OT Routing lgorithms 6.6 Modern hallenges in Detailed Routing VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 52
53 6.6 Modern hallenges in Detailed Routing Manufacturers today use different configurations of metal layers and widths to accommodate high-performance designs Detailed routing is becoming more challenging, for example: Vias connecting wires of different widths inevitably block additional routing resources on the layer with the smaller wire pitch dvanced lithography techniques used in manufacturing require stricter enforcement of preferred routing direction on each layer VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 53
54 6.6 Modern hallenges in Detailed Routing Representative layer stacks for 130 nm - 32 nm technology nodes W2 U2 W1 U1 E2 M6 M5 M4 M3 M2 M1 2 1 M5 M4 M3 M2 M1 E2 E M4 M3 M2 M M4 M3 M2 M1 130 nm 90 nm 65 nm 45 nm 32 nm E1 E M5 M4 M3 M2 M Springer Verlag VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 54
55 6.6 Modern hallenges in Detailed Routing Semiconductor manufacturing yield is a key concern in detailed routing Redundant vias and wiring segments as backups (via doubling and non-tree routing) Manufacturability constraints (design rules) become more restrictive Forbidden pitch rules prohibit routing wires at certain distances apart, but allows smaller or greater spacings Detailed routers must account for manufacturing rules and the impact of manufacturing faults Via defects: via doubling during or after detailed routing Interconnect defects: add redundant wires to already routed nets ntenna-induced defects: detailed routers limit the ratio of metal to gate area on each metal layer VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 55
56 Summary of hapter 6 ontext Detailed routing is invoked after global routing Usually takes about as much time as global routing For heavily congested designs can take much longer Generates specific track assignments for each connection Tries to follow "suggestions" made by global routing, but may alter them if necessary small number of failed global routed (disconnected, overcapacity) can be tolerated More affected by technology & manufacturing constraints than global routing Must satisfy design rules VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 56
57 Summary of hapter 6 Routing Regions reaks down the layout area into regions hannels have net terminals (pins) on two sides Switch-boxes have terminals on four sides hannels are joined at switchboxes When the number of metal layers is >3, use over-the-cell (OT) routing Divide the layout region into a grid of global routing cells (gcells) OT routing makes the locations of cells, obstacles and pins less important hannel and switchbox routing can be used during OT routing when upper metal layers are blocked (by wide buses, other wires, etc.) The capacity of a region is limited by the number of tracks it contains hannels, switchboxes, gcells VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 57
58 Summary of hapter 6 lgorithms and Data Structures Horizontal and vertical constraint graphs capture constraints that must be satisfied by valid routes Simplest algorithms for detailed routing are greedy Every step satisfies immediate constraints with minimal routing cost Use as few bends as possible (doglegs are used when additional bends are needed) Very fast, do a surprisingly good job in many cases Insufficient for congested designs Switchbox routing algorithms are usually derived from channel routing algorithms Strategy 1: Do not create congested designs and rely on greedy algorithms Strategy 2: ccommodate congested designs and develop stronger algorithms VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 58
59 Summary of hapter 6 Modern hallenges Variable-pitch wire stacks Not addressed in the literature until 2008 Satisfying more complex design rules Min spacing between wires and devices Forbidden pitch rules ntenna rules Soft rules Do not need to be satisfied an improve yield by decreasing the probability of defects Redundant vias In case some vias are poorly manufactured Redundant wires In case some wires get disconnected VLSI Physical Design: From Graph Partitioning to Timing losure hapter 6: Detailed Routing 59
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