Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology
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1 Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology
2 OUTLINE Introduction Mapping for Schematic and Layout Connectivity Generate Layout from Schematic Connectivity Some Useful Features Virtuoso Custom Placer and Router Some Layout Editing Tips
3 History of Layout Generation Layout: Each layer of each devices were drawn manually Layout L: PDKs offer pre-made scalable devices. pcells can be individually added to your layout. Layout XL: Generate layout from schematic (pcells Parametrized Cells)
4 Layout L and Layout XL File New Cell View Application / Open with choose Layout XL Hit -- Always use this application for this type of file
5 Layout L and Layout XL Tools Design Synthesis LayoutXL (In cadence 5) Launch LayoutXL (In cadence 6)
6 Layout L and Layout XL See the below menu
7 OUTLINE Introduction Mapping for Schematic and Layout Connectivity Generate Layout from Schematic Connectivity Some Useful Features Virtuoso Custom Placer and Router Some Layout Editing Tips
8 Mapping Launch Configure Physical Hierarchy Physical Library and Physical Cell should be set
9 Mapping If you have existing design, you can map with Connectivity Update Device Corresponding
10 OUTLINE Introduction Mapping for Schematic and Layout Connectivity Generate Layout from Schematic Connectivity Some Useful Features Virtuoso Custom Placer and Router Some Layout Editing Tips
11 Generating Layout From Schematic Connectivity Generate All from Source Connectivity Generate Pick from Schematic File Import XL Netlist (Generates from CDL)
12 Generating Layout From Schematic Change default pin layers to which layer you want Set pins from Create Label As Hit Ok, Cadence automatically creates and places the instances in your layout
13 Generating Layout From Schematic Shift - f
14 Displaying Levels Options Display Set Display level from 0 to 32 (Shift - f) Options Display Set Display level from 0 to 0 (Ctrl- f)
15 Boundary Box Move the cells inside purple bounding box It is not necessary to use it If rules and constraints are entered, Cadence can do automatic routing, which is not optimal in most cases. Route Automatic Routing
16 OUTLINE Introduction Mapping for Schematic and Layout Connectivity Generate Layout from Schematic Connectivity Some Useful Features Virtuoso Custom Placer and Router Some Layout Editing Tips
17 Connectivity When you select a device or a pin in schematic, it will be highlighted in layout
18 Connectivity Cell boundary Pins transistors
19 Connectivity Moving a device or a pin will show its connections with other devices
20 Connectivity
21 Connectivity
22 OUTLINE Introduction Mapping for Schematic and Layout Connectivity Generate Layout from Schematic Connectivity Some Useful Features Virtuoso Custom Placer and Router Some Layout Editing Tips
23 Design Rule Driven (DRD) Options DRD Edit Off Notify Enforce This is a kind of DRC during layout editing
24 Transistor Chaining Move transistor Flight Line will appear Drag the transistor from the highlighted side Vias will be aligned Chaining is achieved From Virtuoso XL Options, Auto Abutment needs to be turned on
25 Transistor Folding Edit Transistor Folding Specify the number of gates and width of each gate Split devices can automatically abutted Abutment can be done while moving devices
26 Permuting Pins & Swaping Devices Connectivity Permute Pins Allows pins of a p-cell device to be swapped Options Virtuoso XL turn on Auto Permute Edit Other Swap Components Swaps selected two components, does not swap connections
27 Aligning Devices Edit Other Align Align any object, instance, layer along its edge, origin or center Minimum separation distance can be applied This comment does not read design rules
28 Property Transistor properties Bulk Gate Fingers Drain/Source Edit Property or q Transistor parameters can be modified during editing layout
29 Property Set bulk connection (left, right, dual, abutted, non-abutted) Set gate fingers connection (top, bottom, both, poly, metal) Set drain/source connection
30 Creating Wires & Guard Rings Wire Create path - p Create shape r Create Point to point ctrl + shift +p Create Multipart Path (MPP creates contact arrays, guard rings, shielded wires) Create Guided routing ctrl + shift + g (creates guard rings) Route Automatic Routing Paths can be used with DRD
31 Creating Via Create Via O hot key
32 Incomplete Nets Connectivity Nets Show/Hide Selected Incomplete Nets
33 Creating Label Create Label l
34 OUTLINE Introduction Mapping for Schematic and Layout Connectivity Generate Layout from Schematic Connectivity Some Useful Features Virtuoso Custom Placer and Router Some Layout Editing Tips
35 Virtuoso Custom Placer & Router It needs placer.rul and router.rul rule files Boundary Box is needed Generally, it is not optimal
36 Virtuoso Custom Placer & Router
37 Virtuoso Custom Placer & Router Place Partitioning Name partitions Link to schematic Create rectangles for partitions Hit the Attach Shape
38 Virtuoso Custom Placer & Router Place Placement Planning Choose the Components Chose the Allign Components Calculate Estimate Will calculate the area of NMOS and PMOS in the boundary
39 Virtuoso Custom Placer & Router Place Placer Choose the Group CMOS Pairs Choose the Optimize Placement Click on Set file Select the rule file
40 Virtuoso Custom Placer & Router
41 Virtuoso Custom Placer & Router Route Export to Route Select Cadence chip assembly There may be some other router depending on your licenses
42 Virtuoso Custom Placer & Router AutoRoute Detail Router Detail Route Hit OK
43 Virtuoso Custom Placer & Router Auto route Clean Change number of passes Remove higher layer of metals Try until it seems fine
44 Virtuoso Custom Placer & Router Add NTAP and PTAP Create Instance Fill the # of rows and colums
45 Virtuoso Custom Placer & Router
46 OUTLINE Introduction Mapping for Schematic and Layout Connectivity Generate Layout from Schematic Connectivity Some Useful Features Virtuoso Custom Placer and Router Some Layout Editing Tips
47 Layout Editing Tips During layout editing try to use Mark/Unmark Nets Array Copy Chop the Line Split the Line Change the origin
48 Engineering Change Order (ECO) During layout editing Make required changes to the schematic Connectivity Check against Source (check the layout against the schematic, missing devices in the layout highlighted in schematic) Connectivity Update Components and Nets (updates the layout with new schematic connectivity, components and pins) Connectivity Update Layout parameters (updates the layout with new schematic parameters) Highlights old extra devices, place new devices, highlights wrong connections
49 References Cadence Automated Custom Physical Design Manual Cadence Tutorial of VLSI Research Group CACS, Chaitanya Emmela North Carolina State University Tutorials
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