1.1 INDUSTRY STANDARD BUS-IOM

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1 Design and Implementation of Extended PCM Interface Controller (EPIC) with reduced clock frequency # Nalini Iyer Jagadish Hadimani*, Santoshkumar chavan*** naliniciyer@yahoo.com* jagadish_hadimani@yahoo.com, ***santosh_s_chavan@yahoo.com B.V.B College of Engineering and Technology, Hubli Abstract This paper presents a design and implementation of EPIC, with reduced clock frequency as compared to available EPIC to suit to the requirements of C- DOT s access network. IOM bus structure is used in the design of EPIC to support ISDN and analog applications which eliminates the need to have microprocessor interface for major IC s on the line card, thus reducing and simplifying the line card cost and layout. Reduction of the clock frequency to 2 MHz compared to 4 MHz in commercially available EPIC is achieved by the use of two data memories, with 128 bytes corresponding to 128 channels for read and writes operations simultaneously, targeted towards the ideal switch architecture. One major application of the EPIC is therefore as line card controller. 1.Introduction The field of telecommunication has gone a rapid change with the advent of ISDN[1]. The demand for higher bandwidth and data rate was catered by ISDN. The ISDN brought with itself the data traffic, which should be properly switched on to the PCM side for transmission through the conventional copper wire cable. The signalling information in ISDN lines put a extra burden on processors in the line cards. To solve these problems Extended PCM Interface Controller (EPIC) evolved which is heart of such a switching application[ 2] The EPIC is principally an intelligent switch of PCM data between two serial interfaces, the system interface (PCM interface) and the configurable interface (CFI). This paper presents the design and synthesis of EPIC using VHDL on Altera s FPGA.The proposed design makes use of IOM bus to support ISDN and analog application, which eliminates the need to have a microprocessor interface on the transceiver or code, thus reducing and simplifying the line card layout and cost. The EPIC can handle up to 32 ISDN-subscribers with their 2B +D channel structure or up to 64 analog subscribers with their 1B channel structure in IOM-configuration 1.1 INDUSTRY STANDARD BUS-IOM The inter-chip bus structures that were used in single channel per line pre- ISDN telephone equipment are not well suited for the 2B+D structure of ISDN[5]. To overcome the above difficulties, new standard bus interface architecture (an industry standard bus) named ISDN Oriented Modular (IOM) interface was designed jointly by 4 major European telephone equipment manufacturers to support both ISDN and analog lines. The IOM bus provides a symmetrical full-duplex communication link, containing user data, control/programming, and status channels. Both the line-card and the ISDN terminal utilize the same basic frame and clocking structure, but differ in the number and usage of the individual channels. The various channels are time-multiplexed over a four-wire serial interface. Frames are delimited by 8-kHz frame synchronization clock (FSC). Data is carried over data upstream (DU) and data downstream (DD) signals. By supporting multiplexing (providing) of data, control, and status information over a serial channel, the IOM bus eliminates the

2 need to have microprocessor interface on the transceiver or codec. This reduces pin count and simplifies line-card layout and thus reduces its cost. The frames are subdivided into eight sub-frames, with one sub-frame being dedicated to each transceiver or pair of codec s. Organisation of the rest of the paper is as follows. Section 2 deals with the architecture of EPIC. Section 3 deals with Monitor channel operation. Section 4 presents the design methodology. Results are simulated and validated in section 5. Section 6 presents conclusions. 2 Architecture of EPIC The EPIC is principally an intelligent switch of PCM data between two serial interfaces, the system interface (PCM interface) and the configurable interface (CFI). Up to 128 channels per direction can be switched dynamically between the CFI and the PCM-interfaces, each having a bandwidth of 64 Kbps. The architecture of EPIC deals with four major functional blocks namely PCM Interface Configurable Interface Pre-processed channel Memory Structure 2.1 PCM Interface: The serial PCM interface provides 4 duplex ports consisting each of a data transmit TxD and data receive RxD and a tristate control (TSC) line. The transmit direction is referred to as upstream direction, where as receive direction is referred to as downstream direction. The output data rate is Mbps, which implies 32 time slots per frame on all four ports. The PCM interface has to be clocked with PCM Data Clock (PDC) signal having a frequency equal to the PCM data rate i.e., Mbps. For the synchronization of the time slot structure to an external PCM system, a PCM Framing Signal (PFS) must be applied with a frequency of 8 khz. 2.2 Configurable Interface The configurable interface has four duplex ports each consisting of a data output (DD) and a data input (DU) line. The output pins are called Data Downstream pins and the input pins are called Data Upstream pins. This interface is suited to realize a standard serial PCM interface (PCM highway) or to implement an IOM (ISDN-Oriented Modular) interface. The IOM interface generated by the EPIC offers all the functionality like C/I- and monitor channel handling required for operating all kinds of IOM compatible layer-1 and codec devices.the CFI-data rate is also at Mbps on all the four ports. Unassigned time slots of both PCM and CFI may be either tri-state or programmed to transmit a defined idle value Switching Functions The major task of EPIC is to dynamically switch PCM data between the serial PCM interface and the serial configurable interface (CFI). The switching functions of EPIC are as shown in Figure- 1. Figure-1.Switching paths CFI PCM time slot Switching Switching paths 1 and 2 of Figure- 1 can be realized for a total number of 32 channels per path. To establish a connection, the microprocessor writes the addresses of the involved CFI and PCM time slots to the control memory. The actual transfer is then carried out frame by frame without further microprocessor intervention. The upstream switching part is realized as random write sequential read. Switching paths 3 and 4 can be realized by programming time slots assignments in the control memory.

3 Looping back a time slot from CFI to CFI requires a spare upstream PCM time slot and looping back a time slot from PCM to PCM requires a spare downstream and upstream CFI time slot. 2.3 Pre-processed channel The pre-processed channel option must always be applied to two consecutive time slots. If two time slots are declared as pre-processed channel, the first one being always even can be accessed by the monitor/feature control handler, which gives access to the frame via 16-byte FIFO. This function is mainly intended for IOM applications. The second pre-processed time-slot, the odd one, is also accessed by the microprocessor. In upstream direction, the received 8-bit value can be read. A change detection mechanism will generate an interrupt upon a change in any of the C/I value. 2.4 Memory Structure The EPIC memory is composed of the control Memory (CM) and the Data Memory (DM). The memory structure of EPIC is shown in Fig- 2 data field depends on the function defined by the code field. Data Memory The data memory refers to the PCM interface such that for each upstream time slot there is a 4 bit code field and an 8 bit data field location, whereas for each downstream time slot there is only an 8 bit data field location and no code field. The data memory data field are two in number with 128 bytes each, corresponding to 128 channels. At any point of time one data memory will be read and the other will be written i.e., one memory will be getting the data to be transmitted and the other will be reading out the data. After a period of 125us (i.e., one frame time) the roles of the data memories are going to be interchanged. This approach implements ideal time switch architecture and hence there will be no frame delays involved. 3 MONITOR CHANNEL OPERATION 3.1 HANDSHAKE PROCEDURE The monitor channel is full duplex and operates on a pseudo-asynchronous basis, that is, while data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using the MX and MR bits. MR being held inactive for two or more frame times indicates the receiver is signaling an abort. 4. DESIGN METHODOLOGY Figure-2. Memory structure Control Memory The control memory refers to the Configurable Interface (CFI) such that for each CFI time slot and for each direction (upstream and downstream) there is a 4-bit code field and an 8-bit data field location. The code field is of 4 bits with 128 such locations corresponding to 128 channels. The code field defines the function of the corresponding CFI time slot. The data field is of 8 bits with 128 such locations corresponding to128 channels. The use of the control memory 4.1 UPSTREAM The proposal for the implementation of the design of upstream part of EPIC is as shown in Figure- 4. The data to the CFI interface is coming serially through the four ports DU0, DU1, DU2, and DU3. The serial data is converted into parallel data using Serial in Parallel out (SIPO). The selector selects one of the inputs based upon select signals generated from the timing generator. This data is written into one of the data memory banks (one that is being written). The control memory data field that is read at the same time specifies the address. The timing generator gives the necessary

4 timing signals to all blocks to synchronize various events. Figure-4. Downstream Design Figure- 3 Upstream Design The code field of the control memory tells whether the data is to be written into data memory or not, as it determines whether the particular time slot is switched or a pre-processed. The other data memory bank reads out the data sequentially synchronized with the PFS (PCM Frame Synchronization). The Parallel in Serial Out shift register transmits this data serially at the PCM ports. The roles of the memories are interchanged after a PFS event. If the control memory code field indicates the pre-processed channel then data is handled by the layer-1 functions i.e., MF (Monitor Feature) handler for the MF channels and C/I (Command Indication) handler for the signaling channels. 4.2 DOWNSTREAM Downstream design is basically Sequential Write Random Read. We propose the following design for the implementation of downstream design of EPIC as in Figure-5. In our design we consider that one of the data memory data field is written sequentially whenever the data from SIPO is latched and the other one is read out depending on the address specified by the control memory data field. The address for the memory which is written is provided by a counter which counts up to 31 (1F) H After the write counter has reached to 31, both the data memory data fields are exchanged. A counter, which acts as a source of read address, reads the data written into the control memory sequentially. This address-generating counter counts from 0 to MF HANDLER DESIGN Monitor Channel operates on an asynchronous basis. The flow of data is controlled by the handshake procedure based on the monitor channel receive (MR) and the monitor channel transmit (MX) bits located at the end of the fourth time slot of the respective IOM channel. EPIC can act both as a transmitter or receiver[4]. The proposed design for the MF handler is as shown in Figure-5. Figure-5. MF Handler Design The major design issues concerning the MF handler are 1. Access control of FIFO

2. Start transmitter and receiver sections after receiving command from CMDR 3. Generation of MX and MR bits according to the handshake protocol. 4.

5 2. Start transmitter and receiver sections after receiving command from CMDR 3. Generation of MX and MR bits according to the handshake protocol. 4. Generation of Status signals for microprocessor and timing signals to Transmitter and Receiver sections. 5.Simulation Results EPIC design is implemented using Altera s MAXPLUS-II synthesis able tool.the simulation results for upstream and downstream are as shown below respectively, Figure-6 Upstream Design Acknowledgement The work was carried out using the in house facilities at B.V.B College of Eng. and Tech. Hubli and was supported by C- DOT Bangalore. Bibliography 1. World telecommunication development Report 1995-Information Infrastructure. 2. Carel-Jan Van Driel, Peter A.M. van Grinsven, Verus Pronk and Wilfred A.M. Snijders, The R evolution of Access Networks for the Information Superhighway. IEEE Commun. Mag. June Colin Low, Integrating communication services, IEEE Commun. Mag. June Bharat Doshi and P. Harshavardhana, Broadband Network Infrastructure of the Future: Roles of Network Design Tools in Technology Development Strategies, IEEE Commun. Mag. May, Bill White, Multimedia Telecommunications, Chapman & Hall 1997 Figure-7 Downstream Design 6.Conclusion The simulation result of modified EPIC with ideal time switch architecture validates the reduction of clock frequency. The modified design of EPIC with reduced clock frequency of 2 MHz is implemented on Altera s Flex10k using Altera s MAXPLUS-II synthesisable tool to suit to the requirements of C-DOT s access network.

Single Channel HDLC Core V1.3. LogiCORE Facts. Features. General Description. Applications

Single Channel HDLC Core V1.3. LogiCORE Facts. Features. General Description. Applications Sept 8, 2000 Product Specification R Powered by Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: logicore@xilinx.com URL: www.xilinx.com/ipcenter Support: