INTERNATIONAL JOURNAL OF PROFESSIONAL ENGINEERING STUDIES Volume 9 /Issue 5 / JAN 2018

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1 Implementation of an Efficient Content Addressable Memory Based on Sparse Cluster Network Basumala Chandram 1 Dr. P.Sreenivasulu 2 Dr. P. Prasanna Muralikrishna 3 chandu6240@gmail.com 1 psrinivas.vlsi@gmail.com 2 pprasannamurali@gmail.com 3 1 PG Scholar, VLSI Design, Krishna Chaitanya Institute of Technology & Sciences, Devarajugattu, Peddaaraveedu, Prakasam, Andhra Pradesh. 2 Professor, Department of ECE, Krishna Chaitanya Institute of Technology & Sciences, Devarajugattu, Peddaaraveedu, Prakasam, Andhra Pradesh. 3 Professor, Department of ECE, Krishna Chaitanya Institute of Technology & Sciences, Devarajugattu, Peddaaraveedu, Prakasam, Andhra Pradesh. Abstract: The Content-addressable memory (CAM) is frequently used in many applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due to its ability to improve application performance by using parallel comparison to reduce search time. This paper proposes a low-control Content-Addressable Memory (CAM) using another count for agreeably between the data tag and the relating area of the yield data. This architecture is based on recently developed sparse clustered networks using binary connections that on average eliminate most of the parallel comparisons which are performed during a search using Load Store Queue (LSQ). When the input data is given with a tag, the search is performed among the stored data and when a match occurs between the input and stored value, the output will display the input data which is given. Also when an mismatch occurs between the input and stored data, the output will not be display the input value. Thus reducing the power consumption and delay estimation by using SCN- CAM. Extension of the project is Pre computation-based Content Addressable Memory. Results are observed from Microwind and DSCH software. Keywords Associative memory, Content Addressable Memory (CAM), Sparse Cluster Networks(SCNs), Load Store Queue(LSQ),Digital Schematic (DSCH). I. INTRODUCTION A Content-Addressable Memory (CAM) is a critical device for applications involving Asynchronous Transfer Mode (ATM), communication networks, Local Area Network (LAN) bridges/switches, databases, lookup tables, and tag directories, due to its high-speed data search capability. A CAM is a functional memory with a large amount of stored data that simultaneously compares the input search data with the stored data. Once matching data are found, their addresses are returned as output. CAM is a type of memory that can be accessed using its contents rather than an explicit address. CAM can be used as a coprocessor for the Network Processing Unit (NPU) to offload the table lookup tasks. CAMs are fast data parallel search circuits. Unlike standard memory circuits, for example Random Access Memory (RAM) data search is performed against all the stored information in single clock cycle. In fact CAM is out growth of RAM. While CAM's are widely used in many applications like memory mapping, cache controllers for central processing unit, data compression and coding etc. It s primary application is fast Internet Protocol (IP) package classification and forwarding at high speed network routers and processors. IP routing is accomplished by examination of the protocol header field s i.e. the originating and destination address, the incoming and outgoing ports against stored information in the routing tables. If a match is registered the package is forwarded towards the port(s) defined in the table. On very high speed networks and huge traffic volume the task is to be performed in fast and massive parallelism. However, managing high speeds and large lookup tables requires silicon area and power consumption. The power dissipation, silicon area and the speed are three major challenges for designers. Since there is always trade-off between them. The circuit structure of a CAM word which is made of CAM cells. A CAM cell compares its stored bit against its corresponding search bit provided on the Search Line (SL). The combined search result for the entire word is generated on the Match-Line (ML). The

2 Match -Line Sense Amplifier (MLSA) senses the state of the ML and outputs a full logic swing signal. At the circuit level, research has focused on saving power by reducing the ML and SL signal swing or using low-power current-based approaches. Even with these circuit innovations, the simple CAM circuit structure can be designed that has a very high power consumption if it is used directly to construct a large capacity CAM. II. OVERVIEW OF CAM In the conventional CAM array, each entry of a tag that, if matched with the input, points to the location of a data word in a Static Random Access Memory (SRAM) block. The actual data are stored in the SRAM and a tag is simply a reference to it. Therefore, when it is required to search a data in the SRAM, it suffices to search for its corresponding tag. Figure: 1.Typical CAM Array Search line drivers are used to store the input bits. The register applies the search data on the differential search lines, which is shared among the entries. Then the search data are compared with the CAM entries. Each CAM-word is attached to a match line among its constituent bits, which indicates, whether they match with the input bits. III. LITERATURE REVIEW Fully parallel Content Addressable Memory (CAM) LSI using a compact dynamic Content Addressable Memory cell with a stackedcapacitor structure and a novel hierarchical priority encoder [1]. The proposed CAM cell is shown in Figure 1. It consists of five NMOS transistors and two stacked capacitors. Four of the transistors (Ms0, Ms1, Mw0, Mw1) are used to store and access data, and one (Md) is used as a diode to isolate current paths during match operations. Charges are stored on stacked capacitors (Cs0, Cs1) and the Ms0 and Ms1 gates. The opposite electrodes of the Cs0 and Csl are connected to a cell plate voltage Vcp, which is equal to half Vcc (Vcc: supply voltage). Two bit lines are supplied with data in write and search operations. The Word Line (WL) allows write access to each cell in a word. The match line (ML) passes through a word to perform a logical AND of the results of each cell s comparison. The ML is also used to read cell data. The storage capacitor (Cs0) is stacked on the gate of the Ms0 and Mw0. The gate electrodes of the Ms0 and Mw0are fabricated with the first poly-si layer [1]. The stacked capacitor is composed of the second poly-si layer, the insulator film, and the third poly-si layer. The second poly-si layer (storage node) is also used to connect the drain (or source) of the Mw0 to the gate of the Ms0.Similarly, the storage capacitor (Csl) is formed on the gate of the Msl and Mwl. A write operation is performed by activating a select WL and then driving the bit lines according to the write data. A read operation is accomplished by discharging the bit lines and then driving a selected ML to a high level. A read operation is accomplished by discharging the bit lines and then driving a selected ML to a high level. A match operation is achieved by pre charging both the bit lines and the match lines to a high level, and then loading the bit lines with search data. When match occurs at several words in a search operation (multiple response), the CAM outputs the address of the matched word with the highest priority. A Priority Encoder (PE) circuit is utilized for multiple-response resolution and match address generation [1]. As a bit capacity of Content Addressable Memory s becomes larger, the number of words increases rather than the bit length of words. Thus in a high density Content Addressable Memory chip, the configuration is such that the cell array is divided into several blocks. This creates a serious problem concerning the layout of the priority encoder. When the priority encoder is incorporated in each block, the silicon area occupied by the priority encoder and the power dissipation of the priority encoder are increased in proportion to the number of divided blocks. So in order to overcome this, novel hierarchical priority encoder architecture suitable for high-density CAM was proposed.

3 Energy reduction of CAMs employing circuit-level techniques are mostly based on the following strategies: 1) reducing the SL energy consumption by disabling the pre-charge process of SLs when not necessary, and 2) reducing the ML precharging, for example, by segmenting the ML, selectively pre-charging the first few segments and then propagating the pre-charge process if and only if those first segments match. This segmentation strategy increases the delay as the number of segments is increased. A hybrid-type CAM integrates the lowpower feature of NAND type with the highperformance NOR type [12] while similar to selective pre charging method, the ML is segmented into two portions. The high-speed CAM designed in 32-nm CMOS [1] achieves the cycle time of 290ps using a swapped CAM cell that reduces the search delay while requiring a larger CAM cell transistors than a conventional CAM cell transistors used in SCN-CAM. A high-performance AND-type match-line, where multiple fan-in AND gates are used for low switching activity along with segmented-style match-line evaluation to reduce the energy consumption. After loading, the activated data will be displayed in the Random Access Memory. When there is a match in the memory the output will be displayed. When the match doesn t occur the output will not be displayed. A. SCN-CAM The Content Addressable Memory is designed based on Sparse Cluster Network which reduces the comparisons during the search. When the data is given inside the SCN, it enables the data that is stored inside the CAM. When the data is enabled, there is a match between the input and stored value. The output will be displayed when there occurs a match between the stored data. IV.PROPOSED SCN-CAM The Content Addressable Memory based Sparse Cluster Network is designed using binary connections that eliminates the parallel comparisons during the search. When an input data is given inside the network, it is compared with the stored data. When the match occurs between the input and stored value, it eliminates the other data stored. This reduces the power consumption of an SCN-CAM. The blocks of Sparse Cluster Network CAM (SCN- CAM) consists of an SCN-based classifier, which is connected to a special-purpose CAM array. The SCN-based classifier is first trained with the association between the tags and the address of the data to be later retrieved. The CAM array is based on a typical architecture, but is divided into several sub-blocks that can be compare-enabled independently. So, when the input data is given inside the SCN, it will consider the few possibilities of matching data that are similar to the input value. Now, this data will be given inside the CAM blocks. The CAM blocks will compare the input value with the data that have already stored in it. When there occur a match between the input and stored value, the output will be activated. Once the sub-blocks are activated, the tag is compared against the few entries in them while keeping the rest deactivated. Then the data is loaded inside the Queue. Figure: 2. SCN-CAM Figure 2 shows the block of Proposed SCN CAM. Here when the input is given inside the network, that data will be searched inside the network. When there is a match occurred between the stored data, the output will be displayed in the data out pin. The pass/fail pin is used to display pass value during the functional mode operation. The fail condition is displayed during the test mode operation. B. Architecture of SCN based Classifier The proposed architecture (SCN-CAM) consists of an SCN-based classifier, which is connected to a special-purpose CAM array. The classifier is at first trained with the association

4 between the tags and the address of the data to be retrieved later. The proposed CAM array is based on a typical architecture, but is divided into several subblocks which can be activated independently. Therefore, it is also possible to train the network with the associatively between the tag and each CAM subblock, if the number of desired sub blocks is known. However, in this paper, the focus is on a generic architecture that can be easily optimized for any number of CAM sub-blocks. Once an input tag is given to the SCN-based classifier, it predicts which CAM sub-block(s) need to be activated and thus saves the dynamic power by disabling the remaining sub-blocks. In this paper the possibility of reducing the number of comparisons to only one in average is shown. SCN-CAM uses only a portion of the actual tag to create or recover the association with the corresponding output. The operation of the CAM, on average, allows this reduction in the tag length. A large enough tag length permits SCN-CAM to always point to a single subblock. However, the length of reduced-length tag affects the hardware complexity of the SCN-based classifier. The length of the reduced-length tag is not dependent on the length of the original tag but rather dependent on the number of CAM entries. Figure: 3. Top level view of SCN CAM Tag Decoding Once the SCN-based classifier has been trained, the ultimate objective after receiving the tag is to find out which neuron(s) in PII should be activated based on the given q bits of the tag. This process is called decoding in which the connection values are recalled from the memory. The decoding process is divided into four steps. 1. An input tag is reduced in length to q bits and divided into c equally sized partitions. The q bits of the entire tag can be selected in such a way to reduce the correlation. 2. Local Decoding (LD): A single neuron per cluster in PI is activated by using a direct binary-tointeger mapping from the tag portion to the index of the neuron to be activated. 3. Global Decoding (GD): GD determines which neuron(s) in PII must be activated based on the results from LD and the stored connection values. If there is at least one active connection from each cluster in PI toward a neuron in PII, that neuron is activated. GD can be expressed. V. EXTENSION PB-CAM Architecture Fig. 4 shows the memory organization of the PB-CAM architecture proposed by Lin et al., which consists of data memory, parameter memory, and parameter extractor, where k << n. To reduce massive comparison operations for data searches, the operation is divided into two parts. In the first part, the parameter extractor extracts a parameter from the input data, which is then compared to parameters stored in parallel in the parameter memory. If no match is returned in the first part, it means that the input data mismatch the data related to the stored parameter. Otherwise, the data related to those stored parameters have to be compared in the second part. It should be noted that although the first part must access the entire parameter memory, the parameter memory is far smaller than that of the CAM (data memory). Moreover, since comparisons made in the first part have already filtered out the unmatched data, the second part only needs to compare the data that match from the first part. The PB-CAM exploits this characteristic to reduce the comparison operations, thereby saving power. Therefore, the parameter extractor of the PB-CAM is critical, because it determines the number of comparison operations in the second part. As we stated previously, the parameter extractor plays a significant role since this circuit determines the number of comparison operations required in the second part. Therefore, the design goal of the parameter extractor is to filter out as many unmatched data as possible to minimize the required number of comparison operations in the second part. Lin et al. adopted the ones-count function to perform parameter extraction. For ones count approach, with an n-bit data length, there are n+1 types of ones count (from 0 ones to n ones count). Further, it is necessary to add an extra type of ones count to indicate the availability of stored data. Therefore, the minimal bit length of the parameter is equal to log(n + 2). The

5 parameter extractor for the ones-count approach is implanted with full adders. Layout Design of SCN-CAM. Simulation Result of SCN-CAM. Figure: 4. Memory organization of the PB-CAM architecture VI. RESULTS Schematic Design of Proposed SCN-CAM. VII. CONCLUSION The design of low power CAM based on SCN using LSQ technique is introduced here. SCN- CAM using LSQ is suitable for low power applications, where frequent and parallel look-up operations are required. SCN-CAM employs an SCNbased classifier, which is connected to several independently compare-enabled CAM sub-blocks some of which are enabled once a tag is presented to the SCN-based classifier. By using independent nodes in the output part of SCN- CAM s training network, simple and fast updates can be achieved without

6 retaining the network entity. SCN-CAM using LSQ eliminates most of the parallel comparison during the operation. In other words, a fail condition will be occurred due to the mismatched condition. As a result of this analysis it came to conclusion that the proposed content- addressable memory architecture with sparse clustered network is more advantageous and reliable one as compared to other architecture sparse clustered network content addressable memory employs a novel associatively mechanism based on a recently developed family of associative memories based on sparse cluster network. REFERENCES [1] Yamagata T, Mihara M, Hamamoto T, Murai Y, Kobayashi T, A 288-kb Fully Parallel Content Addressable Memory Using a Stacked-Capacitor Cell Structure, December [2] Schultz K and Gulak P, Fully parallel integrated CAM/RAM using pre classification to enable large capacities, J. Solid-State Circuits, May 1996; 5, [3] Zukowski C and Wang S Y, Use of selective Pre charge for low power on the match lines of content-addressable memories, Aug. 1997; [4] Lin C S, Chang J C, and Liu B D, A low power pre computation based fully parallel contentaddressable memory, J. Solid-State Circuits, April 2003; 4, [5] Pagiamtzis K and Sheikholeslami K, Pipelined match-lines and hierarchical search-lines for low power content-addressable memories, Sep. 2003; 39, [6] Ruan S J, Wu C Y, and Hsieh J Y, Low power design of pre computation-based content addressable memory, March [7] Onizawa N, Matsunaga S, Gaudet V C, and Hanyu T, High throughput low-energy content addressable memory based on self-timed overlapped search mechanism, May 2012; [8] Jarollahi H, Onizawa N, Hanyu T and Gross W J, Associative Memories Based on MultipleValued Sparse Clustered Networks, July [9] Jarollahi H, Gripon V, Onizawa N, and Gross W J, Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse clustered Networks, April [10] Gripon V and Berrou C, Sparse neural networks with large learning diversity, [11] Pagiamtzis K and Sheikholeslami A, Content Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey, J Solid State Electronics M arch, [12] Peng M and Azgomi S, Content-Addressable memory (CAM) and its network applications, 1996 BIOGRAPHIES: B.Chandram is currently a PG scholar of VLSI Design in The Stream of Electronics and Communications in Krishna Chaitanya Institute of Technology & Sciences, Devarajugattu, Markapur. He received B.TECH degree from QIS Institute of Techonolgy, Ongole, JNT University, Kakinada. Dr. P. SREENIVASULU is currently working as an Professor with the Department of Electronics & Communication Engineering, KITS, Markapur. He reccived the Doctorate in Ultra power VLSI, from JNT University, Kakinada.