EECS 427 Lecture 17: Memory Reliability and Power Readings: 12.4,12.5. EECS 427 F09 Lecture Reminders

Transcription

1 EECS 427 Lecture 17: Memory Reliability and Power Readings: 12.4, Reminders Deadlines HW4 is due Tuesday 11/17 at 11:59 pm ( submission) CAD8 is due Saturday 11/21 at 11:59 pm Quiz 2 is on Wednesday 11/25 Extended office hours this week Monday: 3 3:30 pm and after 5 pm Wednesday office hour is cancelled Sunday: noon 6 pm Half-lecture review in class on Monday 11/23 Extended office hours next week Monday 3 3:30 330pm and after 5 pm Tuesday 3 6 pm What is remaining after Quiz weeks to finish your project by 12/14 2 1

2 Last Time SRAM Configuration row address decoding and column decoding Sizing for read and write avoid read upset and ensure writability Address decoding predecoding + final decoding 3 Outline SRAM review SRAM sense amplifiers DRAM overview (3T and 1T) Memory reliability and yield Memory ypower reduction 4 2

3 4x4 SRAM Memory 2 bit words enable read precharge!bl BL bit line precharge WL[0] A 1 WL[1] A 2 WL[2] WL[3] clocking and control A 0 Cl Column Decoder sense amplifiers BL[i] BL[i+1] write circuitry Irwin and Narayanan 5 SRAM Cell Analysis (Read) WL=1 M5!Q=0 M1 M4 Q=1 M6 C bit C bit!bl=1 BL=1 Cell Ratio (CR) = (W M1 /L M1 )/(W M5 /L M5 ) Irwin and Narayanan 6 3

4 SRAM Cell Analysis (Write) WL=1 M5!Q=0 M1 M4 M6 Q=1!BL=1 BL=0 Pullup Ratio (PR) = (W M4 /L M4 )/(W M6 /L M6 ) Irwin and Narayanan 7 Cell Sizing 8 4

5 Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder 9 Hierarchical Decoders Multi-stage implementation improves performance WL 1 WL 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 2 A 3 A 2 A 3 A 2 A 3 A 2 A 3 A 1 A 0 A 0 A 1 A 3 A 2 A 2 A 3 NAND decoder using 2-input pre-decoders 10 5

6 Dynamic Decoders Precharge devices GND GND WL 3 WL 3 WL 2 WL 2 WL 1 WL 0 WL 1 WL 0 A 0 A 0 A 1 A 1 A 0 A 0 A 1 A 1 2-input NOR decoder Active high All WL s except one is pulled down 2-input NAND decoder Active low Only one WL is pulled down 11 Pass-transistor based column decoder BL 0 BL 1 BL 2 BL 3 A 0 S 0 S 1 S 2 A 1 S 3 2-input NOR decoder Advantages: speed (t pd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count D 12 6

7 Tree based column decoder BL 0 BL 1 BL 2 BL 3 A 0 A 0 A 1 A 1 D Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor approaches 13 Sense Amplifiers t p = C V I av make V as small as possible large small Idea: Use Sense Amplifer small transition s.a. input output 14 7

8 Differential Sense Amplifier M 3 M 4 y Out bit M 1 M 2 bit SE M 5 Directly applicable to SRAMs 15 Differential Sensing SRAM PC BL EQ BL y M 3 M 4 2 y WL i x M 1 M 2 SE M 5 2 x x 2 x SE SRAM cell i SE Diff. x Sense 2 x Amp y Output Output (a) SRAM sensing scheme SE (b) two stage differential amplifier 16 8

9 3-Transistor DRAM Cell WWL RWL WWL write M3 BL1 V dd M1 X M2 X V dd -V t C s RWL read BL1 BL2 BL2 V dd -V t V No constraints on device sizes (ratioless) Reads are non-destructive Value stored at node X when writing a 1 is V WWL -V tn 17 1-Transistor DRAM Cell WL WL write 1 read 1 C BL M1 C s X X V dd -V t BL BL V dd /2 V dd sensing Write: C s is charged (or discharged) by asserting WL and BL Read: Charge redistribution occurs between C BL and C s Read is destructive, so must refresh after read 18 9

10 Advanced 1T DRAM Cells Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Refilling Poly Transfer gate Isolation Storage electrode Storage Node Poly Si Substrate 2nd Field Oxide Trench Cell Stacked-capacitor Cell 19 DRAM Cell Observations DRAM memory cells are single ended (complicates the design of the sense amp) 1T cell requires a sense amp for each bit line due to charge redistribution read 1T cell read is destructive; refresh must follow to restore data 1T cell requires an extra capacitor that must be explicitly included in the design A threshold voltage is lost when writing a 1 (can be circumvented by bootstrapping the word lines to a higher value than V dd ) 20 10

11 Reliability and Yield 21 Sensing Parameters in DRAM 1000 C D(1F) V smax(mv) 100 C S(1F) Q S(1C) 10 Q S 5 C S /2 V smax 5 Q S /(C S 1 C D ) (V) 4K 64K 1M 16M 256M 4G 64G Memory Capacity (bits/chip) From [Itoh01] 22 11

12 Noise Sources in 1T DRAM BL substrate Adjacent BL C WBL a -particles WL leakage C S electrode C cross 23 Alpha-particles (or Neutrons) BL WL a -particle SiO n Particle ~ 1 Million Carriers 24 12

13 Yield Yield curves at different stages of process maturity (from [Veendrick92]) 25 Redundancy Redundant columns Redundant rows Memory Array Row Address Fuse : Bank Column Decoder Row Decoder Column Address 26 13

14 Error-Correcting Codes Example: Hamming Codes with e.g. B3 Wrong 1 1 = Redundancy and Error Correction 28 14

15 Power Dissipation in Memories CHIP I DD 5 S C i D V i f1s I DCP C PT V INT f nc DE V INT f selected m mi act I DCP n ROW DEC non-selected m(n2 1)i hld ARRAY PERIPHERY mc DE V INT f COLUMN DEC V SS EECS 427 F09 From Lecture [Itoh00] Data Retention in SRAM 1.30u I leakage 1.10u 900n 700n 500n (A) 300n Factor m m CMOS 0.18 m m CMOS 100n SRAM leakage increases with technology scaling 30 15

16 Suppressing Leakage in SRAM sleep L low-threshold transistor,int sleep,int SRAM cell SRAM cell SRAM cell SRAM cell SRAM cell SRAM cell sleep V SS,int Inserting Extra Resistance Reducing the supply voltage 31 Data Retention in DRAM I ACT Curren nt (A) I DC I AC Cycle time : 150 ns T 5 75 C,S5 97 mv/dec M 64M 255M 1G 4G 15G 64G Capacity (bit) Operating voltage (V) Extrapolated threshold voltage at 25 C (V) EECS 427 F09 From Lecture [Itoh00]