Design of a Low Power Content Addressable Memory (CAM)

Transcription

1 Design of a Low Power Content Addressable Memory (CAM) Scott Beamer, Mehmet Akgul Department of Electrical Engineering & Computer Science University of California, Berkeley {sbeamer, akgul}@eecs.berkeley.edu May 7, 009 Abstract Conventional CAM designs typically take up significantly more area, power, and sometimes delay compared to location addressed memories of the same capacity. If these penalties are traded off against each other, there will be many new applications for CAMs that are not feasible or practical today. In this study using EDP as a metric, we analytically evaluate individual CAM design techniques previously introduced in our midterm report, and discuss the tradeoffs in each technique. Our study shows that one can achieve significant reduction in matchline (ML) activity factor and thus power by using NAND type CAM cells, at the price of delay. On the contrary, NOR cells exhibit high activity factors and power dissipation, but with a quick ML evaluation phase. Utilizing both types, we find the optimum number of NAND cells for a given array size that minimizes the EDP, followed by low swing ML NOR cells. We also use a precomputation technique to reduce the number of search lines (SL) in the array by half, and to further reduce ML activity by 50%, resulting in substantial power and area savings. Finally, we present the optimum combination of these techniques by evaluating trade offs of various comination possibilities. Index Terms - CAM design, EDP figure of merit, NAND cell, NOR cell, 1 s precomputation, NAND-NOR hybrid optimization 1 Introduction Our study focuses on minimizing power consumption of a CAM array, without sacrificing the speed performance. For a CAM cell, there are three main parts that consume power[9]: 1. SRAM Array: There is a wide range of techniques to improve SRAM cell performance and power in literature, e.g. dynamic voltage scaling, lower retention voltage etc. But these techniques are not directly related to the CAM operation, and can be applied almost regardless of the chosen CAM cell architecture. Considering SRAM oriented techniques common to all CAM improvement methods in this report, we will not include SRAM optimization in this study, but rather elaborate on CAM specific methods.. Matchlines (ML): For the conventional CAM design, the ML is precharged, and then evaluated to discharge or stay high based on the match or not match decision of the evaluation circuit. The area, power and delay considerations of the ML routing limits the CAM array size and performance for many applications. In this study we will investigate methods to reduce ML delay, activity factor and power. 3. Search Lines (SL): Conventional CAM design uses complementary search lines, which results in a SL activity factor of 1. This high activity factor shows that SL improvement techniques are crucial for minimizing the CAM power and delay. In this study we present a way to avoid using complementary search lines, and reducing the activity factor to obtain area, power and delay benefits. In this study we will address both ML and SL optimization. As presented in our midterm report, there are two evaluation approaches for the ML: the NAND cell with low ML activity factor and low power but with a quadratic delay increase with length; and the NOR cell, with high activity factor and power but fast evaluation speed. We select the EDP (energy delay product) as a metric to evaluate various NAND and NOR based approaches. Our analysis shows that minimum EDP is achieved by using the optimum number of NAND cells in front to reduce the ML activity factor, followed by NOR cells to speed up the evaluation which is activated only when all preceding NAND cells match, which has an exponentally decaying probability as the NAND 1

2 3 Matchline Optimization Techniques 3.1 NOR Cell The NOR cell uses a full swing approach that precharges ML to VDD, and has NMOS switches to ground which short ML in the case of a mismatch. The advantage of NOR-type array is its worst case resistance from ML to ground does not grow with array size. But it is wasteful by charging ML to full swing VDD, both in terms of ML power and delay from waiting for the charge/dicharge of a full voltage swing Analytical Modeling Figure 1: Layouts for NAND and NOR CAM cells Cell Type Width (λ) Height (λ) Area (µ ) NOR NAND Half NOR Figure : Approximate layout dimensions and area, assuming λ =.5nm chain gets longer. Then we will analyze the precomputation method as a way to reduce the number of SLs to half by avoiding complementary operation and further reducing ML activity by 50%, leading to substantial savings in power, area and delay. Finally, we present the optimum combination of these methods as our proposed CAM design and demonstrate the improvement in terms of EDP as a metric. To create an analytical model for the energy and delay per NOR cell, we calculated the parasitic capacitance added by the source and drain junctions of the evaluation transistors. We also modeled the matchlines and searchlines by RC T-models. We denote ML capacitance per unit length as C ML, and when multiplied by the width of the NOR cell W, which is also the ML-to- ML wire pitch between cells, it gives us the total ML capacitance per cell, which we use in our T-model for the wire. A similar analysis applies to the ML reistance, where resistance per unit length R ML is multiplied the width of the NOR cell W. For the SL RC T-model, the same approach is applied again by changing the width W and the height H of the cell, which is the SL-to-SL pitch of the CAM array. C ML,NOR = C d + C ML W C SL,NOR = C g + C SL W Simulation Environment To verify our analytical models, we used HSPICE simulations with a predictive 45nm model [1]. As a starting point, reasonable layouts were made according to lambda rules [10] (Figure 1 and Table ). Since much of the power in a CAM is burned in long wires (searchlines or matchlines), simple RC T-models were made for each cell type and dimension using the same predictive model [1]. These T-models were used throughout our simulations, especially between cells or between cells and supplies. To assist with exploring the vast design space, we used Python code to automatically generate, execute, and collect simulation results. This code do more than simply sweep parameters, but it was also capable of assembling arbitrary numbers of elements (cells, wires, and supplies). E NOR = N k V V ML C M + αn k V A C M V SL The layout of the cell defines aconstant ratio between total ML capacitance C M and total SL capacitance C S, which we denote as A = C M CS Then we can define the following metric as energy per cell for a given supply voltage. E NOR V = N k C M ( V ML + α A V SL ) (1) By using the Elmore delay model for the ML and SL, we can write the following equations for delay: t d,ml = 0, 69C ML,NOR R MLW t d,sl = 0, 69(C g + C SL )R SLW N.(N + 1) M.(M + 1)

3 NOR - Full Swing NOR - Low Swing NOR - Half Cell NAND - High V t NAND - Low V t Figure 3: Evaluation of a NAND matchline 3.1. Low Swing Match Lines As (1) indicates, the energy is directly proportional to the voltage swing on the ML, V ML. Considering the worst case delay case of a NOR ML, which is only the NOR cell at the end of the array matching and the rest of the NMOS switches to ground being off, and hence discharging the whole ML through a single switch. Neglecting the ML wire reistance, we can model the ML and the addded drain junction parsitics of the NOR cells along the chain as a lumped capacitance C ML. Then we can write the follwoing simple delay model, which shows the worst case delay of the ML is also linealy proportional to V ML, like energy. i t = C V t ML,NOR V ML These arguments clearly show the advantages of low swing matchlines. The only drawback is, due to the reduced voltage swing, we need a sense amplifier at the end of the match line. For our project, we used a published sense amplifier [4] which has a 150 mv high-low transition threshold. To account for process variations, glitches and other noise sources, we picked V ML = 300mV with enough margin to avoid false evaluation. The delay and energy improvements obtained by the low swing method can be clearly seein in Fig 4and 5. In terms of area it is small cost that can be amortized over each row. 3. NAND Cell 3..1 Analytical Modeling Although it results in increased delay, the fact that the NAND ML is discharged through a series of NMOS chain comes with a power advantage [11]. As depicted in Figure 3, the part of the ML that discharges ends at the first mismatch location. Assuming a uniformly distributed random data pattern, the expected number of the discharged NAND cells as a function of NAND chain size is given by: E[N] = N i i = + N N N i=1 () Using, the average energy as a function of NAND chain length is given by the multiplication of expected Delay (ns) Number of NOR Cells Number of NAND Cells Figure 4: Delays for each cell type to pre-charge and evaluate Search Energy (fj/bit) NOR Full Swing NOR Low Swing NOR Half Cell Cell Type Searchline Energy Matchline Energy NAND High VT NAND Low VT Figure 5: Delays for each cell type to pre-charge and evaluate number of discharged bits and the energy per cell. 3.. Low V T Technique E NAND (k) = E[k] E,cell (3) The delay of the NAND cell suffers from the fact that the match case has to discharge through all the transistors in the NAND chain. If you refer to the NAND cell schematic we presented in our midterm report, the gates of the transistors in the discharge path of series of NAND cells experience a V T drop. Furthermore, the voltage experiences a V T drop across the first NAND cell switch and the precharge PMOS device. Hence, we loose V T compared to the supply, which is a significant amount for our low 1V supply voltage. To avoid this scenario, we edited the device model and added low V T NMOS devices with 100 mv lower thresh- 3

4 old voltage compred to the nominal devices supplied by the 45 nm PTM model. We replaced the NMOS devices on the discharge path with these low V T devices. this not only saves us the threshold drops but also reduces the on resistance of the swithces, which speeds up ML evaluation considerably. Normally low V T devices come with a lekage penalty. However, this does not apply to the NAND cam design, since the low V T NMOS devices form a series chain from the ML capacitance to ground, which passes thorugh a long chain of devices and hence suppresses the leakage.the significant delay benefits and energy comparison wrt. high V T NAND version is presented in Fig 4and NAND-NOR Design The preceding analysis shows that the NAND and NOR cells present complementary trends for energy and delay [1]. Our observations on NAND cell suggest that it is very advantageous in terms of ML power to have a number of NAND cells in series at the beginning of a CAM row, as seen from () and (3), yet there is a delay penalty as seen in Figure 4. On the other hand, (1) and Figure 4 and Figure 5 indicate that to achieve fast evaluation, one needs NOR cells, which come with a linear energy penalty. Once we observe the competing trends, we expect an optimum allocation of the number of NAND and NOR cells in the row for a given total length, which minimizes the multiplication of the two opposing parameters, energy and delay, i.e. EDP as our main metric. We analytically analyze the optimization problem, and verify the results with simulation data in the following. The most important observation in the NAND-NOR is, as pictured in Figure 6, the NOR ML charges only when all the NAND cells match, which has an exponentially decaying probability with increasing NAND length k, which is p(k) = 1. k Using this observation and and 3, we can write the total energy and delay of the NAND-NOR as: E tot (N, k) = E[k]E NAND,cell + p(k)e NOR,cell EDP (Js) 7 1e Figure 6: NAND-NOR matchline Number of NAND Cells Figure 7: EDP of a NAND-NOR matchline of various lengths and this agrees with the model. Additional NAND cells past the optimum continue to half the matchline activity factor for the NOR cells, but it is already beyond the point of diminishing returns. Additional NAND cells also greatly increase the delay, which is penalized with the EDP figure of merit. Additional NAND cells can not reduce the NOR energy much further because most of the NOR energy is burned in their searchlines, which the NAND cels have no control over. 4 Search Line Optimization Techniques E tot (N, k) = ( + k k )E NAND,cell+ 1 k (N k)e NOR,cell (4) D tot (N, k) = k t NAND,cell + (N k) t NOR,cell (5) To validate these models, we computed the EDP for a range of row widths while varying the number of NAND cells per now with results obtained from simulation (Figure 7). It is clear from the the figure that a modest number of NAND cells is the optimum amount, All the techniques we discussd so far tried to reduce ML power, which is only one side of the problem. To avoid a scenario when the SL power dominates the CAM energy consumption, we can consider a precomputation technique that reduces the SL power substantially, and look for ways to improve it [5]. The precomputation technique (Ones-Counter) uses the clever insight that each NOR cell (or even each NAND cell) has two sets of transistors to discharge the matchline, but only one of them is ever on. If each cell had one only searchline, for some misses it would be unable to discharge the matchline because the bit stored on the side with the searchline is 0. This can be fixed 4

5 NOR Array NAND Array Ones Count Figure 8: Hybrid options to integrate NAND-NOR with Ones-Count Search Delay (ns) NOR Array Ones Count NAND Array 0.0 NAND-NOR Ones-Counter Options A & B Option C CAM Type Figure 9: Delay of 64b using hybrid techniques by adding a precomputation stage which guarantees the search term and the rows searched have the same number of ones. If there is a mismatch, there must also be the inverse mismatch somewhere else in the word, so the cell with one searchline is sufficient (Half NOR Cell). By removing a searchline, the cell is smaller, but it also gains in speed and energy efficiency, as shown in Figures 4 and 5. The downside to this approach of course is the area, latency, and energy penalty of the precomputation stage [9]. The precomputation stage is only a CAM of size logarithmic to the Half NOR array that follows. It has the other added benefit of turning off some matchlines for evaluation because of mismatches in the number of ones. For a binary number, the probability distribution for the number of ones is binomial, which will cause a significant number of misses, but not as many as the decaying exponential from NAND cells at the front of the row. To obtain an even more energy efficient CAM, we attempt to mix a NAND-NOR matchline with the ones counter, as shown in Figure 8. There are tradeoffs that could make each design point more or less desirable, but as can be seen in Figures 9 and Figure 10, Option A is never better than the rest. Figures 9 and Figure 10 show the simulation results of a 64b wide CAM array, implemented a variety of ways. For the designs that use NAND cells, they have only 4 as was shown to be optimal for 64b in Figure 7. Compared to Option B, Search Energy (fj/bit) NAND-NOR Ones-Counter Option A Option B Option C CAM Type Figure 10: Energy per bit when implementing 64b using hybrid techniques the NAND cells and the ones counter are in the wrong order. A stage of NAND cells will turn off more match lines that the ones counter, so putting it earlier in the evaluation cycle results in more energy saved. Option C uses more energy by running both comparisons in parallel which also reduces its critical path. Although the hybrids were able to save more energy than the ones-counter, the ones-counter does still have the best EDP of the designs considered. 5 Further Techniques and Considerations In this work, we presented a coherent group of CAM design techniques that we are able to analyze in a fashion that leads to a generally applicable unified technique that optimizes our EDP metric. However, CAM has a wide range of applications, and there are further design considerations and methods that can also result in energy and power improvements for certain design scenarios. One very powerful technique that we found in our literature survey is the segmentation technique [3, 7]. Basically, it tries to optimally divide a large CAM array into smaller arrays that can be operated in a serial or pipelined fashion for improved energy, delay and regular layout. Combining the hybrid NAND-NOR technique with segmentation can be highly advantageous for large CAM sizes. This is an important design aspect that needs to be studied in the future follow up of our study. Another technique is a ML sensing technique called current racing, which we also briefly described in our midterm report[]. This method has slightly faster ML evaluation times than the low swing NOR. It also reduces the SL activity factor by 50% [9], resulting in SL 5

6 power savings. But its design and implementation is a lot more complex than the low swing apporach. It is also highly sensitive to process variations. Due to its design complexity and robustness issues, we decided not to use in our project, and instead implemented the low swing and precomputation method. But the current racing method is also an important method that deserves further attention in future studies on this topic. 6 Conclusion CAMs are used in various important applications, mainly in networking hardware and CPUs, and there are many future applications can benefit from the abilities of CAM memory arrays [6, 8]. But since their significantly more area, power and delay requirements compared to location addressed memories of the same capacity creates a bottleneck in its integration in many applications. In this report, we studied an analytical metric based comparison of major CAM cell techniques we surveyed in our midterm report. We used EDP as a metric to compare the advantage and disadvnateges of each technique. Our study indicates that NAND cell exhibit very low power but long delay operation. To complement this, NOR cells have a very quick evaluation phase, but spend more energy. Using these opposing trends to our advantage, we combined the NAND and NOR cells such that the number of NAND cells in front of the array is optimized to minimize the EDP, while benefiting from the high speed of the forllowing NOR cells, whose high power consumption is harnessed by the reduced activity factor due to the preceding NAND cells. We also noticed that just focusing on ML oriented techniques will create an unbalanced design. Therefore, we investigated a precomputation method, which reduces the number of search lines in the array by half, and further reduces the activity factor of the remaining search lines by 50%. Finally, having these individual methods at our disposal, we combined them in the optimum fashion to obtain minimum EDP. The unique contribution of our study is to combine various CAM design methods in an optimum fashion rather than attacking the problem with a single dimension by the individual methods we found in our survey for the midter report. We believe the ideas presented in this report can enhance CAM performance significantly, enabling its integration into various exciting future applications, especially with the rise of multicore CPU architectures. [] Igor Arsovski, Trevis Chandler, and Ali Sheikholeslami. A ternary content-addressable memory (tcam) based on 4t static storage and including a current-race sensing scheme. JSSC, 38(1): , Mar 003. [3] S Baeg. Low power ternary content-addressable memory (tcam) design using a segmented matchline. IEEE Transactions on Circuits and Systems, 55(6), Jul 008. [4] G Kasai, Y Takarabe, K Furumi, and M Yoneda. 00mhz/00msps 3. w at 1.5 v vdd, 9.4 mbits ternary cam with new charge injection match detect circuits and bank selection scheme. Custom Integrated Circuits Conference, pages , 003. [5] Chi-Sheng Lin, Jui-Chuan Chang, and Bin-Da Liu. A low-power precomputation-based fully parallel content-addressable memory. JSSC, 38(4):654 66, 003. [6] Kun-Jin Lin and Cheng-Wen Wu. A low-power cam design for lz data compression. IEEE Transactions on Computers, 49(10): , 000. [7] K Pagiamtzis and A Sheikholeslami. A low-power content-addressable memory (cam) using pipelined hierarchical search scheme. JSSC, 39(9), Sep 004. [8] K Pagiamtzis and A Sheikholeslami. Using cache to reduce power in content-addressable memories (cams). IEEE Custom Integrated Circuits Conference, 005. [9] K Pagiamtzis and A Sheikholeslami. Contentaddressable memory (cam) circuits and architectures: A tutorial and survey. JSSC, 41(3), Mar 006. [10] Deep Submicron Rules. Mosis scalable cmos (scmos), October [11] J Wang, H Li, C Chen, and C Yeh. An and-type match-line scheme for energy-efficient content addressable memories. ISSCC, Feb 005. [1] Byung-Do Yang and Lee-Sup Kim. A low-power cam using pulsed nand-nor match-line and chargerecycling search-line driver. JSSC, 40(8), Aug 005. References [1] 45nm PTM LP model. Predictive technology model (ptm), September ptm/. 6