Generating TLM Bus Models from Formal Protocol Specification. Tom Michiels CoWare

Transcription

1 Generating TLM Bus Models from Formal Protocol Specification Tom Michiels CoWare

2 Agenda Cycle accurate TLM Requirements Difficulties in creating TLM bus models Generating from formal specification Example & Results

3 Transaction Level Modeling: What Is It? A Higher Level Of Abstraction For Communication MEM BUS RISC RTL: Each device on the bus has a pin-accurate interface Each device interface must implement the bus protocol Periph MEM Periph Clk Req Sel Grnt Addr Data BUS RISC Transaction HREQ HGRANT HADDR TLM: ReqTrf Grant Trf Allow easy modeling, easy assembly Each device communicates via transaction level API Less code, fewer pins, fewer events => much faster AddrTrf HWDATA WriteDataTrf HREADY HRESP EotTrf

4 TLM Requirements: Use Model POV System Architectural Exploration Allow cycle accuracy modeling Analysis and Verification (System-Level) Verify that the assembled system does what is expected Verify architectural decisions Allow cycle accurate mixed abstraction simulations Fast simulation Design and Easy Modeling API should allow implementation flow Do not encode timing in both peripherals and bus Minimize modeling artifacts exposure (like transaction memory management)

5 TLM Requirements: Model POV Fast simulation (100kc/s) API that allows modeling without encoding polling event sensitivity Bus model should not depend on peripherals for correct timing. Bus model should allow accurate mixed abstraction simulation RTL & TLM.

6 What Makes it Hard: Mixed Abstraction Level Simulation MEM RISC Clk Req Sel Grnt Addr Data Periph BUS Transaction Problems with RTL to TLM converter signals Periph Converter? A Functions & events BUS Wait for last delta cycle? TLM even/function call early enough to start driving signals? B

7 What Makes it Hard: Bus Interconnectivity MEM1 RISC DMA BUS Matrix Periph1 BRIDGE SI SI Peripheral BUS OS OS Periph2 Periph3 Periph4 MEM2 Combinatorial paths through bus topologies can be difficult to implement. E.g. no full clock cycle available to do arbitration.

8 What Makes it Hard: Bus Knows Protocol Timing Peripherals can interact with the bus through events and through polling. Initiator is allowed to send a Write Data transfer during this time slot WriteDataTrf GrantTrf AddrTrf ReadDataTrf ReqTrf Transfers WriteDataTrf Initiator Bus Attributes Target The bus synchronizes the transfers with the target according to the timing of the protocol

9 Creating a Bus model at TLM by hand Bus specification 1 Timing diagram Clk Req Sel Grnt Addr Data Bus model Cycle accurate TLM Long and complex development phase Hard to keep a good speed/accuracy trade-off All Validation of model in simulation Accuracy allows study of critical part of a system (bottleneck) SystemC and C++ Expertise needed A TLM user always has to build and maintain a complex modeling infrastructure in order create several bus models,, TLM IPs. Bus model High Level TLM Short and simple development phase High speed but low accuracy Co-simulation with RTL requires long development of complex adatper. Sometimes the adapter cannot even be created.

10 Creating a Bus Model at TLM from Protocol Specification Bus specification 1 Timing diagram Clk Req Sel Grnt Addr Data Bus model User takes care of : Timing Protocol. Tool takes care off: Fast simulation RTL cosim interfacing Computational kernel of bus

11 Example Bus Protocol Specification APB timing (1) include "genprot.bci"; node APB protocol = GPTransaction, bus = { variable setupread, compute = (addrtrf.sent & addrtrf.type == readataddress); variable setupwrite, compute = (addrtrf.sent & addrtrf.type == writeataddress); variable setup, compute = setupread setupwrite; variable enableread, compute = delay (setupread); variable enablewrite, compute = delay (setupwrite); variable enable, compute = enableread enablewrite;

12 Example Bus Protocol Specification APB timing (2) input internodesetupread, type = bool; input internodesetupwrite, type = bool; variable cansendinternodesetupread, compute =!enable &&!internodesetupwrite &&!addrtrf->sent; variable cansendinternodesetupwrite, compute =!enable &&!internodesetupread &&!addrtrf->sent; use addrtrf, configurators = { sendtra receivetra slavedrive masterdrive cansend = setup enable, = setup enable, =!enable, }; CanReceive = delay (setup)

13 Example Bus Protocol Specification APB timing (3) use writedatatrf, configurators = { sendtra receivetra slavedrive masterdrive cansend = setupwrite enablewrite, = setupwrite enablewrite, = setupwrite, }; canreceive = delay (setupwrite) use eottrf, configurators = { sendtra receivetra slavedrive masterdrive cansend = enable, = enable, = enable, }; canreceive = delay (enable)

14 Example Bus Protocol Specification APB timing (4) use ReadDataTrf, configurators = { sendtra receivetra slavedrive masterdrive cansend = enableread, = enableread, = enableread, }; canreceive = delay (enableread) decoder MyDecder, sensitivity = addrtrf.sent, };

15 Results Modeled cycle accurate TLM bus models for AMBA Modeled cycle accurate TLM bus models for proprietary NoC busses for CoWare customers Buffers and Fifo s Switches Split busses Busses programmable through control ports