Integration of Digital Test Tools to the Internet-Based Environment MOSCITO

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1 Integration of Digital Tet Tool to the Internet-Baed Environment MOSCITO Abtract Current paper decribe a new environment MOSCITO for providing acce to tool over the internet. The environment i built according to the mater-lave concept, and it allow to encapulate different EDA tool in order to form variou work flow. In thi paper we dicu integration of two ytem for digital tet into the MOSCITO environment. The firt one i a hierarchical ytem DECIDER, which contain tool for regitertranfer and gate-level circuit including application for VHDL paring, tet generation, tet compaction and tetability analyi. The latter i a ytem Turbo Teter coniting of a wide range of tool for the gate-level tet. The ytem ha tool for fault imulation, multi-valued imulation, ATPG, tet et optimization and built-in elftet. Turbo Teter ha a powerful EDIF interface, allowing to link it to mot of the available commercial EDA ytem. The paper preent the work flow that can be executed over the internet and give the experimental reult for etimating the efficiency of the hierarchical ATPG. 1. Introduction Auring the quality of modern Sytem-on-Chip (SoC) technology i unthinkable without the ue of efficient tet method. In addition to traditional logic level tool for built-in elf-tet, fault imulation, tet generation and optimization, high-level and hierarcical tet application are required. However, not all the needed tet tool may be available for a deigner and intalling a new one would be a an additional overhead. The Internet open a new dimenion, and offer new chance uing tool from different ource. The topic of thi paper i Internet-baed integration of tool and execution of program over the Internet for teting digital circuit. For that purpoe, a novel and very efficient hierarchical ATPG tool called DECIDER wa uccefully integrated into MOSCITO [1] to implement a new Internet-baed environment for digital deign and tet. By thi moment, no commercial ytem for hierarchical tet pattern generation are available on the market. An intereting feature of DECIDER i that it VHDL deign interface allow to convert VHDL decription into deciion diagram model, which provide for a more general repreentation of digital hardware and can be ued for fat imulation and tet pattern generation [3]. In addition, a wide et of diagnotic tool for the logic level tet were made available over the internet. The ytem i called Turbo Teter and it include a powerful EDIF interface, which allow to ue the tool in cooperation with mot of the available commercial EDA ytem. The tool and workflow integrated to the MOSCITO environment are preented in Fig. 1. The paper i organized a follow: The MOSCITO ytem i pecified in Section 2. The tet generation ytem integrated to MOSCITO are preented in Section 3, and experimental reult obtained by ue of the MOSCITO environment are hown in Section MOSCITO Environment 2.1. General Concept of MOSCITO The MOSCITO ytem developed at Fraunhofer IIS/EAS, Dreden, Germany offer a Client- concept. There i one Mater, everal Slave erver and arbitrary number of client. The requeted ervice i provided by Slave erver. That i becaue ocalled were attached to each Slave erver. The encapulate ervice providing work tool (program executable). An can be een a an intelligent wrapper around a tand-alone program, which i capable of communicating with the. All Slave erver are regitered at the Mater, o all (i.e. ervice) are alo regitered at the Mater erver. Uer acce firt the Mater erver and will get a lit of available ervice. After electing a ervice (), the uer i automatically re-directed to the Slave erver, and after that the work with the ervice providing tool can tart. The MOSCITO framework wa implemented in JAVA and can run on different computing platform. The only prerequiite i an intalled Java Virtual Machine. At the moment MOSCITO i ued on SUN worktation (Solari) and on PC (Microoft Window and LINUX).

2 2.2. Software architecture MOSCITO conit of three oftware layer: kernel layer, interface layer, extenion. The kernel provide functionality for baic object and data management, file handling, XML proceing, and communication. Due to the fact that MOSCITO i an open ytem a pecial interface layer provide programming interface for integration of new tool, new workflow and appropriate viewer uch a for diagram, plain text and image. Each interface i repreented by a Java cla which contain the baic functionality. The uer only need to extend thi cla and can implement it own extenion. A large number of template and example implementation help the uer to integrate a new tool or workflow in le than one or two day. Behavioral level VHDL decription High-level VHDL decription Commercial or in-houe CAD oftware 1 High-level 2 Synthei Logic ynthei 3 Schematic entry RTL VHDL decription Gate-level EDIF 6 EDIF-ISCAS converter (TTU) MOSCITO USER 4 VHDL-DD converter 5 EDIF-SSBDD converter ISCAS benchmark High-level DD model SSBDD model ISCAS netlit 7 Hierarchical 8 ATPG Turbo Teter 9 Univerity oftware Functional tet Tet pattern exchange interface Fig. 1. Work flow integrated to the MOSCITO environment Mater Client GUI Slave Slave Internet Fig. 2. Communication between firewall protected MOSCITO ubytem: connection are allowed only between dedicated communication port

3 2.3. Tool encapulation For the integration of tool with MOSCITO a ophiticated agent interface wa introduced. A tool i embedded into a MOSCITO agent for: adapting the input data to the embedded tool, converting the tool-pecific data (imulation reult, logfile, tet vector), mapping the control information to the embedded tool and the tranfer and converion of tatu information to be ubmitted to the uer. For embedding program into a MOSCITO agent there are three way: Integration of the entire program: the oftware ha to be run capable a a batch job. In thi way the integration of a lot of commercial tool i poible. Embedding of a library via the Java Native Interface (JNI): e.g. C, C++ or FORTRAN routine can be embedded. Direct integration of Java-clae and application, repectively, in particular for JAVA oftware. Encapulation of the tool a a MOSCITO agent guarantee a uniform interface to the framework. All tool-pecific detail are aggregated in a pecial agent decription file. Thi file i neceary to create toolpecific dialog for the configuration of the tool via the front-end program. The main emphai in the tool integration wa put on the following iue: Encapulation of deign tool and adaptation of the tool-pecific control and data input/output to the MOSCITO framework Communication between the tool for data exchange to upport ditributed, Internet-baed work. Uniform graphical uer front-end program for the configuration of the tool, the control of the whole workflow and the viualization of reult data. Moreover, an important goal i to provide the functionality of a tool to a potential uer a a ervice in a local area network (LAN). Thi approach i imilar to the Application Service Provider (ASP) idea or the recent approach of Web Service Communication The implementation of the tool communication i baed on TCP/IP-ocket. The tool can be executed on different computer or on different computing platform (e.g. UNIX, Window). All we need for communication i a LAN or Internet acce. To minimize the implementation effort for parer, tranlator and converter, the format for all data tranmitted in MOSCITO wa et to a pecial XML format, the Mocito Markup Language (MocitoML) Graphical Uer Interface (GUI) To offer a uniform and conitent concept for the uer interaction the MOSCITO ytem ha been provided with a graphical front-end with the following functionality: The problem decription including all data can be read in from a MOSCITO project file. Workflow can be choen from a et of predefined flow for the pecific problem. A brower upport the choice of agent (tool) needed for the olution of the problem from the et of available ervice. With button for tart, paue, reume and top the workflow can be controlled by the uer. A conole window collect all meage from the running tool and allow the obervation of the proper operation or trouble hooting, repectively. The viualization module MOSCITO Scope upport the diplay of all reult data (tet vector, tatitic information). The graphical front-end aim at uing deign tool via the Internet in a imple and efficient manner. Actually, the front-end i available a a JAVA application and ha to be intalled together with the MOSCITO oftware Internet-baed uage At firt, it i neceary to tart one MOSCITO erver on each hot belonging to a domain of ervice. After that an adminitrator ha to regiter one or more MOSCITO agent o that they are available a remote ervice via LAN or Internet. Now a uer can tart the MOSCITO front-end program (GUI) and can browe through regitered agent, can elect, configure, and initialize the appropriated workflow and the needed agent. MOSCITO automatically call remote tool and etablihe direct connection between the tool for data tranfer. Furthermore, the GUI allow the uer to control and oberve the data proceing provided by a certain workflow. Reult data are tranmitted to the front-end and diplayed by appropriate viewer. Finally MOSCITO cloe the connection between all remote tool and organize correct termination of them Working with firewall protection can be regarded a filter which allow certain type of communication (e.g. TCP/IP protocol baed) go through certain configurable chock point (called port) [13]. i implemented for example a a pecialized oftware running on a well ecured computer. ha it filter rule. Internet i acceible only via that computer and vice vera- any computer in i acceible only via that computer (through firewall). While peaking about opening a port in a firewall, then

4 uually i ment that firewall filtering rule are configured appropriately. At firt, MOSCITO wa not intended to be ued acro firewall protected ytem. Therefore, it randomly ued the non-retricted communication port above The problem nowerday i that that many other network application alo ue thee o-called free port. There i no harm in internal network generally, but there will be ecurity problem when uch program are directly expoed to internet. The reaon i that ome of them are known to be vulnerable, i.e. they can be miued to attack the hot computer they are running on. Tolerating one of uch vulnerable program will compromie the hot computer and alo finally entire network. Conequently, in a retrictive firewall protected ytem there are only few port left open for incoming internet connection (like port 80 for http web erver). In the cae of retrictive firewall uch MOSCITO olution would not work, becaue firewall block all the communication. In order to comply with firewall requirement, the major MOSCITO communication cheme wa modified. Simplified communication chema for MOSCITO in a firewall protected environment i hown in Fig. 2. Direct connection between ubcomponent are not allowed. All the communication ha to be organized through predetermined communication port. Random port number are alo not allowed. All the traffic goe only through firewall port. Client GUI Proxy Proxy Slave Fig. 3. Communication between client and agent via proxy One poible olution for olving the firewall traveral problem i to implement MOSCITO proxy a Java application (Fig.3). Here we relay on uual MOSCITO ocket baed communication (TCP/IP ocket). By default only ome vital port for computer ytem are configured to be open while all the ret are blocked. Thi mean it i neceary to open up at leat one dedicated port in a firewall for MOSCITO communication need. Proxy mechanim (Authenticated Traveral) enable hot in one ide of proxy erver to gain full acce to hot in the other ide of the proxy erver without requiring direct IP reachability. It work by redirecting connection requet from hot in one ide to hot in the other ide to a proxy erver, who authenticate and authorize the requet, etablihe a proxy connection and pae data back and forth Tool environment In order to validate the MOSCITO ytem and to collect experience while uing it for real-life application an experimental tool environment for deign and tet pattern generation (Fig.1) wa developed and mapped to a MOSCITO workflow. In the following Section the functionality of the tool will be explained in detail. Deign information can be generated in different way, by VHDL file to be proceed by commercial or experimental high-level or logic ynthei ytem, or provided manually by chematic editor. The gate-level deign i preented in the EDIF format. In the univerity reearch practice, ISCAS benchmark familie with a dedicated ISCAS format are widely ued. For linking tet generation and fault imulation tool with all the needed format, different tranlator and interface were developed (Block 4,5,6 in Fig.1). The interface make poible to deign a circuit in one geographical ite, generate tet pattern in another ite, and to analyze the quality of pattern in a third ite. The following tool have been integrated in MOSCITO: High-level ynthei (1) with RTL output [2] Interface from RTL VHDL (4) to ATPG Interface from EDIF (5) and ISCAS (6) format to ATPG and fault imulator Hierarchical ATPG (7) DECIDER [3] Logic level ATPG (8) Turbo-Teter [4]. The lited tool can act a MOSCITO agent and each of them provide a demanded ervice. The uer are empowered to combine all the ervice to a problem-pecific workflow. That mean, the needed tool have not to be intalled on the uer local computer. Due to that fact the uer effort for intallation, configuration and maintenance of oftware will be dratically reduced. RTL Deign Tetability Analyi Logic Synthei (3-rd party) Tetability value Gate-level Deign Hierarchical ATPG DECIDER Tet Turbo Teter Toolet Sequential Tet Set Compaction Fig.4. Deign flow of the hierarchical ATPG ytem

5 3. Tet Generation Sytem 3.1. Hierarchical ATPG DECIDER The hierarchical ATPG (block7 in Fig.1) ue a top-down approach, with a novel method of combining random and determinitic technique. Tet are generated for each Functional Unit (FU) of the ytem eparately. Firt, a high-level ymbolic tet frame (tet plan) for teting the given FU i created by implementing determinitic earch. The earch i guided by the tetability meaure calculated by a tetability analyzer. A the reult of the earch proce, a ymbolic path (a tet frame) for propagating fault through the network of component i activated and correponding contraint are extracted. The tet frame will adopt the role of a filter between the random TPG and the FU under tet. If the filter doe not allow to find a random tet with 100% fault coverage for the component under tet, another tet frame will be choen or generated in addition to the previouly created one. In uch a way, the following main part in the ATPG are ued alternatively: determinitic high-level tet frame generator, random low-level tet generator, highlevel imulator for tranporting random pattern to the component under tet and low-level fault imulator for etimating the quality of random pattern. The general tructure of the hierarchical ATPG ytem i hown in Fig. 4. In addition to the tet pattern generator it contain tool for tetability analyi and tet et compaction. Deign interface from VHDL and EDIF are available (not hown in the Figure) Logic-Level ATPG Sytem Turbo Teter The Turbo Teter (TT) ATPG oftware (Block 8 in Fig.1) conit of a et of tool (Fig.5) for olving different tet related tak at the gate-level by implementing the following method and algorithm: tet pattern generation by determinitic, random and genetic algorithm tet optimization (tet compaction) fault imulation for combinational and equential circuit defect-oriented fault imulation and tet generation multi-valued imulation for detecting hazard and analyzing dynamic behaviour of circuit tetability analyi and fault diagnoi. The tet generation and fault imulation tool of TT are ued a the back-end for the hierarchical ATPG decribed in Section 3.1. All the TT tool operate on the model of Structurally Syntheized Binary Deciion Diagram (SSBDD) [9]. The tool run on the tructural logic level. Two poibilitie are available - gate-level and macro-level. In the latter, the gate network i tranformed into macro network where each macro repreent a tree-like ubnetwork. Uing the macro-level help to reduce the complexity of the model and to improve the performance of tool. The fault model in the Turbo Teter i the traditional tuck-at model. However, the fault imulator and tet generator can be run alo in the defect-oriented mode, where defect in the library component can be taken into account. In thi cae, additional input information about defect in the form of defect table for the library component i needed. Level: Gate Macro Deign Method: BILBO CSTP Store/Generate Tet Generation BIST Simulation Fig.5. A et of low-level ATPG tool Turbo-Teter 4. Experiment Method: Determinitic Random Genetic Tet Tet Optimization model: Stuck-at-fault Stuck-open Delay fault Simulation Table Method: Single fault Parallel Deductive Location Diagnoi An experimental cae tudy ha been uccefully carried out on Internet-baed teting of a digital deign for Rotation Detection developed at the Fraunhofer IIS/EAS, Germany. In the following, the performance of the hierarchical ATPG i compared to tate-of-the-art commercial and univerity tool. The main characteritic of the benchmark ued in the comparion are preented in Table 1. Table 1: Characteritic of the benchmark circuit circuit # of gate # of fault PI bit PO bit gcd mult8x ric_ diffeq Table 2 how the comparion of the hierarchical ATPG and a commercial ATPG on the four above example. A the experiment howed, the ATPG integrated to MOSCITO i coniderably fater than the commercial tool, obtaining higher fault coverage for the larger deign while loing omewhat coverage for the maller one. All the experiment were run on a 300 MHz SUN UltraSPARC 10 worktation with 128 MB RAM under SOLARIS 2.6 operating ytem. The performance of the hierarchical ATPG wa alo compared againt the exiting univerity tool GATEST [10] and HITEC [11]. The reult of comparion of different ATPG are given in Table 3. Actual tuck-at fault coverage of the tet pattern generated by all the three tool were meaured by the fault imulator of Turbo Teter.

6 Table 2: Comparion of the hierarchical tet pattern generation ytem and a commercial ATPG Commercial ATPG DECIDER circuit detected time, tet length fault detected time, tet length gcd mult8x ric diffeq Table 3. Tet generation performance comparion with univerity tool DECIDER GATEST HITEC Time cover Time cover % % cover % Time GCD mult 8x diffeq N.A. Finally, the combinational ATPG integrated to the MOSCITO environment, which implement an improved PODEM algorithm wa evaluated on a real deign example of a Modified Dicrete Coine Tranform (MDCT) core. The tool achieved % fault coverage for the 50 kgate core after one minute of tet generation. The tate-of-the-art commercial ATPG pent one minute while reaching 100 %. 5. Concluion In the paper an Internet-baed environment for digital tet upported by MOSCITO ytem [12] i preented. The environment i focued on providing high-level and logic level deign flow with tetability analyi, tet pattern generation and fault imulation. The paper decribe the work flow that can be executed over the Internet and give the experimental reult for etimating the efficiency of the hierarchical ATPG. The ytem provide interface and link to commercial deign environment and alo to other univerity tool. The functionality of the integrated deign and tet ytem wa verified by everal benchmark circuit and by different deign and tet flow. Furthermore, author believe that the MOSCITO architecture i powerful enough to olve imilar problem in other application area of automated ytem deign. Future work will continue in thi direction. Reference [1] A.Schneider et. al Internet-baed Collaborative Tet Generation with MOSCITO. Proc. of DATE 02, Pari, France, March 4-8, 2002, pp [2] G.Jervan, P.Ele, Z.Peng, J.Raik, R.Ubar. High-Level Tet Synthei with Hierarchical Tet Generation. 17th NORCHIP Conf., Olo, Nov. 8-9, 1999, pp [3] J.Raik, R.Ubar: Fat Tet Pattern Generation for Sequential Circuit Uing DD Repreentation. J. of Electronic Teting: Theory and Application. Kluwer Acad. Publiher. Vol. 16, No. 3, pp , [4] J.Raik, R. Ubar: Feaibility of Structurally Syntheized BDD Model for Tet Generation. Proc. of the ETW, Barcelona (Spain), May 27-29, 1998, pp [5] M.L.Buhnell, V.D.Agrawal. Eential of Electronic Teting. Kluwer Academic Publiher, [6] Goldtein L.H. Controllability/obervability analyi of digital circuit. IEEE Tran. Circuit. Syt., CAS-26, No.9, 1979, pp [7] Gu X., Kuchcinki K., Peng Z. Tetability Analyi and Improvement from VHDL Behavioral Specification. Proc. EURO-DAC, [8] Ubar R. Tet Synthei with alternative graph. IEEE Deign & Tet of Computer. Spring 1996, pp [9] Ubar R. Multi-Valued Simulation of Digital Circuit with Structurally Syntheized BDD. OPA N.V. Gordon & Breach Publ, Multiple Valued Logic, Vol.4, pp , [10] E.M.Rudnick, J.Patel, G.S.Greentein, T.M.Niermann: Sequential Circuit Tet Generation in a Genetic Algorithm framework. DAC., pp , [11] M.Niermann, J.H.Patel: HITEC: A Tet Generation Package for Sequential Circuit. European Conf. Deign Automation, pp , [12] MOSCITO: