Automated system partitioning based on hypergraphs for 3D stacked integrated circuits. FOSDEM 2018 Quentin Delhaye
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1 Automated system partitioning based on hypergraphs for 3D stacked integrated circuits FOSDEM 2018 Quentin Delhaye
2 Integrated circuits: Let s go 3D
3 Building an Integrated Circuit (IC) Transistors to build gates 3
4 Building an Integrated Circuit (IC) Transistors to build gates Gates to build logic functions 4
5 Building an Integrated Circuit (IC) Transistors to build gates Gates to build logic functions Logic functions build ICs 5
6 Building an Integrated Circuit (IC) Transistors to build gates Gates to build logic functions Logic functions build ICs 6
7 Building an Integrated Circuit (IC) Transistors to build gates Gates to build logic functions Logic functions build ICs System performance depends on transistor performance and the quality of the system interconnect 7
8 What does a 2D IC look like? Metal Gate Substrate Planar 2D IC: only one transistor layer 8
9 What are its limitations? Fin pitch Standard cell Metal layers Metal pitch If you want more of them, you need them smaller. Gate pitch But scaling has physical and financial limitations. 9
10 You can t simply make it bigger Good die Bad die Constant amount of defects per wafer Larger IC means lower yield 10
11 Split the IC to keep it small Xilinx split its latest node to keep it relatively affordable. FPGA FPGA FPGA FPGA FPIC FPIC FPIC 11
12 What is a 3D IC? 12
13 What is a 3D IC? 13
14 What is a 3D IC? 14
15 What is a 3D IC? Face-to-Back (past) 15
16 What is a 3D IC? Face-to-Back (past) Face-to-Face (present) 16
17 What is a 3D IC? Face-to-Back (past) Face-to-Face (present) Transistor-on-transistor (future) 17
18 What is a 3D IC? Face-to-Back (past) Face-to-Face (present) Transistor-on-transistor (future) Somebody needs to decide what goes where 18
19 3D benefit: shorter connections Increased performance Decreased system power consumption Improved area utilisation 19
20 2D flow... Hardware description: Verilog, VHDL,... 20
21 2D flow... Synthesis: Yosys, ODIN-II, ABC,... Yields a netlist. 21
22 2D flow... Place and route (P&R): QRouter, Graywolf, FGR,... 22
23 ... Extended to 3D Pick which standard cell or module goes where 23
24 This is not a design. 24
25 Bipartition this system Objectives: Area balance Limit 3D interconnectivity 25
26 Clustering: hide the shortest nets Big clusters: Few nets Long nets hidden 26
27 Clustering: hide the shortest nets Small clusters: Lots of nets Long nets apparent 27
28 Graph extraction Clusters become vertices 28
29 Graph extraction Interconnections become edges 29
30 Graph extraction Extraction complete 30
31 Graph extraction Single nets are split into different edges 31
32 From graph to hypergraph 32
33 Graph extraction Single nets are split into different edges 33
34 Graph extraction Hyperedges maintain their integrity 34
35 Hypergraph extraction 35
36 Partitioning Minimize the crossing nets and maintain area balance 36
37 Split the netlist Die 1 module die1(); module die2(); Die 2 37
38 Replace the manual partitioning 38
39 Automated 3D flow 39
40 Automated 3D flow Export design properties Design clustering Export clusters connectivity 40
41 Automated 3D flow From the clustering outputs Build hyperedges and merge identical ones Compute graph weights Format graph and call partitioning tool Export cut data and partition directives 41
42 Automated 3D flow hmetis Karypis Lab, University of Minesota PaToH Ümit Catalyürek, Bilkent University 42
43 Automated 3D flow Early development stage Based on 2D netlist and partitioning directives 43
44 Designs tested LDPC RISC V (BoomCore) OpenSparc T2: SPC, CCX and RTX 44
45 3D: up to 77% less total wire length Experiments using different functional blocks from OpenSPARC T2 SoC Different partitioning schemes Different clustering options 45
46 3D: Up to 61% shorter critical path Experiments using different functional blocks from OpenSPARC T2 SoC Different partitioning schemes Different clustering options 46
47 Open questions What is the best clustering? Does the clustering method have a significant impact? Can we predict the partitionability of a design? Links: 47
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