Minje Jun. Eui-Young Chung

Transcription

1 Mixed Integer Linear Programming-based g Optimal Topology Synthesis of Cascaded Crossbar Switches Minje Jun Sungjoo Yoo Eui-Young Chung

2 Contents Motivation Related Works Overview of the Method Problem Definition Constraints and Formulations Experiment Conclusion

3 Motivation On-chip Interconnection Methodology Shifting Shared bus Hierarchical bus or Bus matrix Switch-based design Crossbar Switch Sufferings against Its Size Increase in logic delay Control blocks (decoder, arbiter, etc) grow Results in lower speed Worse then linear increase in silicon area Quadratic increase of # of bus lines

4 Motivation Maximum Area of Crossbar Freq. of Swtich Crossbar agaist Swtich Its Size agaist Its Size Frequency Area (m (M Mhz) m 2 ) number number of of slave slave ports ports number of master ports number of master ports Synthesis result of RTL code from AMBA Designer with Samsung 90nm process technology

5 Motivation M0 S0 M0 M1 S0 M1 S2 S1 M3 M2 S2 S5 M3 M2 S3 S6 M4 M4 S4 S7 M6 M5 S1 S3 S5 M7 M6 M5 S4 S6 M7 S7 Proposed Conventional Cascaded Single Crossbar Switch Backbone Network Bus Can achieve faster speed Can achieve area reduction

6 Related Works Does it need to be fully connected? S.Murali et al. and S.Pasricha et al. presented synthesis of partially connected bus matrix [1-3] Limitation on modularity and scalability Can t it be shared by multiple masters/slaves? S.Murali et al. presented clustering method to minimize the central crossbar switch [4] An extereme case of our work

7 Related Works How about in NoC area? K.Srinivasan et al. presented irregular topology synthesis method using fixed size routers [5] J Yoo et al first presented cascaded crossbar J.Yoo et al. first presented cascaded crossbar switch, based on simulated annealing method [6] Does not targetting optimality

8 Overview of the Synthesis Process Communication Requirement of Target System Library Physical Characteristics of Crossbar Switch (frequency, area) Proposed Synthesis Flow Optimal Cascaded Crossbar Switch Topology

9 Problem Definition Communication Requirement Graph CRG G(V M,V S,E) v m V M : master node v s V S : slave node e m,s E : edge between v m and v s w(e m,s ) : BW requirement of e m,s d(e m,s ) : latency constraint of e m,s Crossbar Switch Physical Characteristics A m,s : area of m xs crossbar switch F m,s : maximum freq. of m xs crossbar switch

10 Problem Definition Cascaded Crossbar Topology T(MX,SX,XX) MX mx m,x : 1 iff master v m is connected to crossbar x SX s,x : 1 iff slave v s is connected to crossbar x XX x,x : 1 iff crossbar x is connected to crossbar x Our problem is to find T(MX,SX,XX) which optimizes the design

11 Assumptions Single clock frequency and data width Bridges for freq. and/or data width conversion already included in IP interfaces Single path routing Each e m,s in CRG is accommodated by a single path Productized switch modules [7-8] remain unchanged Still, a master-slave pair can communicate with multiple path by using multiple ports

12 Topology Feasibility Constraint A master or slave must be connected to one and only one crossbar switch A crossbar switch must be not used : or larger than 1x2 or 2x1 :

13 Single Communication Path Constraint Depth-n path matrix D n m,x1,x2, xn,s 1 iff master v m is connected to slave v s through m s g x 1,x 2,,x n-1, and x n

14 Single Communication Path Constraint For a master-slave pair with w(e m,s ) >0, there must exist a communication path When latency constraint exists, d(e m,s )=k

15 Bandwidth Constraint x 1 x 2 m 1 s 1 m 2 s 2 m 3 x 3 x 4 x 5 s 3 m 4 s 4 depth 2 path depth 3 path Link between x 1 and x 2 is loaded by depth-2 connection (m 1 -s 1 ) by depth-3 connection (m 2 -s 2 )

16 Bandwidth Constraint Total weight bewteen x 1 and x 2 in above example general expression Bandwidth Constraint crossbar network frequency channel width of the switches

17 Table Referencing with MILP Variables Freq. / Area of crossbar x F PS A PMx,PSx / PMx,PSx PS / Cannot be directly obtained!! Obtain indexing i matrix K x,m,s 1 iff crossbar x is m xs, otherwise 0 integer part less than 1 by β always less than 1 by α, thus fractional part K x,m,s is 0 if inside the brace is negative positive K x,m,s can and must be 1 if inside the brace is 0

18 Experiemt Setting Applications App I : Industrial strength SoC (12x4) App II : Mpeg4 decoder example (9x3) [9] Objectives Frequency maximization w/o area upper bound Frequency maximuzation w/ area upper bound (30%) Area minimization w/o freq. lower bound Area minimization w/ freq. lower bound (380Mhz)

19 Result for App I Freq. improvement is up to 37.3%, 3% but with 43.6% area overhead (Objective I) Area reduction is up to 12.7%, and with 21.9% freq. improvement (objective III) Improvement (% %) Obj I Obj II Obj III Obj IV 20 Freq. maximization Area minimization Freq. Area

20 Result for App I m2 m3 m10 m12 m4 m5 m7 m m1 m6 m8 s2 s3 s4 s1 m4 m6 m8 m11 m3 m7 m10 m12 m5 m1 m m s3 s2 s1 s4 m9 m6 m2 m3 m6 m8 m9 m10 m11 m12 m1 m4 m5 m7 s s1 s3 s4 m2 m3 m4 m10 m12 m7 m8 m9 m11 s2 m m s1 s3 s4

21 Result for App II Freq. improvement is up to 22.9%, but with area overhead of 68.4% (Objective I) For area minimization, the single crossbar is the best solution Freq. lower bound 380Mhz achieved with only 4% area overhead Improvement (% %) I Obj I Obj II Obj III Obj IV Freq. maximization Area minimization Freq. Area

22 Result for App II idct risc cpu mem2 bab upsp cpu rast vu au dsp mem2 mem3 mem1 rast dsp idct risc bab upsp vu 942 au mem3 mem1 vu au cpu rast idct risc bab upsp dsp mem1 mem2 mem3 idct risc bab upsp dsp mem vu au cpu rast mem1 mem2

23 Conclusion We proposed cascaded crossbar switch network using arbitrary sized crossbar switches MILP-based exact topology synthesis method Experimental result shows up to 37.3% (12.7%) freq. (area) improvement synthesis time : 15.7 hours (App I) /0.36 hours (App II) on average Future Work Time-efficient heuristic algorithm Adding bbjective for power consumption

24 Thank You

25 References [1] S. Murali and G. De Micheli, "An Application-Specific Design Methodology for STbus Crossbar Generation", DATE 2005, pp [2] S. Pasricha, N. Dutt, M. Ben-Romdhane, "Constraint-Driven Bus Matrix Synthesis for MPSoC", ASPDAC 2006, pp [3] S. Pasricha, N. Dutt, COSMECA: application specific co-synthesis of memory and communicat ion architectures for MPSoC, DATE 2006, pp [4] S. Murali, L. Benini, and G. De Micheli, "An Application- Specific Design Methodology for On-C hip Crossbar Generation", Trans. VLSI (to appear), available at [5] K. Srinivasan, K. S. Chatha, and G. Konjevod, "Linear Programming Based Technique for Synth esis of Network-on- on Chip Architectures", es" IEEE TVLSI, April 2006, vol. 14, pp [6] J. Yoo, S. Yoo, and K. Choi, "Communication Architecture Synthesis of Cascaded Bus Matrix", ASPDAC 2007, pp [7] ARM, [8] Sonics Inc., [9] K. Srinivasan, K. S. Chatha, A low complexity heuristic for design of custom network-on-chip a rchitectures, DATE 2006, pp