SONICS, INC. Sonics SOC Integration Architecture. Drew Wingard. (Systems-ON-ICS)
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1 Sonics SOC Integration Architecture Drew Wingard 2440 West El Camino Real, Suite 620 Mountain View, California Fax (Systems-ON-ICS)
2 Overview 10 Background 10 Architecture Overview 10 Implementation 10 Summary P1500 Presentation 99/1/28 2
3 SOC Applications and Data Flow APPLICATION AREA DIGITAL CAMERA COLOR PRINTERS NEXT GENERATION STB NETWORK SWITCHING SOHO MULTIMEDIA XDSL INTERFACE DIGITAL TELEVISION DIGITAL VIDEO SERVER WORLD PHONE SOC Data Flow DMA CPU DSP A C MEM I O O P1500 Presentation 99/1/28 3
4 System-on-a-Chip Communications Characteristics: 10 Wide performance range 10 Increasing real-time multimedia/networking traffic 10 Shared memory requirements 10 Complex interactions Challenging Design IP Core Communications Bandwidth Performance- Driven Real-Time Video/2D P1394 LAN DSP ATM CPU PCI 3D 4M 16M 64M 256M 1G 4G 16G 64G 256G Bandwidth (bits/sec) P1500 Presentation 99/1/28 4
5 Conventional Approach DMA CPU DSP A Bridge B C I O O SOC Design Requirements 10 New design for each system 10 Match system design cycle System SOC Design Time 10 Hit cost/performance goals P1500 Presentation 99/1/28 5
6 Sonics Integration Architecture (SonicsIA) Highly configurable communication structure with tools that simplify making complex & high performance IP blocks successfully inter-operate in an SOC. Value Proposition SonicsIA cuts design time by 50% SonicsIA increases value (productivity) of resources (people, IP, tools) P1500 Presentation 99/1/28 6
7 Comparison Conventional DMA CPU DSP A Bridge System Bus DMA Sonics Integration Architecture CPU DSP Sonics Silicon Backplane A B Peripheral Bus C I O O Sonics Module Interface Custom Interfaces Allows unification of all on-chip communication C B I O O P1500 Presentation 99/1/28 7
8 SonicsIA Aspects* DMA CPU DSP A 10 Tunable Communications Subsystems Silicon Backplane TM C MEM I O Silicon Backplane Sonics Module Interface Initiator Module Target Module Logic Backplane Bridge Logic Backplane TM 10 Configurable IP Core Interface Sonics Module Interface 10 Design Software SonicsIA Compilers SonicsIA Workbenches * Patent Pending P1500 Presentation 99/1/28 8
9 Bus Bandwidth Requirements 10 Must satisfy sum of sustained BW SOC Data Flow 10 Total bus BW > peak BW of any IP Core DMA CPU DSP A Bandwidth mismatch between Bus and IP Cores Need de-coupled Bus performance C MEM I O O < 10 Mbits/sec < 100 Mbits/sec > 100 Mbits/sec P1500 Presentation 99/1/28 9
10 Computer Bus Approach IP Core IP Core Transmit FIFO Data Arbiter Computer Bus Time Address Receive FIFO IP Core IP Core P1500 Presentation 99/1/28 10
11 Communication Bus Approach IP Core IP Core Transmit FIFO Data TDMA Communications Bus Time Receive FIFO TDMA IP Core IP Core P1500 Presentation 99/1/28 11
12 Integration Architecture Features From Computing 10 Address-based Selection 10 Write and Read Transfers 10 Pipelining From Communications 10 Efficient BW De-coupling 10 Guaranteed BW & Latency 10 Side-band Signaling Integration Architecture DMA CPU DSP A C MEM I O P1500 Presentation 99/1/28 12
13 Guaranteed Bandwidth Arbitration 10 Independent arbitration for every cycle 10 Two phases Distributed TDMA Round robin Gives SOC designer fine control over system bandwidth Current Slot Arbitration Command P1500 Presentation 99/1/28 13
14 Guaranteed Latency 10 Fixed latency between command/address and data/response phases 10 Matches pipelined CPU model High performance access to on-chip resources 10 Allows routing of pipelined data through Backplane 10 Latency is re-programmable in software 10 Variable-latency IP Cores do not tieupthe Backplane P1500 Presentation 99/1/28 14
15 Memory-Mapped Address Space 10 IP Cores accessed only via Read / Write commands 10 Interface Modules decode addresses for IP Core selection 10 Interface Module address match logic features: Variable match width Multiple match regions Positive / Negative decoding Subtractive decoding 10 Module Configuration Registers Access re-programmable / hardwired Backplane features IP Core device control registers P1500 Presentation 99/1/28 15
16 Pipeline Diagram Cycle Arbitration Command WR WR Address A1 A2 Data D1 D2 Response P1500 Presentation 99/1/28 16
17 Integrated Signaling Mechanism 10 Dedicated Backplane wires (Flags) support: Bus-style Out-of-Band Signaling (Interrupts) Point-to-Point Communications (Flow control) Dynamic point-to-point (Retry mechanism) 10 Integral part of Integration Architecture Same design flow, timing, flexibility as address/data part P1500 Presentation 99/1/28 17
18 Off-Chip Extension: Logic Backplane Silicon Backplane CPU-Based ASSP PLD Logic Backplane ASSP P1500 Presentation 99/1/28 18
19 Target Module Block Diagram Silicon Backplane Interface C L O C K Address/Data Flow Address Decoder Configuration Registers Clock Address / Control Data Synchronizer (Optional) Sonics Module Interface P1500 Presentation 99/1/28 19
20 Sonics Module Interface: Basics Signal Driver Width Comments Clock Any 1 Driven by Master, Slave, or other Cmd Master 3 Idle, Read, Write + extensions Addr Master Varies Req. Address; VC specs width DataOut Master Varies Write Data; VC specs width ReqAccept Slave 1 Slave accepts request Resp Slave 3 Response to prior request DataIn Slave Varies Read Data; valid based on Resp RespAccept Master 1 Master accepts response Simple Synchronous Read/Write Protocol with Variable Widths and Flow Control P1500 Presentation 99/1/28 20
21 VSIA Correspondence Virtual Component Interface VSIA On-chip Bus Model Virtual Component Transaction Protocol Bus Transfer Protocol Physical Bus Sonics Integration Architecture Sonics Module Interface Silicon Backplane Protocol Physical Bus P1500 Presentation 99/1/28 21
22 Bandwidth Engineering Define System Specifications Analyze Performance Partition System System Bandwidth & Latency Constraints Select / Design IP Cores IP Core Requirements SonicsIA Compilers IP Cores Silicon Backplane Simulate / Integrate SOC P1500 Presentation 99/1/28 22
23 Validation / Test 10 Silicon Backplane is highly visible for test All subsystems communicate through Backplane 10 Test Interfaces: Logic Backplane: 100 s MB/s Snooping Module: Scan-based 10 Each subsystem can be tested/validated stand-alone Test Vectors Logic Backplane Test Vectors P1500 Presentation 99/1/28 23
24 Silicon Backplane Performance Roadmap 5000 Silicon Backplane Bandwidth Range MBytes per second Version Hard Firm Soft µm 0.25µm 0.18µm Soft and Firm versions should satisfy 90% of SOC applications P1500 Presentation 99/1/28 24
25 Summary DMA CPU DSP A B Bridge System Bus DMA CPU DSP Sonics Silicon Backplane Peripheral Bus C I O O Sonics Module Interface Custom Interfaces A C B I O O SonicsIA Benefits 10 Simplified Design 10 Guaranteed Performance 10 Reduced Iteration Cost 10 Higher IP Library Value 10 Increased Flexibility On Time! On Spec! On Budget! P1500 Presentation 99/1/28 25
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