Round-Robin Arbiter Based on Index for NoC Routers

Transcription

1 Round-Robin Arbiter Based on Index for NoC Routers Vishwaradhya B Yadrami, Jeeru Dinish Reddy Dept. of ECE, BMS College of Engineering, Bengaluru, India yadramivishwa@gmail.com, dineshreddy.ece@bmsce.ac.in Abstract: In the era of digital, scalable on-chip communication like network on chip is needed to meet the communication of large number of on-chip cores. In the micro architecture-design of NoC router s, arbiter design has significant impact on performance and efficiency of NoC systems. The proposed paper round robin arbiter scheme based on index, that functions on index format that is, logarithmically(log 2 )with number of input ports as compared to the conventional round robin arbiter. The architecture of our design leads to lower power consumption as well as higher characterstics of performance. Keywords: Micro-Architecture, Arbiter Design, Index Variance, Network On Chip. I. INTRODUCTION In the digital design systems, communication on the chip,plays an important role,where the resources need to be allocated and shared across various node or regions of the chip. Whenever a resource like, buffer a switch-port or a channel is need to be shared. An arbiter is required to assign the resource to a particular place at particular time. Shared-bus arbitration use the scheme of arbiter,where multiple master module initiate their transactions. the modules needs to be arbitrated for bus to access before any transaction. In this paper,we investigate on arbiters used in NoC systems. For various cores on chip of SoC, the communication is facilitated through an NoC systems. SoC includes a network of switches(routers) that are interconnected by communication links. The typical NoC router consisting of input and output ports an arbiter and a crossbar switch is shown in Figure 1.a, Figure 1.b. [2]. The data paths of routers are made up of buffers and switches. The control parts of routers are largely com osed of arbiters and allocators. Allocators are nothing but used to allocate virtual channels to packets and to allocate switch cycles to flits. Arbiters, which resolves multiple request for the single resource, they form the fundamental block for the allocaters that match mutliple requests with mutilple resources. To grant the resource at a time, arbiter is required. whenever their are resources such as buffer, channel, or crossbar switch ports is shared by many agents, an. Use of virtual channel(vc) mechanism, makes the arbiter s structure more complex. A key property of an arbiter is its fairness. A fair, arbiter is one that provides equal service to the different request s. The exact meaning of equal,can vary from application to application. The usefull definations of fairness are: Weak fairness : Every request is eventually served, Strong fairness: Requests will be served equally offen. FIFO fairness: Requesters are serviced in the order they made their requests. Arbiters are grouped in terms of two fixed and variable architectures, which depends on priority. Request s priorities are to be established in a linear order for fixed priority arbiters. Consider a bit cell of figure 2.a. accepts one request input ri, and one carry input ci, and generates a output grant gi, and a output carry c i+1. Figure 2 (a) illustrates a bit cell of fixed priority arbiter. The ci bit indicates that the highest priority request has not granted the request and hence, is available for this bit cell. If the current request is true and the carry is true, the grant line us asserted and the carry output is disserted, signalling that the resource has been granted and is no longer available. We can express this logic in equation form as: g i = r i & c i. c i + 1 = ( ~r i & c i ). Figure 2.(b) shows the four-bit fixed priority arbiter constructed in this above manner by using iterative cells of figure.2 (a).the first and the last cells, however,have been simplified. The first bit cell takes the advantage of the fact that c 0 is always 1.While the the last bit cell takes the advantage of the fact that there is no need to generate c 4. At first glance, it appears that the delay of an iterative arbiter must be linear in the number of inputs. Indeed, if they are constructed as shown in figure.2.(b),then that case,since in the worst case the carry must be propagate from one end of the arbiter to the other. However, we can build these arbiters to operate in time that grows logarithmically with the number of inputs by employing carry lookahead type techniques. However above mentioned arbiter is completely unfair and not useful in practice. It is not even fair in the weak sense. None of the other request will ever be resourced, when requests r0 is continuously raised. A fair arbiter is designed by changing the priority from cycle to cycle, as illustrated in figure 7.To select the request of highest priority, it s corresponding priority signal is asserted, by setting One bit, i.e. p is set. From that request point cyclically around the circular carry chain the corresponding bits of request priority decreases. The logic equations for this arbiter are: 194

2 g i = r i & ( c I p i ). c i + 1 = ( ~r i & ( c I p i ). c 0 = c n. Consider the case, while all other request inputs remain low and where two adjacent inputs r i and r i+1 repeatedly request the service from n-input arbiter. Request r i wins the arbitration only when p i is true while r i+1 will win the arbitration n times as often as r i. This unfairness can be overcome by using a round robin arbiter. Figure 1. (a) SoC Mesh in 2D. (b)noc Router for Wormhole II. PREVIOUS WORKS The authors W. J. Dally and B. Towles presented the architecture of Round robin arbiter and Matrix arbiter. A matrix arbiter by maintaining a triangular array of state of bits W i, j for all i < j, it implements a least recently served priority scheme. The bit W i j in column j and row i, indicates the requests j takes the priority less over request i. As W j i = W i j i j,for this the diagonal elements are not needed, only the upper triangular portion of the matrix need be maintained. A request k is generated each time, it clears all bits in its row, since it was the most recently served W * k to give itself the lowest priority. Figure 3. Four Input Variable-Priority Arbiter Figure.8. shows a four-input matrix arbiter. The solid boxes denoted in the upper triangular matrix portion, consist of states maintained in six SR flip flops. The lower triangular matrix portion denoted in shaded circular portion represents the complementary output. When a request is asserted, it is AND ed with the state bits in its row to disable any lower priority requests. The outputs of all the AND gates in a column are OR-ed together to generate a disable signal for the corresponding request. For example, if bit W 02 is set and request r0 is asserted,signal dis2 will be asserted to disable lower priority requests 2.if a request is not disabled,it propagates to the corresponding grant output via a single AND gate. When a grant is asserted, it clears the state bits in its row and sets the state bits in its Column to make its requests the lowest priority on subsequent arbitrations. The modification to the state bits takes place on the next rising edge of the clock. To operate properly, a matrix arbiter must be initialized to a legal state. Not all the states of the array are meaningful since for an n-input arbiter there are 2 (n-1)n/2 states and only n! Permutations of inputs. States that result in cycles are particularly dangerous because they can result in deadlock. For example, If W 01 =W 02 =1 and W 02 =0 and requests 0,1 and 2 are all asserted, the requests will disable one another and no grants will be issued. (a) Bit Cell, (b) Four-Bit Fixed Priority Arbiter Figure 2. A Fixed Priority Arbiter Figure.4. A Four-Input Matrix Arbiter 195

3 For small number of inputs the matrix arbiter is fast, economical and performs strong fairness. However they not presented any evaluation. Authors Z.Fu and Xiang Ling worked out on RoR and Matrix arbiters, they imitated the mechanism on FPGA platform, they find that, the Matrix arbiter reach higher clock frequency, can process more number of data and consumes more resources. Authors Si Qing Zheng and Mei Yang,based on binary search algorithm they prosed Parallel round robin arbiter (PRRA) and also Improved PRRA. In IPPRA,to generate new grant signals gl and gr of PRRA are directly ANDed with grant signals, which are shown in the figure 5 and 6.They concluded that PRRA takes more timing than IPPRA. Authors Yun-Lung Lee, Jer Min Jou, and Yen-Yu Chen presented a High speed and decentralized Round robin Arbiter (HDRA) As of the conventional round-robin arbiters, the HDRA design is, area-efficient, fast with critical path delay of only O(log 4 N) and fair based on a de-centralized structure. The results of HDRA has the smaller area, cost and best arbitration performance compared with all existing arbiters. III. INDEX-BASED ROUND ROBIN ARBITER In this paper, we design a arbiter of scheme round robin, in which it takes into account of index of the incoming requests. Which has an efficiency, in the computing logic to grant the requests. Thus better designing the arbitration part helps in the power and area in lower level as compared to the above mentioned arbiters. Before designing the IRR arbiter architecture, we define some important terms like, grant_index, varianble priority. Figure.5 Four-Input PRRA Architecture A. Grant Index Figure.6 Four-input IPRRA Architecture The arbiters have the same input and output width, grants that is the output array to. Each grants have their own grant index s and is also generated in practical design, which act as a look up table in which other components like memories and multiplexer's are used in NoC and are able to request/retrieve the data from grant index s of the requested input. g_id can be used as a selection lines of a multiplexers,when they are used in the router's crossbar to switch the requested input port to the required output port. log 2 of the grant, is the width of the grant index As compared to aforementioned arbiters, because of smaller the width of g_id, our design of arbiter is smaller and fast and our first output is g_id. Here in our design both the grant and g_id are generated as outputs. Figure 7. shows the architecture of fixed priority, the request priorities are in ascending order and in linear fashion,in which r n-1 has least priority and r n has highest priority. The switch outputs the grant and g_id, when the index of first request is asserted. Then the further grant signals are generated depending upon the decoded logic of g_id. The last request r n-1 is directly ANDed with g n-1, without multiplexing like other requests. Then, if the g n-1 becomes high only when r n-1 is high and others didn t raised the request. Each input request behaves as highest priority in ascending order of the loop, if the g_id of the fixed priority arbiter is connected to one more multiplexer m p. Consider the example of four input r0,r1,r2 and r3 as requests which are connected to each multiplexers of size 2 1.If multiplexer m 1 generates an index where m1 has highest priority than other multiplexers m2,m3 m0 nothing but the r 2,r 3, and r4,outputs of these 2 1 multiplexers are then multiplexed to one more multiplexer m p,from this we can choose one of the input request as highest priority, as shown in the figure 8. g_id issue the same value for the case of no request is asserted or r0 is asserted. In order to separate these two conditions, ORing of all the input requests is done to get any_r, to check whether their is request or not.and the obtained value of any_r is directly ANDed with the g0 bit, so that the grant will become zero, when all the requests are zero. 196

4 Figure 9. Strong Fairness Waveform. Figure 7. n-input Fixed Priority Arbiter, Where m =log2 (n) B. IRR Arbiter As the g_id is also produced at the output, it points the current granted output s index. From this logic, we can choose for the next priority selection, just by adding one to the g_id. To accomplish this, g_id is stored in register. Thus by incrementing the register and connecting it as a selection line to the multiplexer mp, as shown in Figure 8. Next priority is determined. In this way the present served priority will get least priority. For next priority selection, if the next index of granted request is chosen then its next request receives the highest priority among all the requests and the current granted request receives the least priority. When there is no request condition, without changing the priority, the next_g output of priority register is feedback to the multiplexer SF, this is done to store the previous g_id value as a remembrance, Whenever this type of condition occurs to deliver the strong fairness. As any_r is logical false it selects the feedback next_g value by granting 0000 at the output end by decoding value of g_id. Figure 8. n-input IRR Arbiter, Where m=log2 (n) 197 IV. RESULTS Model is designed with efficient utilization of output resource, synthesized and simulated using cadence tool and synthesis details are shown in below figure 9 and 10, provide the strong and week fairness. Figure 10. Week Fairness Waveform Power and area report for 45nm technology of cadence tool, for the design is: V. CONCLUSION The designed paper presents a strong fairness system. Design provides the working based on the index of the requested inputs, which manipulates the operation easy and less time delay for the computation as compared to as HDRA [4], PRRA and IPRRA [5]is provided by our design to achieve a strong fairness for all input patterns Our design has the less computing time, lowfigur area leads to cost effective economical and efficiency to. Our design has less power as compared to the other arbiters. In ASIC and FPGA designs. The IRR arbiter is more economical and faster than other arbiters. Simulation results with the 45nm cadence technologoy Library show that the IRR has improved area and power over the previous design paper,the distinctive feature of our IRR arbiter design is its lower power consumption as compared to other arbiters due to its usage of fewer registers. The proposed method is applicable to diverse applications that need such comparison VI. REFERENCES [1] M. Morris Mano, Michael D. Clietti :Digital Design 4 th Edition Pearson USA: Prentice-Hall. [2] W. J. Dally and B. Towles. Arbitration, In: Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers, 2004, pp

5 [3] Z. Fu and Xiang Ling, "The design and implementation of arbiters for Network-on-chips," Proc. 2nd Int. Conf. Industrial and Information Systems, Dalian, 2010 pp [4] S. Q. Zheng and Mei Yang, "Algorithm-Hardware Codesign of Fast Parallel Round-Robin Arbiters", IEEE Trans Parallel and Distributed Systems, vol. 18, January 2007, pp [5] Yun-Lung Lee, Jer Min Jou, and Yen-Yu Chen, "A High- Speed and Decentralized Arbiter Design for NoC," Proc. IEEE/ACS Int. Conf. on Computer Systems and Applications, Rabat, 2009 pp