A design of real-time image processing platform based on TMS320C6678

Transcription

1 Advanced Materials Research Online: ISSN: , Vols , pp doi: / Trans Tech Publications, Switzerland A design of real-time image processing platform based on TMS320C6678 LeiQu 1,2,a, YanTian 1,b, JunLiu 1,2,c 1 XI'ANInstitute of Optics and Precision Mechanics of CAS, Xi'an, China 2 University of Chinese Academy of Sciences, Beijing, China a qulei@opt.ac.cn, b tianyan@opt.ac.cn, c liujun@opt.ac.cn Keywords: DSP, FPGA, C6678, C6414 Abstract: For real time target detection, identification and tracking in high frame rates, large field of view images, a real-time image processing system is designed. A TMS320C6678 DSP runs as the chief arithmetic processor of this system and FPGA as the secondary controller. C6678 is compared with the same series C6414 in image compression algorithm test. Experimental results show that the new system has a more effective construct, and higher reliability, and can provide a platform for the new high-speed image processing. Introduction With the continuous development of digital signal processing technology [4], the increase of communications and image processing algorithm s complexity, as well as increasingly tight requirements of the quality and real-time of the signal processing, single-core DSP can t keep up with demand for large-scale data processing. If the single-core DSP system is used, it is necessary to integrate a large number of DSP chips on one board. Not only the system power consumption will be increased, but the task allocation and coordination among the various DSPs will be an additional cost, so it is necessary to design a processing system with multi-core processors in parallel. In addition, the FPGA has rich logical resources, so it is easy to dock with the data input device interfaces. The use of architecture in the form of DSP + FPAG can give full play to the advantages of DSP and FPGA to achieve large-scale data processing Introduction Fig.1 C6678 structure All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, (ID: , Pennsylvania State University, University Park, USA-05/03/16,21:28:48)

2 Advanced Materials Research Vols C6678 is 8-core floating-point DSP in the C66 series, its maximum operating frequency of each core can reach 1.25GHz. It executes 32 fixed-point data or 16 floating point data operations arithmetic in a single instruction cycle. It can provide 320 GMAC fixed-point calculation or 160 GFLOP floating-point computing ability. The internal structure is shown in Figure 1. Each core has 64KB level 1 and 512KB level 2 storage space. A 4MB shared SRAM is inside the chip for core data interchange [1]. If the internal storage space does not meet the requirements of application, C6678 also offers DDR3 controller interface which can connect DDR3 and directly control 8GB addressing range. There are four SRIO high-speed serial interfaces in the chip Peripheral, two PCIE interface, 16-bit external memory EMIF interface, Gigabit Ethernet port and SPI, I2C bus, UART, TSIP, GPIO interfaces etc. With these resources, these interfaces interchange data by high-speed interactive data bus on the chip. 2 System Hardware Design 2.1 system structure Figure 2 shows the overall structure of the hardware, FPGA is responsible for controlling each unit in logic and storing the collected image data in the DDR2 SDRAM, then pretreating these data by SDRAM Ping-Pong structure, and transporting the processed data to DSP by SRIO. When the specific processing algorithm is completed, finally, the processed data returns to the FPGA for storage and transmission Fig.2 System structure 2.2 Power Circuit The core and external I/O of DSP in C6000 series both need power supply. TMS320C6678 is the latest released DSP based on KeyStone architecture by TI. The chip has eight cores with a working speed up to 10 GHz. So the power supply system should meet high demands which ordinary power system cannot, and the core voltage is the most complicated. The DSP core power supply is divided to two domains: UCD9244 and UCD7242. The external I / O and FPGA's power demand is 0.75V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V. The 1.2V, 1.8V, 2.5V voltage are converted by chip TPS73701DRBT, the 1.5V and 0.75V voltage converted by chip TPS51200DRCT, and the 3.3V is converted by chip TPS54620RGY. Power on sequence is logically controlled by FPGA. UCD9222 has a VID Interface. The VID interface is a standard interface based on SmartReflex technology to achieve the detection of static and dynamic power consumption of the device. UCD9222 is a digital PWM waveform control chip that providing two-way multi-phase synchronous digital PWM control signals and the structure of loop controlled by two-way PWM signal are completely same. The compensation filter outputs a high-resolution PWM waveform under the ARM control. It will control the voltage driver chips UCD7242 by changing the PWM

3 1456 New Technologies for Engineering Research and Design in Industry waveform and adjusting the output voltage and current of UCD7242 to digitally control the power supply [3]. The inner-core power supply schematic is shown in Figure 3. Fig.3 Inner-core power supply schematic 2.3 Clock Design In particular clock circuit design, the clock chip CDCE62005 is used which is specially developed for high-speed DSP by TI. Only a 25MHz single-ended clock is needed by CDCE62005 to output up to 5-way differential clock frequency range of 125 KHz-1.5GHz. Thus the requirement of TMS320C6678 s six groups of clock: CORECLK, DDRCLK, PASSCLK, SRIOCLK, MCMCLK and PCIECLK are all met [2]. The clock resource is shown in Figure 4. Fig.4 Clock resource 2.4 Reset Circuit Power-on reset, Hard reset, Soft reset, Local reset are included by reset control in platform design. Power-on reset pin PORz and RESETFULLz both are active low [6]. Hardware reset pin RESETz is active low, software reset is active also when RESETz is low, and the difference between hardware and software reset is the configuration of RSCFG register. Local reset is active when pin LRSETz is low. And RESETSTATz can be triggered (driven low) by former three reset conditions. After the

4 Advanced Materials Research Vols device is fully initialized, RESETSTATz is de-asserted [1] (driven high) and all of the reset conditions are logically controlled by the FPGA. Figure 5 shows the reset control part of the DSP. Fig.5 RESET CONTROL 2.5 JTAG Interface Design There are seven emulation pins on C6678: TRST, TMS, TDI, TDO, TCK, EMU0 and EMU1 that are connected to a 14-foot double-row plug which can be connected with the XDS560 emulator. The system debugging can be processed via a program downloaded from a PC. 2.6 Memory Configuration There are two pieces of 64bit-width DDR2 SDRAM memory which have 64MB store capacity each and 533MHz memory operating speed provided for FPGA in the design. There are also four pieces of 64bit-width DDR3 SDRAM memory which have 128MB store capacity each provided for DSP ; 64MB FLASH memory. In addition, because there are a lot of internal memory integrated in DSP and FPGA, so the overall system memory resources are very abundant so that large-scale data processing is guaranteed for this system. 2.7 FPGA configuration When selecting the specific model of FPGA, following requirements are considered: supporting interconnections with DSP by SRIO interface, the number of Rocket IO transceivers integrated in FPGA, quantity of logic resources and IOs. Based on above considerations and considering that FPGA run as a system front-end data processing center in this design, and the requirement of docking FPGA in CameraLink, SDI, PAL and other types of interfaces simultaneously, the final selection of the FPGA is the K7 made by Xilinx. 3 Eight-core communication structure Fig.6 Main and auxiliary topology Main and auxiliary topology in the TMS320C6678 is shown in Figure 6. Processor which is running as the main core (control core) exchanges data with external DDR memory via EDMA. Afterwards, the main core communicates with the auxiliary cores by inter-core interrupt. The main core plays a controlling role, and all the auxiliary cores (computing cores) interrupts are all handled

5 1458 New Technologies for Engineering Research and Design in Industry by the controlling core. Auxiliary cores are only responsible for computing tasks and there is no inter-core communication between the auxiliary cores [7]. The 7 auxiliary cores as auxiliary ones in main and auxiliary structure can run in parallel and save run-time. 4 Simulations This platform is used for H.264 baseline level compression in the experiment. 20 frames of 1024*1024 BMP images in the IPPPP frame arrangement are to be compressed with a compression ratio of Processing results are shown in Table 1. Table 1 C6678 runtime Corenumbers runtime(ms) ms processing time is needed when one inner-core is used in C6678, while ms is need for two cores, ms for four cores, and ms for eight cores. If a single-core DSP C6416 is used in processing, run time will be ms. The C6416 s run time is times than C6678 s in the condition of C6678 s eight cores running at the same time in the main and auxiliary structure, so this platform s characteristic of real-time is more obvious. 5. Conclusion The system uses a DSP + FPGA structure and comprehensively designs hardware includes: the power supply circuit, the clock circuit, the reset circuit, the debug interface and the memory configurations. This system processes images with the great computing power of TMS320C6678 DSP and the logical control ability of the FPGA, and optimizes the C6678 s eight-core communication architecture. Considering the results of the test of image compression algorithm [5] in which the C6416 is compared with, we can make the conclusion that the platform which is advanced and practical [4] can be better applied in a variety of embedded image processing systems. References [1] Texas Instruments: TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor Data Manual, USA: 12-13, (2011). [2] Texas Instruments: Hardware Design Guide for KeyStone Devices, USA: 16, (2010). [3] Wu Minjie, Feng Qi, Yuan Naichang: Power supply design of TMS320C6678 DSP, Electronic Design Engineering, , (2012). [4] JiaYaqiong: Design of digital video image processing system based on TMS320C6711, Electronic Test, 1-4, (2008). [5] Chen Bing, Wang Xingguo, Liu Jilin: Real Time Image Processing System Based on DSP TMS320C6x, Opto-Electronic Engineering, 37-41, (2000). [6] Texas Instruments: TMDXEVM6678LEVM Technical Reference Manual Version 2.0, USA: 53, (2011). [7] Wu Hao, XiaoJiyang, Fan Hongqi, FuQiang: Inter-processor communication method of TMS320C6678 multicore DSP, Embedded Technology, 11-13, (2012).

6 New Technologies for Engineering Research and Design in Industry / A Design of Real-Time Image Processing Platform Based on TMS320C /