wiznet MMwiz 5300 Ethernet net5300 User Guide minimodule REV 1.0 Many ideas one solution

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1 MMwiz wiznet net00 REV.0 00 Ethernet minimodule User Guide Evalu ation Board s for, AVR, ST, PIC microcontrollers Sta- rter Kits Embedded Web Serve rs Prototyping Boards Minimodules for microcontrollers, etherdesigning Evaluation Boards net controllers, RFID High Spe- ed In System programmers for AVR, PIC, ST microcontrollers Microprocesor systems, PCB for, AVR, ST, PIC microcontrollers Starter Kits Embedded Web Servers Prototyping Boards mi- nimodules for microcontrollers, ethernet controllers, RFID High Speed In Systems programme- rs for AVR, PIC, ST microcontrlollers Microprocesor systems, PCB designing Evaluation Bo- ards for `, AVR, ST, PIC microcontrollers Starter Kits Embe- dded Web Serwers Prototyping Boards Minimodules for microcontrollercontrollers, ethernet controllers, High Speed In System program- mers for AVR, PIC, ST microco- Microprocesor R Many ideas one solution Systems, PCB Designing Evaluation Boards

2 Contents INTRODUCTION... APPLICATIONS... FEATURES... CONSTRUCTION OF THE MODULE... BLOCK DIAGRAM... MODULE PIN-OUT... ATMEGA MICROCONTROLLER... ETHERNET CONTROLLER W00... MEMORY CONTROLLER... DATAFLASH MEMORY... RESET CIRCUIT... LED DIODES... CONNECTION OF THE MODULE WITH THE EXTERNAL WORLD... CONNECTION TO THE ETHERNET NETWORK... RS- INTERFACE... RS- INTERFACE... USB INTERFACE... RADIO LINK... LCD DISPLAY... PROGRAMMING THE MODULE... ISP CONNECTOR... JTAG CONNECTOR... 0 AN APPLICATION EXAMPLE... EVALUATION BOARD... SPECIFICATIONS... TECHNICAL ASSISTANCE... GUARANTEE... ASSEMBLY DRAWINGS... DIMENSIONS... SCHEMATICS...

3 Introduction Thank you for buying MMwiznet00 minimodule. It was created with the idea of facilitating the communication of microprocessor systems through the Internet/Ethernet networks. The heart of the module is the RISC Atmega microcontroller with kb of program memory and kb of (external) RAM memory, co-operating with the Ethernet controller, WizNET W00. The minimodule has an kb DataFlash serial memory for storage of WWW pages and of any files e.g. with measurement data. The memory is connected to a fast SPI bus with Mb/s transmission speed. Applications The MMwiznet00 minimodule can be used as a design base for electronic circuits co-operating from the Ethernet/Internet network, covering the following areas of interest: Industrial remote controlling and monitoring systems Telemetry Intelligent buildings Alarm systems Weather stations and environment monitoring Medical electronics Heating and air-conditioning systems Telecommunication Road traffic monitoring Remote data logging Home automation The MMwiznet00 minimodule can be also used in didactic workshops of information and electronic schools, illustrating the aspects of co-operation of electronic circuits from the Ethernet/Internet network, as well as be used to construct thesis circuits. Features Fast RISC microcontroller ATmega with up to MIPS throughput Ethernet controller/0mb/s W00 with hardware TCP/IP stack kb of in circuit programmable FLASH program memory KB of RAM memory kb of EEPROM memory Serial DataFlash memory Mbits (kbytes) Reliable reset circuit Crystal resonator. or MHz LED diodes indicating: power, LAN activity, DataFlash activity Fully SMD made on -layer PCB x 0 terminals with 0." (.mm) pitch fitting every prototype board Available free operating system with TCP/IP stack supporting many protocols Available evaluation board and sample applications Small dimensions: mm x 0.mm

4 Construction of the module Block diagram The block diagram of the MMwiznet00 minimodule is shown in the drawing: BUS PORTE ATmega kb RAM W00 PORTF EEPROM PORTB PORTD DataFlash MHz Figure Block diagram of the MMwiznet00 minimodule. Minimodule is sold in version MMwiznet00---, which contain Mbit DataFlash memory, MHz crystal and RJ connector mounted. For larger quantity orders it is possible to adjust module to customer s needs, and then ordering using following selector is possible MMwiznet00 f c c 0 without DataFlash Mb DataFlash Mb DataFlash Mb DataFlash Mb DataFlash. -. MHz Crystal - MHz Crystal - MHz Crystal - MHz Crystal MHz Crystal. -. MHz Crystal - MHz Crystal 0 without RJ connector(j mounted instead) with RJ connector

5 Module pin-out Figure Module pin-out top view.

6 Function in MMwiznet 00 Name J J Name PB0/#SS PE/ INT DataFlash SCK PB/ SCK PE/ INT DataFlash - MOSI PB/MOSI PE/ INT DataFlash MISO PB/ MISO PE/ INT PB/OC0/PWM0 PE/ AC- DataFlash #CS PB/ OCA/PWMA PE/ AC+ PB/OCB/PWMB PE/ PDO/TxD Function in MMwiznet0 0 Interrupt from W00 PB/ OC/PWM PE0/ PDI/RxD PD0/#INT0/SCL AREF PD/#INT/SDA PF0/ ADC0 PD/#INT/RxD PF/ ADC PD/#INT/TxD PF/ ADC PD/ IC PF/ADC PD PF/ ADC/TCK PD/ T PF/ ADC/TMS PD/T PF/ ADC/TDO LEDACT PF/ ADC/TDI LEDLINK TOSC/PG +V TOSC/PG 0 0 #RESET J No. Function Alt. function Description PB0 #SS PB0 general purpose digital I/O SS Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit. Table and Table relate the alternate functions of Port B to the overriding signals shown in Figure on page. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.

7 PB SCK PB MOSI PB MISO PB OC0/PWM0 PB OCA/PWMA PB OCB/PWMB PB OC/PWM PB general purpose digital I/O SCK Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB bit. PB general purpose digital I/O MOSI SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB bit. PB general purpose digital I/O MISO Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB bit. PB general purpose digital I/O OC0 Output Compare Match output: The PB pin can serve as an eternal output for the Timer/Counter0 Output Compare. The pin has to be configured as an output (DDB set (one)) to serve this function. The OC0 pin is also the output pin for the PWM mode timer function. PB general purpose digital I/O OCA Output Compare Match A output: The PB pin can serve as an external output for the Timer/Counter Output Compare A. The pin has to be configured as an output (DDB set (one)) to serve this function. The OCA pin is also the output pin for the PWM mode timer function. PB general purpose digital I/O OCB Output Compare Match B output: The PB pin can serve as an external output for the Timer/Counter Output Compare B. The pin has to be configured as an output (DDB set (one)) to serve this function. The OCB pin is also the output pin for the PWM mode timer function. PB general purpose digital I/O OC Output Compare Match output: The PB pin can serve as an external output for the Timer/Counter Output Compare. The pin has to be configured as an output (DDB set one ) to serve this function. The OC pin is also the output pin for the PWM mode timer function. OCC Output Compare Match C output: The PB pin can serve as an external output for the Timer/Counter Output Compare C. The pin has to be configured as an output (DDB set (one)) to serve this function. The OCC pin is also the output pin for the PWM mode timer function.

8 PD0 #INT0/SCL PD0 general purpose digital I/O INT0 External Interrupt source 0. The PD0 pin can serve as an external interrupt source to the MCU. SCL Two-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PD0 is disconnected from the port and becomes the Serial Clock I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. PD #INT/SDA PD general purpose digital I/O INT External Interrupt source. The PD pin can serve as an external interrupt source to the MCU. SDA Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PD is disconnected from the port and becomes the Serial Data I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. PD #INT/RxD PD general purpose digital I/O INT External Interrupt source. The PD pin can serve as an External Interrupt source to the MCU. RXD Receive Data (Data input pin for the USART). When the USART receiver is enabled this pin is configured as an input regardless of the value of DDD. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD bit. PD #INT/TxD PD general purpose digital I/O INT External Interrupt source : The PD pin can serve as an external interrupt source to the MCU. TXD Transmit Data (Data output pin for the USART). When the USART Transmitter is enabled, this pin is configured as an output regardless of the value of DDD. PD IC PD general purpose digital I/O XCK USART External clock. The Data Direction Register (DDD) controls whether the clock is output (DDD set) or input (DDD cleared). The XCK pin is active only when the USART operates in Synchronous mode. IC Input Capture Pin: The PD pin can act as an input capture pin for Timer/Counter. PD PD general purpose digital I/O PD T PD general purpose digital I/O T Timer/Counter counter source. PD T PD general purpose digital I/O T Timer/Counter counter source. LEDACT The output of the LEDACT diode driving signal (indicating activity of the module in Ethernet network). It can be used to connect an additional diode, e.g. led out externally to the device case. LEDLINK +V Power supply input +V. 0 Grodund. The output of the LEDLINK diode driving signal (indicating connection to the Ethernet network). It can be used to connect an additional diode, e.g. led out externally to the device case.

9 J Nr Funkcja Alt. funkcja Opis PE INT PE General purpose digital I/O INT External Interrupt source : The PE pin can serve as an external interrupt source. IC Input Capture Pin: The PE pin can act as an input capture pin for Timer/Counter. PE INT PE general purpose digital I/O INT External Interrupt source : The PE pin can serve as an external interrupt source. T Timer/Counter counter source. PE INT PE general purpose digital I/O INT External Interrupt source : The PE pin can serve as an External Interrupt source. OCC Output Compare Match C output: The PE pin can serve as an External output for the Timer/Counter Output Compare C. The pin has to be configured as an output (DDE set one ) to serve this function. The OCC pin is also the output pin for the PWM mode timer function. PE INT PE general purpose digital I/O INT External Interrupt source : The PE pin can serve as an External Interrupt source. OCB Output Compare Match B output: The PE pin can serve as an External output for the Timer/Counter Output Compare B. The pin has to be configured as an output (DDE set (one)) to serve this function. The OCB pin is also the output pin for the PWM mode timer function. PE AC- PE general purpose digital I/O AC- Analog Comparator Negative input. This pin is directly connected to the negative input of the Analog Comparator. OCA, Output Compare Match A output: The PE pin can serve as an External output for the Timer/Counter Output Compare A. The pin has to be configured as an output (DDE set one ) to serve this function. The OCA pin is also the output pin for the PWM mode timer function. PE AC+ PE general purpose digital I/O AC+ Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. XCK0, USART0 External clock. The Data Direction Register (DDE) controls whether the clock is output (DDE set) or input (DDE cleared). The XCK0 pin is active only when the USART0 operates in Synchronous mode. PE PDO/TPD PE general purpose digital I/O PDO SPI Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the ATmega. TXD0 UART0 Transmit pin.

10 PE0 PDI/RxD PE0 general purpose digital I/O PDI SPI Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the ATmega. RXD0 USART0 Receive Pin. Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled this pin is configured as an input regardless of the value of DDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up. AREF Analog reference voltage for the A/D converter PF0 ADC0 PF0 general purpose digital I/O ADC0 Analog to Digital Converter, Channel 0. PF ADC PF general purpose digital I/O ADC Analog to Digital Converter, Channel. PF ADC PF general purpose digital I/O ADC Analog to Digital Converter, Channel. PF ADC PF general purpose digital I/O ADC Analog to Digital Converter, Channel. PF ADC/TCK PF general purpose digital I/O ADC Analog to Digital Converter, Channel. TCK JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin. PF ADC/TMS PF general purpose digital I/O ADC Analog to Digital Converter, Channel. TMS JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. PF ADC/TDO PF general purpose digital I/O ADC Analog to Digital Converter, Channel. TDO JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. The TDO pin is tri-stated unless TAP states that shift out data are entered. PF ADC/TDI PF general purpose digital I/O ADC Analog to Digital Converter, Channel. TDI JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Register (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin. PG TOSC PG general purpose digital I/O TOSC - Timer Oscillator pin : When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG is disconnected from the port, and becomes the input of the inverting Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin. PG TOSC PG general purpose digital I/O TOSC - Timer Oscillator pin : When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG is disconnected from the port, and becomes the inverting output of the Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin, and the pin can not be used as an I/O in. 0 #RESET Input/output of RESET signal

11 ATmega microcontroller High-performance RISC architecture, instructions (most single clock cycle execution), MIPS at MHz KBytes of Flash memory K Bytes of SRAM memory K Bytes of EEPROM SPI Master/Slave interface Four internal timers/counters /bit Two UART interfaces (up to Mbaud) Serial interface compatible with IC In System Programming In Circuit Debugging through JTAG interface Real Time Clock with khz oscillator channel -bti A/D converter I/O ports PWM outputs Extended temperature range, internal and external interrupt sources Internal watchdog timer More informations at Atmel's site Ethernet controller W00 Single chip Ethernet contro ller with embedded TCP/IP stack Integrated BaseT/0BaseTX Ethernet PHY Supports hardwired TCP/IP protocols : TCP,UDP,ICMP,IPv,ARP,IGMPv,PPPoE,Ethernet Supports independent SOCKETs simultaneously High network performance : Up to 0Mbps Supports PPPoE connection (with PAP/CHAP Authentication mode) Internal Kbytes memory for data communication Supports auto negotiation and auto MDI/MDIX(Crossover) Supports network Indicator LEDs The module is adapted to operate with the network controller with use of interrupts. The interrupt signal is connected to input INT (PE) of the microcontroller. The state of the Ethernet controller is signaled by two LED diodes: LNK connection with the network, and ACT active (transmission/reception).

12 Memory controller MMwiznet00 has simple memory controller, which divides memory space into two areas: RAM memory area and Ethernet controller area. Implementation of memory controller is shown on drawing below +V A A A A A A U HC0 UC HC00 #SEL_LAN #SEL_RAM Memory map is shown below: FFFF FC00 W00 External RAM and MCU s internal RAM B 0000

13 DataFlash memory The minimodule can be equipped with serial ATDB DataFlash memory ( - Mb capacity), this gives 0. MB of memory for storing files with WWW pages or collecting measurement files. The memory is connected to a fast SPI bus with MB/s transmission speed. Memory chip is activated after applying a low logic level to #CS input. The #CS input of memory is connected to port PB of the microcontroller. The SPI bus occupies three terminals of the microprocessor: PB, PB, PB. It should be kept in mind that if DataFlash memory is installed, the just outlined port terminals cannot be used externally to the module. Of course the SPI bus can be used for communication with external peripherals, under the condition that they will have circuit selection inputs (CS). The diagram below shows the connection of DataFlash memory inside the module. +V D DF U +V R k C 0n WP# RST# SI SO SCK CS# PB PB PB PB ATDB0B Figure Connection of DataFlash memory inside the module. A detailed description of DataFlash circuits is on the Atmel Company page: RESET circuit The MMwiznet00 has a built-in voltage monitoring circuit constructed around the DS integrated circuit. The circuit generates a RESET signal in case when the supply voltage value is lower than. V. This takes place when the supply voltage is switched on or off, when the voltage changes its value from 0 to V. The guard circuit detects also momentary voltage drops. A short duration drop of below. V causes the generation of a resetting signal of 0 ms duration. This signal is applied directly to the resetting input of the microcontroller and the W00. The RESET signal is led out to a module connector and it can be used as the zeroing output resetting external circuits and as the input for resetting the module, e.g. by means of the RESET button. In such a case the RESET button can short the RESET line directly to ground. An implementation of the reset circuit is presented in the diagram below. +V +V U RST DS R k UD #RESET RESET HC00 Figure Implementation of the reset circuit in the module.

14 LED diodes The minimodule is equipped with four LED diodes which signal the following: supply of power operation of the Ethernet controller: o connection to the network o activity (transmission/reception) operation of the DataFlash memory (analogously as the HDD diode in PCs). Diode signals (with exception of DataFlash diode) are led out outside the module which enables doubling the signaling e.g. externally to the device case. An example of a realization of such a solution is shown in the drawing: J_ J_ J_ J_ +V ACT LINK k k +V J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_0 PB0/SS PE/INT PB/SCK PE/INT PB/MOSI PE/INT PB/MISO PE/INT PB/OC0/PWM0 PE/AC- PB/OCA/PWMA PE/AC+ PB/OCB/PWMB PE/PDO/TxD0 PB/OC/PWM PE0/PDI/RxD0 PD0/INT0/SCL AREF PD/INT/SDA PF0/ADC0 PD/INT/RxD PF/ADC PD/INT/TxD PF/ADC PD/IC PF/ADC PD PF/ADC PD/T PF/ADC PD/T PF/ADC LED_ACTIV PF/ADC LED_LINK TOSC +V TOSC #RESET TPIN- TPIN+ TPOUT- TPOUT+ MMnet0 J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_0 RESET Figure Connection of external signaling diodes and the RESET button.

15 Connection of the module with the external world Connection to the Ethernet network MMwiznet00 module has RJ connector integrated with separation transformer and LED diodes. This frees the user from necessity of buying suitable components and mounting them on base board. Led diodes indicates operation of the Ethernet controller: green connection to the network, orange activity. +.V D LINK R 0R +.V D ACT R 0R J Header ACTLED LINKLED TXOP TXON RXIP RXIN R.R R.R C 0nF R.R R.R C 0nF +VA +.V R 0R R 0R C0 0nF J A K A K TXD+ TXD_CT TXD- RXD+ RXD_CT RXD- SH SH SH JFM0-0T LAN Figure Connection of RJ jack inside module. The module can be also bought without mounted RJ connector. In this case Ethernet signals are led out from module through J connector. This option makes possible to place separation transformer on the base board and use Power-Over-Ethernet technology or power device through Ethernet cable. AC AC 0F00N RXIN RXIP TXON TXOP XMIT RCV RJ RX+ TX- TX+ SH SH RX- LAN n n n n/kv n/kv LAN_ LAN_ LAN_ Figure Connection to the Ethernet using a transformer.

16 RS- interface The ATmega microcontroller has two USART ports which can be used to connect the minimodule with a PC computer or other equipment equipped with a RS- port. Such a connection requires a level converter based on a MAX or similar IC, connected to the TxD and RxD lines. +V +V 0n V+ C+ 0n DBF 0n V- C- C+ 0n RS- T OUT T OUT R IN R IN C- T IN T IN R OUT R OUT ST PE(TxD0) lub PD(TxD) PE0(RxD0) lub PD(RxD) Figure Connection of the RS- to the MMwiznet00. RS- interface The RS- interface facilitates long-distance transmission in a difficult environment. An implementation of this interface is as simple as that of RS- and requires only a line driver, e.g. MAX. The feature discerning this interface from RS- is the necessity to control the direction of action of the driver (transmission/reception). This control is effected through the program, using any I/O pin of the microcontroller. The 0R resistors visible in the diagram polarize initially the inputs, increasing the immunity to interference. The 0R resistor connected by means of a shorting strap is used to match the interface to the line impedance. +V +V JP PE0(RxD0) lub PD(RxD) Pxx PE(TxD0) lub PD(TxD) U RO RE DE DI B A 0R 0R B A MAX 0R Figure Connection of the RS- port to the MMwiznet00.

17 USB interface The current standard in connecting with a PC, the USB interface, permits quick transfers and taking the power supply from the computer. Thanks to the existence of circuits converting the USB interface to RS-, its implementation in own equipment is very simple and cheap. The drawing below presents a way of equipping the MMwiznet00 module with an USB interface, using the MMusb module. After installing VCP drivers, such an interface is seen in the system as a virtual COM port, thus its software on the PC should surely provide no problems. USB Connector RX +V k k TX PE(TxD0) lub PD(TxD) PE0(RxD0) lub PD(RxD) TXLED PWRCTL PWREN TxDEN RI DCD DSR DTR CTS RTS RxD TxD MMusb PORT EXT IO RXLED SLEEP VOUT RESETO RESET NC 0 +V_USB Figure Connection of the USB port to the MMnet0. Additional information on the MMusb module can be found on the web page: Radio link Fitting the system with the possibility of communicating via a wireless path provides a possibility of easy control and collection of measurement data from system elements dispersed in the object, without the need to install any cabling. Thanks to the existence of integrated transceivers the construction of such links is relatively simple. The figure presents a way of connecting an MMnet0 module with a radio minimodule MMcc00. To execute such a connection, five I/O microcontroller lines are needed, including one breakpoint input. An optional connection of the RSSI output with the input of the A/D converter permits the measurement of the strength of the received signal. ADCx Pxx INTx Pxx Pxx Pxx k k k k k J_ J_ J_ J_ J_ J_ CHP DIO DCLK PCLK PDATA PALE J MMcc00 RSSI ANT J J_ J_ J_ J_ J_ J_ +.V Antena Additional information on the MMcc00 module can be found on the page:

18 LCD display MMwiznet00 module does not have external system bus, so LCD display can be connected only to microcontroller s ports. Such a solution is shown in the figure below. +V k 0R 0n +V PE PE PE PE0 PE PE PE CONT RS RW E D0 D D D D D D D LCD x HD0 Figure Connection of the LCD display to microcontroller ports. RW input can be permanently connected to ground, which reduce necessary pin count to six. Programming the module The ATmega microcontroller has kb of Flash memory programmable in the system for the program code and kb of EEPROM memory for user s data. Programming of these memories can be effected in two ways: by means of an ISP interface or through JTAG. Both interfaces have a standard of used connectors and a standard of arranging signals in the connector. ISP connector The programmer in ISP standard communicates with the microcontroller through a three-wire SPI interface (plus the RESET signal and power supply). The interface uses the I/O terminals of the microcontroller (PE0, PE and PB) which, after the programming, can fulfill ordinary functions. When connecting peripherals to these terminals it should be remembered that the programmer should have the possibility to force appropriate logic levels on them. The figures below present the method of connecting the ISP connector to the module. Figure shows the use of an analog multiplexer 0 to separate the programmer from the peripherals connected to microcontroller ports.

19 +V ISP +V MISO SCK RST LED MOSI ISP k +V PE/INT J_ PE/INT J_ PE/INT J_ PE/INT J_ PE/AC- J_ PE/AC+ J_ PE/PDO/TxD0 J_ PE0/PDI/RxD0 J_ PF/ADC J_ PF/ADC J_ PF/ADC J_ PF/ADC J_ PF/ADC J_ PF/ADC J_ PF/ADC J_ PF0/ADC0 J_ AREF J_ +V J_ J_0 LED_LINK J_ LED_ACTIV J_ #RESET J_0 TOSC J_ TOSC J_ PD/T J_ PD/T J_ PD J_ PD/IC J_ PD/INT/TxD J_ PD/INT/RxD J_ PD/INT/SDA J_ PD0/INT0/SCL J_ PB/OC/PWM J_ PB/OCB/PWMB J_ PB/OCA/PWMA J_ PB/OC0/PWM0 J_ PB/MISO J_ PB/MOSI J_ PB/SCK J_ PB0/SS J_ TPIN- J_ TPIN+ J_ TPOUT- J_ TPOUT+ J_ MMwiznet00 Figure Connecting the MMnet0 module with an ISP connector. +V ISP #RESET +V X0 X Y0 Y Z0 Z INH A B C X Y Z VDD VSS VEE 0 PE PB PE0 +V ISP +V k MISO SCK RST LED MOSI #RESET PE/INT J_ PE/INT J_ PE/INT J_ PE/INT J_ PE/AC- J_ PE/AC+ J_ PE/PDO/TxD0 J_ PE0/PDI/RxD0 J_ PF/ADC J_ PF/ADC J_ PF/ADC J_ PF/ADC J_ PF/ADC J_ PF/ADC J_ PF/ADC J_ PF0/ADC0 J_ AREF J_ +V J_ J_0 LED_LINK J_ LED_ACTIV J_ #RESET J_0 TOSC J_ TOSC J_ PD/T J_ PD/T J_ PD J_ PD/IC J_ PD/INT/TxD J_ PD/INT/RxD J_ PD/INT/SDA J_ PD0/INT0/SCL J_ PB/OC/PWM J_ PB/OCB/PWMB J_ PB/OCA/PWMA J_ PB/OC0/PWM0 J_ PB/MISO J_ PB/MOSI J_ PB/SCK J_ PB0/SS J_ TPIN- J_ TPIN+ J_ TPOUT- J_ TPOUT+ J_ MMwiznet00 Figure Connection of the MMnet0 module with an ISP connector using a multiplexer.

20 MOSI LED RST SCK MISO Figure ISP connector. PIN DESCRIPTION MOSI Commands and data from programmer to target LED Multiplexer and LED diode driving signal RST RESET signal SCK Serial Clock, Controlled by programmer MISO Data from target AVR to programmer Supply voltage to the programmer Ground Caution: The SPI interface used for programming the processor is not the same interface which is available to the user for communication with peripherals and it uses other outputs. Programmers which can be used to program the MMnet0 can be found on the following pages: - ISPCable I: - ISPCable II: JTAG connector JTAG is a four-lead interface permitting the takeover of control over the processor s core and its internal peripherals. The possibilities offered by this interface are, among others: step operation, full-speed operation, equipment and program pitfalls, inspection and modification of contents of registers and data memories. Apart from this, functions are available offered by ISP programmers: programming and readout of Flash, EEPROM, fuse memories and lock bites. The method of connecting the JTAG connector to the minimodule is shown in the drawing: J_ J_ J_ J_ +V J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_0 PB0/SS PE/INT PB/SCK PE/INT PB/MOSI PE/INT PB/MISO PE/INT PB/OC0/PWM0 PE/AC- PB/OCA/PWMA PE/AC+ PB/OCB/PWMB PE/PDO/TxD0 PB/OC/PWM PE0/PDI/RxD0 PD0/INT0/SCL AREF PD/INT/SDA PF0/ADC0 PD/INT/RxD PF/ADC PD/INT/TxD PF/ADC PD/IC PF/ADC PD PF/ADC PD/T PF/ADC PD/T PF/ADC LED_ACTIV PF/ADC LED_LINK TOSC +V TOSC #RESET TPIN- TPIN+ TPOUT- TPOUT+ MMwiznet00 J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_0 +V TCK TDO TMS TDI J JTAG Vref RST +V Figure Connection of the MMnet0 module with the JTAG connector. 0

21 TCK TDO TMS TDI Vref NSRST NTRST Figure JTAG connector. TCK TDO TMS TDI Vref RST PIN DESCRIPTION Test Clock, clock signal from emulator to target Test Data Output, data signal from target to emul. Test Mode Select, mode select signal from Supply voltage to the emulator Test Data Input, data signal from emul. to target Target voltage sense RESET signal Ground If the JTAG interface is connected into the fuse bits of the microcontroller, then terminals PF...PF (ADC...ADC) can serve only as an interface and cannot operate as I/O terminals or analogue inputs. The programmer/emulator JTAG can be found on the page: - JTAGCable I : An application example The diagram below shows the MMwiznet module in a simple application, controlling relays through the Ethernet network (e.g. surfing the WWW). The diagram does not include the supply of power. LAN J_ J_ J_ J_ +V J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_0 PB0/SS PE/INT PB/SCK PE/INT PB/MOSI PE/INT PB/MISO PE/INT PB/OC0/PWM0 PE/AC- PB/OCA/PWMA PE/AC+ PB/OCB/PWMB PE/PDO/TxD0 PB/OC/PWM PE0/PDI/RxD0 PD0/INT0/SCL AREF PD/INT/SDA PF0/ADC0 PD/INT/RxD PF/ADC PD/INT/TxD PF/ADC PD/IC PF/ADC PD PF/ADC PD/T PF/ADC PD/T PF/ADC LED_ACTIV PF/ADC LED_LINK TOSC +V TOSC #RESET TPIN- TPIN+ TPOUT- TPOUT+ MMwiznet00 J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_ J_0 k k +V BC N k BC N k ARK ARK RREL RREL Figure MMwiznet00 in a simple application controlling relays through the Ethernet network.

22 Evaluation Board Minimodule can be used with two evaluation foards from Propox offer. Below is short characterisation of them: EVBnet0 Power supply RS port USB port (with use of MMusb minimodule) ISP connector JTAG connector x chars LCD display LED diodes push-buttons potentiometers Prototype design area EVBmmTm Connector with all terminals of the minimodule Connectors of all peripherals accessible on board JTAG connector for in system programming and debugging Voltage regulators (+V and +,V) Possibility supply with USB Port Power switch switches and LED diodes Buzzer potentiometers IRDA port USB Device and USB Host ports Two ports RS with LEDs Codec Audio CAN Interface -WIRE connector SD/MMC card slot Alphanumeric LCD connector Graphic LCD connector More info: More info:

23 Specifications Microcontroller ATmega MHz Ethernet controller W00 /0Mb/s Program memory kb Data memory kb EEPROM memory kb DataFlash memory up to MB No. of digital I/O up to No. of analog inputs up to Power V % Dimensions x0.mm Weight ok. 0g Operating temperature range 0 0ºC Humidity % Connectors double x0 headers Technical assistance In order to obtain technical assistance please contact support@propox.com. In the request please include the following information: number of the module version (e.g. REV ) a detailed description of the problem Guarantee The MMwiznet00 minimodule is covered by a six-month guarantee. All faults and defects not caused by the user will be removed at the Producer s cost. Transportation costs are borne by the buyer. The manufacturer takes no responsibility for any damage and defects caused in the course of using the MMwiznet00 module.

24 Assembly drawings Figure Assembly drawing top layer. Figure Assembly drawing bottom layer.

25 Dimensions Figure Dimensions top view. Figure Dimensions side view. Schematics

26 ADC ADC ADC ADC ADC ADC ADC0 ADC PD PD PD PD0 PD PD PD PD #RD ALE #WR PE PE PE PE PB0 PB PB PB PE PB PB PE #RESET PB RESET 0 XTAL XTAL A A AREF PC0/A PC/A PC/A PC/A PC/A PC/A 0 PC/A PC/A PD0(/INT0/SCL) PD(/INT/SDA) PD(/INTRxD) PD(/INT/TxD) PD/IC PD 0 PD/T PD/T PB0/SS PB/SCK PB/MOSI PB/MISO PB/OC0/PWM0 PB/OCA/PWMA PB/OCB/PWMB PB/OC/PWM PA0/AD0 PA/AD 0 PA/AD PA/AD PA/AD PA/AD PA/AD PA/AD PF/ADC PF/ADC PF/ADC PF/ADC PF/ADC PF/ADC PF/ADC 0 PF0/ADC0 ALE RD WR TOSC TOSC PEN PE0/PDI/RxD PE/PDO/TxD PE/AC+ PE/AC- PE/INT PE/INT PE/INT PE/INT U ATMEGA C pf C pf X MHz +V +V +V +V AD0 AD AD AD AD AD AD AD A A A A A A A A PE PB PE0 C 0nF D D D D D D D D C OC Q Q Q Q Q Q Q Q U HC ALE A0 A A A A A A A AD AD0 AD AD AD AD AD AD C 0nF +V C 0nF C 0nF Sheet of support@propox.com Size: File: Rev: Date: Title: MMwiznet00 #RESET +V RST U DS 0 J Header 0 0 J Header 0 AREF +V ADC ADC ADC ADC ADC ADC ADC0 ADC AREF PE PE PE PE PE PE PE PE0 PB0 PB PB PB PB PB PB PB PD PD PD PD0 PD PD PD PD #RESET TOSC TOSC TOSC TOSC SCK SO SI CS# WP# RST# U ATDBD C 0nF #RD #WR +V AD AD0 AD AD AD AD AD AD A A A A A A KT0 A0 0 A A A A A A A A A A A A A A CS 0 OE WE D0 D D D D D D D A A CS A U +V A A R k PWR D +V R k DF D U HC0 UC HC00 #SEL_LAN #SEL_RAM A A A A A A #SEL_RAM PB PB PB PB C 0nF C 0nF +V UB HC00 LINKLED UA HC00 R k +V + C u/v +.V + C u/v VIN VOUT TAB U SPX0M-. +V +.V +V +V UD HC00 ACTLED +V

27 Sheet of Size: File: Rev: Date: Title: MMwiznet00 LAN C0 0nF J Header SH SH TXD+ TXD_CT TXD- RXD+ RXD_CT RXD- SH A K A K J JFM0-0T R 0R R 0R A0 A A A #RD #WR #SEL_LAN X MHz LINK D A ACT D AD AD0 AD AD AD AD AD AD PE C pf C pf +.V +.V C 0nF +.V +VA R k % R 00R % R.R R.R R.R R.R C 0nF C 0nF C 0nF C 0nF C uf + C u/v + C u/v L BLM L BLM R M +.V +.V RXIP RXIN TXOP TXON XTLP XTLN R 0R R 0R (INT) A A A A A +VA +VA V_OUT + C u/v C 0nF C 0nF C 0nF #RESET C 0nF C0 0nF ACTLED LINKLED RSET_BG A NC A RXIP RXIN A TXOP TXON A V VO V A A BITEN TEST_MODE TEST_MODE 0 TEST_MODE TEST_MODE0 OP_MODE0 OP_MODE OP_MODE V DATA DATA DATA 0 DATA DATA DATA DATA DATA V DATA DATA DATA 0 DATA DATA DATA DATA DATA0 V ADDR ADDR ADDR 0 ADDR ADDR ADDR ADDR ADDR ADDR ADDR0 V /WR 0 /RD /CS V /INT /RESET BRDY0 BRDY BRDY BRDY 0 MII_RXC V MII_RXDV MII_RXD0 MII_RXD MII_RXD MII_RXD MII_COL /FDX 0 MII_CRS MII_TXC V /SPDLED(MII_TXD0) /FDXLED(MII_TXD) /COLLED(MII_TXD) /RXLED(MII_TXD) /TXLED(MII_TXEN) /LINKLED 0 OSCI V V XTLN XTLP NC NC NC 0 U W00 +VA +VD C 0nF C 0nF C 0nF C 0nF +VD +VA + C u/v D BAW