CMOS 8-BIT SINGLE CHIP MICROCOMPUTER S1C Technical Manual. S1C88650 Technical Hardware

Transcription

1 CMOS 8-BIT SINGLE CHIP MICROCOMPUTER SC8865 Technical Manual SC8865 Technical Hardware

2 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. SEIKO EPSON CORPORATION 24, All rights reserved.

3 Configuration of product number Devices S C 884 F A Packing specifications : Besides tape & reel A : TCP BL 2 directions B : Tape & reel BACK C : TCP BR 2 directions D : TCP BT 2 directions E : TCP BD 2 directions F : Tape & reel FRONT G : TCP BT 4 directions H : TCP BD 4 directions J : TCP SL 2 directions K : TCP SR 2 directions L : Tape & reel LEFT M : TCP ST 2 directions N : TCP SD 2 directions P : TCP ST 4 directions Q : TCP SD 4 directions R : Tape & reel RIGHT 99 : Specs not fixed Specification Package D: die form; F: QFP Model number Model name C: microcomputer, digital products Product classification S: semiconductor Development tools S5U C D Packing specifications : standard packing Version : Version Tool type Hx : ICE Ex : EVA board Px : Peripheral board Wx : Flash ROM writer for the microcomputer Xx : ROM writer peripheral board Cx : C compiler package Ax : Assembler package Dx : Utility tool by the model Qx : Soft simulator Corresponding model number 88348: for SC88348 Tool classification C: microcomputer use Product classification S5U: development tool for semiconductor products

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5 CONTENTS Contents INTRODUCTION.... Features....2 Block Diagram Pins Pin layout diagram Pin description Mask Option POWER SUPPLY Operating Voltage Internal Power Supply Circuit CPU AND BUS CONFIGURATION CPU Internal Memory Program ROM RAM I/O memory Display memory Kanji font ROM Exception Processing Vectors CC (Customized Condition Flag) Chip Mode MCU mode and MPU mode Bus mode CPU mode External Bus Data bus Address bus Read (RD)/write (WR) signals Chip enable (CE) signal WAIT control Bus authority release state INITIAL RESET Initial Reset Factors RESET terminal Simultaneous LOW level input at input port terminals KK Initial reset sequence Initial Settings After Initial Reset PERIPHERAL CIRCUITS AND THEIR OPERATION I/O Memory Map System Controller and Bus Control Bus mode and CPU mode settings Address decoder (CE output) settings WAIT state settings Setting the bus authority release request signal Stack page setting Control of system controller Programming notes SC8865 TECHNICAL MANUAL EPSON i

6 CONTENTS 5.3 Watchdog Timer Configuration of watchdog timer Interrupt function Control of watchdog timer Programming notes Oscillation Circuits Configuration of oscillation circuits Mask option OSC oscillation circuit OSC3 oscillation circuit Switching the CPU clocks Control of oscillation circuit Programming notes Input Ports (K ports) Configuration of input ports Mask option Pull-up control Interrupt function and input comparison register Control of input ports Programming notes Output Ports (R ports) Configuration of output ports High impedance control DC output Control of output ports I/O Ports (P ports) Configuration of I/O ports Mask option I/O control registers and I/O mode Pull-up control Special output Control of I/O ports Programming notes Serial Interface Configuration of serial interface Switching of terminal functions Transfer modes Clock source Transmit-receive control Operation of clock synchronous transfer Operation of asynchronous transfer Interrupt function Control of serial interface Programming notes Clock Timer Configuration of clock timer Interrupt function Control of clock timer Programming notes Programmable Timer Configuration of programmable timer Operation mode Setting of input clock Operation and control of timer Interrupt function Setting of TOUT output Transfer rate setting of serial interface ii EPSON SC8865 TECHNICAL MANUAL

7 CONTENTS 5..8 Setting frame frequency for LCD driver Control of programmable timer Programming notes LCD Driver Configuration of LCD driver LCD power supply Frame frequency Switching drive duty Display memory Display control Control of LCD driver Programming notes Supply Voltage Detection (SVD) Circuit Configuration of SVD circuit SVD operation Control of SVD circuit Programming notes Heavy Load Protection Function Outline of heavy load protection function Control of heavy load protection function Programming note Interrupt and Standby Status Interrupt generation conditions Interrupt factor flag Interrupt enable register Interrupt priority register and interrupt priority level Exception processing vectors Control of interrupt Programming notes SUMMARY OF NOTES Notes for Low Current Consumption Precautions on Mounting BASIC EXTERNAL WIRING DIAGRAM ELECTRICAL CHARACTERISTICS Absolute Maximum Rating Recommended Operating Conditions DC Characteristics Analog Circuit Characteristics Power Current Consumption AC Characteristics Oscillation Characteristics Characteristics Curves (reference value) PACKAGE Plastic Package Ceramic Package for Test Samples...6 PAD LAYOUT Diagram of Pad Layout Pad Coordinates...62 SC8865 TECHNICAL MANUAL EPSON iii

8 CONTENTS APPENDIX A S5UC88P&S5UC88649P2 MANUAL (Peripheral Circuit Board for SC8865) A. Names and Functions of Each Part...63 A.2 Precautions...65 A.2. Precaution for operation A.2.2 Differences from actual IC A.3 Connecting to the Target System...68 A.4 Product Specifications...7 APPENDIX B USING KANJI FONT iv EPSON SC8865 TECHNICAL MANUAL

9 INTRODUCTION INTRODUCTION The SC8865 is an 8-bit microcomputer for portable equipment with an LCD display that has a built-in LCD controller/driver and a character generator (kanji) ROM. This microcomputer features low-voltage (.8 V) and high-speed (8.2 MHz) operations as well as low-current consumption (2.5 µa during standby). The LCD controller/driver contains an LCD drive power supply circuit and can drive an maximum of dot LCD panel in low-power consumption. The SC8865 has a built-in 2-dot kanji font ROM that contains JIS level- and level-2 kanji sets, other characters and user-defined characters, this makes it possible to display kanji characters without any external kanji font ROM (refer to Appendix B, "USING KANJI FONT"). This 8-bit CPU has up to 6MB accessible address space allowing easy implementation of a large data processing application. The SC8865 is suitable for display modules, portable CD/MD, solid audio players, PDA, data bank and other applications that required an exclusive LCD driver in conventional systems.. Features Table.. lists the features of the SC8865. Table.. Main features Core CPU Main (OSC3) oscillation circuit SC88 (MODEL3) CMOS 8-bit core CPU Crystal oscillation circuit/ceramic oscillation circuit 8.2 MHz (Max.), or CR oscillation circuit 2.2 MHz (Max.) Sub (OSC) oscillation circuit Crystal oscillation circuit khz (Typ.), or CR oscillation circuit 2 khz (Max.) Instruction set 68 types (usable for multiplication and division instructions) Min. instruction execution time.244 µsec/8.2 MHz (2 clock) Internal ROM capacity 48K bytes/program ROM 896K bytes/kanji font ROM (can be used for a program and data ROM when no font data is stored.) Internal RAM capacity 8K bytes/ram 768 bytes/display memory Bus line Address bus: 2 bits (also usable as general output ports when not used for the bus) Data bus: 8 bits (also usable as general I/O ports when not used for the bus) CE signal: 3 bits WR signal: bit (also usable as general output ports when not used for the bus) RD signal: bit Input port 8 bits (4 bits can be used as the source clock inputs for PWM timers and bit as a bus request signal input) Output port 3 bits (when the external bus is used) 26 bits (when the external bus is not used) ( bit can be configured for the bus acknowledge signal output) I/O port 8 bits (when the external bus is used) (shard with serial interface, FOUT and TOUT terminals) 6 bits (when the external bus is not used) Serial interface Timer ch (optional clock synchronous system or asynchronous system) Programmable timer: 6 bits (8 bits 2) 4 ch (with PWM function) Clock timer: ch LCD driver Dot matrix type (supports 6 6/5 8 or 2 2 dot font) 26 segments 32, 6 or 8 commons (/5 bias) Built-in LCD power supply circuit (booster type, 5 potentials) Watchdog timer Supply voltage detection (SVD) circuit Interrupt Supply voltage Current consumption Built-in (8 second cycles) 3 value programmable (.82.7 V) External interrupt: Internal interrupt: Input interrupt Timer interrupt Serial interface interrupt system (8 types) 2 systems (6 types) system (3 types).83.6 V SLEEP mode: µa (Typ.) HALT mode: 2.5 µa (Typ.) 32 khz crystal, LCD OFF µa (Typ.) 32 khz CR, LCD OFF 7.6 µa (Typ.) 32 khz crystal, LCD ON*, VDD = V Run state: 9 µa (Typ.) 32 khz crystal, LCD OFF 5 µa (Typ.) 32 khz CR, LCD OFF 7 µa (Typ.) 8 MHz ceramic, LCD OFF 6 µa (Typ.) 2 MHz CR, LCD OFF 4 µa (Typ.) 32 khz crystal, LCD ON*, VDD = V 9 µa (Typ.) 32 khz crystal, LCD ON*, VDD =.82.5 V, Power voltage booster ON 4 µa (Typ.) 32 khz crystal, SVD ON Supply form QFP22-256pin or chip The current consumption with LCD ON listed above is the value under the conditions of LCDCx = " (all on)", LCx = "FH" and "No panel load". Current consumption increases according to the display contents and panel load. SC8865 TECHNICAL MANUAL EPSON

10 INTRODUCTION.2 Block Diagram Core CPU SC88 OSC, 2 OSC3, 4 Oscillator Interrupt Controller MCU/MPU BREQ (K3) BACK (R33) System Controller Input Port KK2 K3 (BREQ) K4K7 RESET TEST EXCLEXCL3 (K4K7) TOUTTOUT3 (P4, P5) TOUT2/TOUT3 (P7) Reset/Test Watchdog Timer Programmable Timer /Event Counter Clock Timer I/O Port Serial Interface External Memory Interface Output Port P (SIN) P (SOUT) P2 (SCLK) P3 (SRDY) P4 (TOUT/TOUT) P5 (TOUT2/TOUT3) P6 (FOUT) P7 (TOUT2/TOUT3) PP7 (D7) RR7, RR7, R2R23 (AA7, A8A5, A6A9) R24, R25 (RD, WR) R3R32 (CECE2) R33 (BACK) VDD VSS VD V Power Generator LCD Driver SEGSEG25 COMCOM3 VCVC5 CACG Supply Voltage Detector RAM 8K bytes ROM 48K bytes+896k bytes Fig..2. SC8865 block diagram 2 EPSON SC8865 TECHNICAL MANUAL

11 SC8865 TECHNICAL MANUAL EPSON 3 INTRODUCTION.3 Pins.3. Pin layout diagram QFP22-256pin INDEX Pin No. Pin name Pin No. Pin name SEG88 SEG89 SEG9 SEG9 SEG92 SEG93 SEG94 SEG95 SEG96 N.C. N.C. N.C. N.C. N.C. VSS SEG97 SEG98 SEG99 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG2 SEG2 SEG22 SEG23 SEG24 SEG25 COM3 COM3 COM29 COM28 COM27 COM26 COM25 COM24 N.C. N.C. TEST SEG39 SEG4 SEG4 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG5 SEG5 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG6 SEG6 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG7 SEG7 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG8 SEG8 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 Pin No. Pin name COM23 COM22 COM2 COM2 COM9 COM8 COM7 COM6 V CG CF CE CD CC CB CA VC5 VC4 VC3 VC2 VC N.C. N.C. N.C. N.C. N.C. VDD OSC3 OSC4 VSS VD OSC OSC2 TEST RESET MCU/MPU K7/EXCL3 K6/EXCL2 K5/EXCL K4/EXCL K3/BREQ K2 K K P7/TOUT2/TOUT3 P6/FOUT P5/TOUT2/TOUT3 P4/TOUT/TOUT P3/SRDY P2/SCLK P/SOUT P/SIN Pin No. Pin name P7/D7 P6/ P5/ P4/D4 P3/D3 P2/ P/D P/ R/A R/A R2/A2 R3/A3 R4/A4 R5/A5 R6/A6 R7/A7 R/A8 R/A9 R2/A R3/A R4/A2 R5/A3 R6/A4 R7/A5 R2/A6 R2/A7 R22/A8 R23/A9 R24/RD R25/WR R3/CE R3/CE VDD N.C. N.C. N.C. N.C. N.C. VSS R32/CE2 R33/BACK COM COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM Pin No. Pin name COM COM2 COM3 COM4 COM5 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG2 SEG2 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG3 SEG3 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 VSS N.C. N.C. N.C Fig..3.. SC8865 pin layout

12 INTRODUCTION.3.2 Pin description VDD VSS VD V VCVC5 CACG OSC OSC2 OSC3 OSC4 MCU/MPU KK2 K3/BREQ K4/EXCL K5/EXCL K6/EXCL2 K7/EXCL3 RR7/AA7 RR7/A8A5 R2R23/A6A9 R24/RD R25/WR R3R32/CECE2 R33 (BACK) PP7/D7 P/SIN P/SOUT P2/SCLK P3/SRDY P4/TOUT/TOUT P5/TOUT2/TOUT3 P6/FOUT P7/TOUT2/TOUT3 COMCOM3 SEGSEG25 RESET TEST TEST Table.3.2. SC8865 pin description Pin name Pin No. In/Out Function 3, 89 67, 34, 95, I 37 O 32 I 33 O 4 I 4846 I 45 I 44 I 43 I 42 I 4 I 6572 O 738 O 884 O 85 O 86 O 87, 88, 96 O 97 O 6457 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O , , 46, I/O I/O I/O O O I I Power supply (+) terminal Power supply (GND) terminal Internal logic system and oscillation system voltage regulator output terminals LCD circuit power voltage booster output terminal LCD drive voltage output terminals LCD and power voltage booster capacitor connection terminals OSC oscillation input terminal (select crystal/cr oscillation by mask option) OSC oscillation output terminal OSC3 oscillation input terminal (select crystal/ceramic/cr oscillation by mask option) OSC3 oscillation output terminal MCU/MPU mode setup terminal Input terminals (KK2) Input terminal (K3) or bus request signal input terminal (BREQ) Input terminal (K4) or programmable timer external clock input terminal (EXCL) Input terminal (K5) or programmable timer external clock input terminal (EXCL) Input terminal (K6) or programmable timer external clock input terminal (EXCL2) Input terminal (K7) or programmable timer external clock input terminal (EXCL3) Output terminals (RR7) or address bus (AA7) Output terminals (RR7) or address bus (A8A5) Output terminals (R2R23) or address bus (A6A9) Output terminal (R24) or read signal output terminal (RD) Output terminal (R25) or write signal output terminal (WR) Output terminals (R3R32) or chip enable signal output terminals (CECE2) Output terminal (R33) or bus acknowledge signal output terminal (BACK) I/O terminals (PP7) or data bus (D7) I/O terminal (P) or serial I/F data input terminal (SIN) I/O terminal (P) or serial I/F data output terminal (SOUT) I/O terminal (P2) or serial I/F clock I/O terminal (SCLK) I/O terminal (P3) or serial I/F ready signal output terminal (SRDY) I/O terminal (P4) or programmable timer underflow signal output terminal (TOUT/TOUT) I/O terminal (P5) or programmable timer underflow signal output terminal (TOUT2/TOUT3) I/O terminal (P6) or clock output terminal (FOUT) I/O terminal (P7) or programmable timer underflow inverted signal output terminal (TOUT2/TOUT3) LCD common output terminals LCD segment output terminals Initial reset input terminal Test input terminal Test terminal (open during normal operation) 4 EPSON SC8865 TECHNICAL MANUAL

13 INTRODUCTION.4 Mask Option Mask options shown below are provided for the SC8865. Several hardware specifications are prepared in each mask option, and one of them can be selected according to the application. Multiple specifications are available in each option item as indicated in the Option List. Select the specifications that meet the target system and check the appropriate box. The option selection is done interactively on the screen during function option generator winfog execution, using this option list as reference. Mask pattern of the IC is finally generated based on the data created by the winfog. Refer to the "S5UC88C Manual II" for details on the winfog. PERIPHERAL CIRCUIT BOARD option list The following shows the options for configuring the Peripheral Circuit Board (S5UC88P with S5UC88649P2) installed in the ICE (S5UC88H5). The selections do not affect the IC's mask option. A OSC SYSTEM CLOCK. Internal Clock 2. User Clock B OSC3 SYSTEM CLOCK. Internal Clock 2. User Clock When User Clock is selected, input a clock to the OSC terminal. When Internal Clock is selected, the clock frequency is changed according to the oscillation circuit selected by the IC's mask option. When User Clock is selected, input a clock to the OSC3 terminal. When Internal Clock is selected, the clock frequency is changed according to the oscillation circuit selected by the IC's mask option. SC8865 mask option list The following shows the option list for generating the IC's mask pattern. Note that the Peripheral Circuit Board installed in the ICE does not support some options. OSC SYSTEM CLOCK. Crystal 2. CR 2 OSC3 SYSTEM CLOCK. Crystal 2. Ceramic 3. CR 3 MULTIPLE KEY ENTRY RESET Combination... Not Use 2. Use K, K 3. Use K, K, K2 4. Use K, K, K2, K3 4 INPUT PORT PULL UP RESISTOR K.... With Resistor 2. Gate Direct K.... With Resistor 2. Gate Direct K2.... With Resistor 2. Gate Direct K3.... With Resistor 2. Gate Direct K4.... With Resistor 2. Gate Direct K5.... With Resistor 2. Gate Direct K6.... With Resistor 2. Gate Direct K7.... With Resistor 2. Gate Direct MCU/MPU.... With Resistor 2. Gate Direct RESET.... With Resistor 2. Gate Direct The specification of the OSC oscillation circuit can be selected from among two types: "Crystal oscillation" and "CR oscillation". Refer to Section 5.4.3, "OSC oscillation circuit", for details. The specification of the OSC3 oscillation circuit can be selected from among three types: "Crystal oscillation", "Ceramic oscillation" and "CR oscillation". Refer to Section 5.4.4, "OSC3 oscillation circuit", for details. This mask option can select whether the multiple key entry reset function is used or not. When the function is used, a combination of the input ports (KK3), which are connected to the keys, can be selected. Refer to Section 4..2, "Simultaneous LOW level input at input port terminals KK3", for details. This mask option can select whether the pull-up resistor for the input (K) port terminal is used or not. It is possible to select for each bit of the input ports. Refer to Section 5.5, "Input Ports (K ports)", for details. Furthermore, a pull-up option is also provided for the MCU/MPU and RESET terminals. SC8865 TECHNICAL MANUAL EPSON 5

14 INTRODUCTION 5 I/O PORT PULL UP RESISTOR P.... With Resistor 2. Gate Direct P.... With Resistor 2. Gate Direct P2.... With Resistor 2. Gate Direct P3.... With Resistor 2. Gate Direct P4.... With Resistor 2. Gate Direct P5.... With Resistor 2. Gate Direct P6.... With Resistor 2. Gate Direct P7.... With Resistor 2. Gate Direct P.... With Resistor 2. Gate Direct P.... With Resistor 2. Gate Direct P2.... With Resistor 2. Gate Direct P3.... With Resistor 2. Gate Direct P4.... With Resistor 2. Gate Direct P5.... With Resistor 2. Gate Direct P6.... With Resistor 2. Gate Direct P7.... With Resistor 2. Gate Direct 6 INPUT PORT INPUT I/F LEVEL K.... CMOS Level 2. CMOS Schmitt K.... CMOS Level 2. CMOS Schmitt K2.... CMOS Level 2. CMOS Schmitt K3.... CMOS Level 2. CMOS Schmitt K4.... CMOS Level 2. CMOS Schmitt K5.... CMOS Level 2. CMOS Schmitt K6.... CMOS Level 2. CMOS Schmitt K7.... CMOS Level 2. CMOS Schmitt 7 I/O PORT INPUT I/F LEVEL P.... CMOS Level P.... CMOS Level P2.... CMOS Level P3.... CMOS Level P4.... CMOS Level P5.... CMOS Level P6.... CMOS Level P7.... CMOS Level 8 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt WATCHDOG TIMER NMI GENERATION CYCLE /fOSC (.75-sec cycle when fosc = 32 khz) /fOSC (.52-sec cycle when fosc = 32 khz) /fOSC (34-sec cycle when fosc = 32 khz) /fOSC (68-sec cycle when fosc = 32 khz) This mask option can select whether the pull-up resistor for the I/O port terminal (it works during input mode) is used or not. It is possible to select for each bit of the I/O ports. Refer to Section 5.7, "I/O Ports (P ports)", for details. This mask option can select the interface level of the input (K) port from either the CMOS level or CMOS Schmitt level. It is possible to select for each bit of the input ports. Refer to Section 5.5, "Input Ports (K ports)", for details. The input port on the ICE (with the Peripheral Circuit Board installed) is fixed to the CMOS level interface regardless of this option selection. This mask option can select the interface level of the I/O (P) port from either the CMOS level or CMOS Schmitt level. It is possible to select for each bit of the I/O ports. Refer to Section 5.7, "I/O Ports (P ports)", for details. The input port on the ICE (with the Peripheral Circuit Board installed) is fixed to the CMOS level interface regardless of this option selection. This mask option can select the NMI generation cycle of the watchdog timer. Refer to Section 5.3., "Configuration of watchdog timer", for details. 6 EPSON SC8865 TECHNICAL MANUAL

15 2 POWER SUPPLY 2 POWER SUPPLY In this section, we will explain the operating voltage and the configuration of the internal power supply circuit of the SC Operating Voltage The SC8865 operating power voltage is as follows:.8 V to 3.6 V 2.2 Internal Power Supply Circuit The SC8865 incorporates the power supply circuit shown in Figure When voltage within the range described above is supplied to VDD (+) and VSS (GND), all the voltages needed for the internal circuit are generated internally in the IC. Roughly speaking, the power supply circuit is divided into three sections. Table 2.2. Power supply circuit Circuit Oscillation circuits, Internal circuits LCD system voltage regulator LCD driver Power supply circuit Internal logic voltage regulator Power voltage booster LCD system voltage regulator Output voltage VD VDD or V VCVC5 The internal logic voltage regulator generates the operating voltage <VD> for driving the internal logic circuits and the oscillation circuit. The VD voltage value is fixed at.8 V (Typ.). The power voltage booster generates the operating voltage <V> for the LCD system voltage regulator. External power supply VDD VD Internal logic voltage regulator Either <VDD> or <V> can be selected as the power source for the LCD system voltage regulator according to the <VDD> power supply voltage level. Table Power source for LCD system voltage regulator Supply voltage VDD.82.5 V V Power source for LCD system voltage regulator V VDD The V voltage is about double the VDD voltage level. Refer to Chapter 8, "ELECTRICAL CHARACTERISTICS", for details. The LCD system voltage regulator generates the / 5-bias LCD drive voltages <VC>, <VC2>, <VC3>, <VC4> and <VC5>. See Chapter 8, "ELECTRICAL CHARACTERISTICS" for the voltage values. In the SC8865, the LCD drive voltage is supplied to the built-in LCD driver which drives the LCD panel connected to the SEG and COM terminals. VD Notes: Under no circumstances should VD,V, VC, VC2, VC3, VC4 and VC5, terminal output be used to drive external circuit. If VDD is used as the power source for the LCD system voltage regulator when VDD is 2.5 V or less, the VC to VC5 voltages cannot be generated within specifications. Oscillation circuit Internal circuit OSC, OSC2 OSC3, OSC4 V CF CG Power voltage booster V VC VC2 VC3 VC4 VC5 CA CB CC CD CE LCD system voltage regulator VCVC5 LCD driver COMCOM3 SEGSEG25 VSS Fig Configuration of power supply circuit SC8865 TECHNICAL MANUAL EPSON 7

16 3 CPU AND BUS CONFIGURATION 3 CPU AND BUS CONFIGURATION In this section, we will explain the CPU, operating mode and bus configuration. 3. CPU The SC8865 utilize the SC88 8-bit core CPU whose resistor configuration, command set, etc. are virtually identical to other units in the family of processors incorporating the SC88. See the "SC88 Core CPU Manual" for the SC88. Specifically, the SC8865 employ the Model 3 SC88 CPU which has a maximum address space of M bytes Internal Memory The SC8865 is equipped with internal ROM and RAM as shown in Figure Small scale applications can be handled by one chip. It is also possible to utilize internal memory in combination with external memory. Furthermore, internal ROM can be disconnected from the bus and the resulting space released for external applications. EFFFFH H FFFFH FFH FD7FH F8H F7FFH D8H D7FFH : CH BFFFH Kanji font ROM (896K bytes) I/O memory Display memory RAM (8K bytes) Unused area ROM (48K bytes) H Fig Internal memory map 3.2. Program ROM The SC8865 has a built-in 48K-byte program ROM. The ROM is allocated to HBFFFH. This ROM areas shown above can be released to external memory depending on the setting of the MCU/MPU terminal. (See "3.5 Chip Mode".) RAM The internal RAM capacity is 8K bytes and is allocated to D8HF7FFH. Even when external memory which overlaps the internal RAM area is expanded, the RAM area is not released to external memory. Access to this area is via internal RAM I/O memory A memory mapped I/O method is employed in the SC8865 for interfacing with internal peripheral circuit. Peripheral circuit control bits and data register are arranged in data memory space. Control and data exchange are conducted via normal memory access. I/O memory is arranged in page : FFHFFFFH area. See Section 5., "I/O Memory Map", for details of the I/O memory. Even when external memory which overlaps the I/ O memory area is expanded, the I/O memory area is not released to external memory. Access to this area is via I/O memory Display memory The SC8865 is equipped with an internal display memory which stores a display data for LCD driver. Display memory is arranged in page : FxH Fx7FH (x = 8DH) in the data memory area. See Section 5., "LCD Driver", for details of the display memory. Like the I/O memory, display memory cannot be released to external memory Kanji font ROM The SC8865 has a built-in kanji font ROM that can be used to store JIS level- and level-2 kanji sets, alphanumeric characters and music shift-jis characters. The kanji font ROM capacity is 896K bytes and is allocated to HEFFFFH. When the kanji font is not used the remaining area or the entire area can be used for a program and data storage area (see the "S5UC88xxxRx Manual" for use of font data). This ROM areas shown above can be released to external memory depending on the setting of the MCU/MPU terminal. (See "3.5 Chip Mode".) 8 EPSON SC8865 TECHNICAL MANUAL

17 3 CPU AND BUS CONFIGURATION 3.3 Exception Processing Vectors H4BH in the program area of the SC8865 is assigned as exception processing vectors. Furthermore, from 4EH to FFH, software interrupt vectors are assignable to any two bytes which begin with an even address. Table 3.3. lists the vector addresses and the exception processing factors to which they correspond. Table 3.3. Exception processing vector table Vector Exception processing factor Priority address H 2H 4H 6H 8H AH CH EH H 2H 4H 6H 8H AH CH EH 2H 22H 24H 26H 28H 2AH 2CH 2EH 3H 32H 34H 36H 38H 3AH 3CH 3EH 4H 42H 44H 46H 48H 4AH 4CH 4EH : FEH Reset Zero division Watchdog timer (NMI) K7 input interrupt K6 input interrupt K5 input interrupt K4 input interrupt K3 input interrupt K2 input interrupt K input interrupt K input interrupt PTM underflow interrupt PTM compare match interrupt PTM underflow interrupt PTM compare match interrupt PTM 2 underflow interrupt PTM 2 compare match interrupt PTM 3 underflow interrupt PTM 3 compare match interrupt System reserved (cannot be used) Serial I/F error interrupt Serial I/F receiving complete interrupt Serial I/F transmitting complete interrupt System reserved (cannot be used) System reserved (cannot be used) System reserved (cannot be used) Clock timer 32 Hz interrupt Clock timer 8 Hz interrupt Clock timer 2 Hz interrupt Clock timer Hz interrupt PTM 4 underflow interrupt PTM 4 compare match interrupt PTM 5 underflow interrupt PTM 5 compare match interrupt PTM 6 underflow interrupt PTM 6 compare match interrupt PTM 7 underflow interrupt PTM 7 compare match interrupt System reserved (cannot be used) Software interrupt High Low No priority rating For each vector address and the address after it, the start address of the exception processing routine is written into the subordinate and super ordinate sequence. When an exception processing factor is generated, the exception processing routine is executed starting from the recorded address. When multiple exception processing factors are generated at the same time, execution starts with the highest priority item. The priority sequence shown in Table 3.3. assumes that the interrupt priority levels are all the same. The interrupt priority levels can be set by software in each system. (See Section 5.4, "Interrupt and Standby Status".) Note: For exception processing other than reset, SC (system condition flag) and PC (program counter) are evacuated to the stack and branches to the exception processing routines. Consequently, when returning to the main routine from exception processing routines, please use the RETE instruction. See the "SC88 Core CPU Manual" for information on CPU operations when an exception processing factor is generated. 3.4 CC (Customized Condition Flag) The SC8865 does not use the customized condition flag (CC) in the core CPU. Accordingly, it cannot be used as a branching condition for the conditional branching instruction (JRS, CARS). 3.5 Chip Mode 3.5. MCU mode and MPU mode The chip operating mode can be set to one of two settings using the MCU/MPU terminal. MCU mode...set the MCU/MPU terminal to HIGH Switch to this setting when using internal ROM. With respect to areas other than internal memory, external memory can even be expanded. See Section 3.5.2, "Bus mode", for the memory map. In the MCU mode, during initial reset, only systems in internal memory are activated. Internal program ROM is normally fixed as the top portion of the program memory from the common area (logical space H7FFFH). Exception processing vectors are assigned in internal program ROM. Furthermore, the application initialization routines that start with reset exception processing must likewise be written to internal program ROM. Since bus and other settings which correlate with external expanded memory can be executed in software, this processing is executed in the initialization routine written to internal program ROM. Once these bus mode settings are made, external memory can be accessed. SC8865 TECHNICAL MANUAL EPSON 9

18 3 CPU AND BUS CONFIGURATION When accessing internal memory in this mode, the chip enable (CE) and read (RD)/write (WR) signals are not output to external memory, and the data bus (D7) goes into high impedance status (or pull-up status). Consequently, in cases where addresses overlap in external and internal memory, the areas in external memory will be unavailable. MPU mode...set the MCU/MPU terminal to LOW Internal ROM area is released to an external device source. Internal ROM then becomes unusable and when this area is accessed, chip enable (CE) and read (RD)/write (WR) signals are output to external memory and the data bus (D7) become active. These signals are not output to an external source when other areas of internal memory are accessed. In the MPU mode, the system is activated by external memory. When employing this mode, the exception processing vectors and initialization routine must be assigned within the common area (H7FFFH). You can select whether to use the built-in pull-up resistor of the MCU/MPU terminal by the mask option. Iput port pull-up resistor MCU/MPU... With resistor Gate direct Notes: Setting of MCU/MPU terminal is latched at the rising edge of a reset signal input from the RESET terminal. Therefore, if the setting is to be changed, the RESET terminal must be set to LOW level once again. The data bus while the CPU accesses to the internal memory can be select into highimpedance status or pulled up to high using the pull-up control register and mask option. See Section 5.7, "I/O Ports (P ports)", for details Bus mode In order to set bus specifications to match the configuration of external expanded memory, two different bus modes described below are selectable in software. Single chip mode EFFFFH H FFFFH FFH FD7FH F8H F7FFH D8H D7FFH : CH BFFFH H - MCU mode - Kanji font ROM (896K bytes) I/O memory Display memory Internal RAM Unused area Internal ROM Fig Memory map for the single chip mode The single chip mode setting applies when the SC8865 is used as a single chip microcomputer without external expanded memory. Since this mode employs internal ROM, the system can only be operated in the MCU mode discussed in Section In the MPU mode, the system cannot be set to the single chip mode. Since there is no need for an external bus line in this mode, terminals normally set for bus use can be used as general purpose output ports or I/O ports. Expansion mode The expansion mode setting applies when the SC8865 is used with less than M bytes 3 of external expanded memory. This mode is usable regardless of the MCU/MPU mode setting. Because internal ROM is being used in the MCU mode, external memory in this model can be assigned to the area from H to 3FFFFFH. Since the internal ROM area is released in the MPU mode, external memory in this model can be assigned to the area from H to 2FFFFFH. However, the area from CH to FFFFH is assigned to internal memory and cannot be used to access an external device. EPSON SC8865 TECHNICAL MANUAL

19 3 CPU AND BUS CONFIGURATION 3FFFFFH : H FH EFFFFH H FFFFH D8H D7FFH : CH BFFFH - MCU mode - External memory area Unused area Internal memory Unused area - MPU mode - External memory area Internal memory 2FFFFFH 3.6 External Bus The SC8865 has bus terminals that can address a maximum of M 3 bytes and memory (and other) devices can be externally expanded according to the range of each bus mode described in the previous section. SC8865 BREQ BACK RD WR CE CE CE2 Address bus (AA9) Data bus (D7) External device External device Fig External bus lines External device Internal memory External memory area Below is an explanation of external bus terminals. For information on control methods, see Section 5.2, "System Controller and Bus Control". H See Figure 3.2. for the internal memory Fig Memory map for the expansion mode There is an explanation on how all these settings are actually made in "5.2 System Controller and Bus Control" of this Manual CPU mode The CPU allows software to select its operating mode from two types shown below according to the programming area size. Minimum mode The program area is configured within 64K bytes in any one-bank. However, the bank to be used must be specified in the CB register and cannot be changed after an initialization. This mode does not push the CB register contents onto the stack when a subroutine is called. It makes it possible to economize on stack area usage. This mode is suitable for small- to midscale program memory and large-scale data memory systems. Maximum mode The program area can be configured exceeding 64K bytes. However the CB register must be setup when the program exceeds a bank boundary every 64K bytes. This mode pushes the CB register contents when a subroutine is called. This mode is suitable for large-scale program and data memory systems Data bus The SC8865 possesses an 8-bit external data bus (D7). The terminals and I/O circuits of data bus D7 are shared with I/O ports PP7, switching between these functions being determined by the bus mode setting. In the single chip mode, the 8-bit terminals are all set as I/O ports PP7 and in the expansion mode, they are set as data bus (D7). When set as data bus, the data register and I/O control register of each I/O port are detached from the I/O circuits and usable as a general purpose data register with read/write capabilities. The data bus can be pulled up to high during input mode using the built-in pull-up resistor. This pullup resistor is enabled or disabled using the pull-up control register and mask option. See "5.7 I/O Ports" for details. Bus mode Single chip I/O port P P P2 P3 P4 P5 P6 P7 Data bus D D3 D4 D7 Bus mode Expansion Fig Correspondence between data bus and I/O ports SC8865 TECHNICAL MANUAL EPSON

20 3 CPU AND BUS CONFIGURATION Address bus The SC8865 possesses a 2-bit external address bus AA9. The terminals and output circuits of address bus AA9 are shared with output ports RR7 (=AA7), RR7 (=A8A5) and R2 R23 (=A6A9), switching between these functions being determined by the bus mode setting. In the single chip mode, the 2-bit terminals are all set as output ports RR7, RR7 and R2R23. In the expansion mode, all of the 2-bit terminals are set as the address bus (AA9). When set as an address bus, the data register and high impedance control register of each output port are detached from the output circuit and used as a general purpose data register with read/write capabilities. Bus mode Single chip Output port R R R2 R3 R4 R5 R6 R7 R R R2 R3 R4 R5 R6 R7 R2 R2 R22 R23 Address bus A A A2 A3 A4 A5 A6 A7 A8 A9 A A A2 A3 A4 A5 A6 A7 A8 A9 Bus mode Expansion Fig Correspondence between address bus and output ports Read (RD)/write (WR) signals The output terminals and output circuits for the read (RD)/write (WR) signals directed to external devices are shared respectively with output ports R24 and R25, switching between these functions being determined by the bus mode setting. In the single chip mode, both of these terminals are set as output port terminals and in the expansion mode, they are set as read (RD)/write (WR) signal output terminals. When set as read (RD)/write (WR) signal output terminal, the data register and high impedance control register for each output port (R24, R25) are detached from the output circuit and is usable as a general purpose data register with read/write capabilities. See Section 3.6.5, "WAIT control", for the output timing of the signal. Bus mode Single chip Output port R24 R25 RD/WR signal RD WR Bus mode Expansion Fig Correspondence between read (RD)/ write (WR) signal and output ports Chip enable (CE) signal The SC8865 is equipped with address decoders which can output three different chip enable (CE) signals. Consequently, three devices equipped with a chip enable (CE) or chip select (CS) terminal can be directly connected without setting the address decoder to an external device. The three chip enable (CECE2) signal output terminals and output circuits are shared with output ports R3R32 and in the expansion mode, either the chip enable (CE) output or general output can be selected in software for each of the three bits. When set for chip enable (CE) output, the data register and high impedance control register for each output port are detached from the output circuit and is usable as general purpose data register with read/write capabilities. In the single chip mode, these terminals are set as output ports R3R32. Bus mode Output port R3 R3 R32 CE signal Bus mode CE Single CE Expansion chip CE2 Fig Correspondence between CE signals and output ports Table shows the address ranges which are assigned to the chip enable (CE) signal in the expansion mode. 2 EPSON SC8865 TECHNICAL MANUAL

21 CE signal CE CE CE2 Table CECE2 address settings Address range (expansion mode) MCU mode 3H3FFFFFH HFFFFFH 2H2FFFFFH When accessing the internal memory area, the CE signal is not output. Care should be taken here because the address range for these portions of memory involves irregular settings. The arrangement of memory space for external devices does not necessarily have to be continuous from a subordinate address and any of the chip enable signals can be used to assign areas in memory. Note: The CE signals will be inactive status when the chip enters the standby mode (HALT mode or SLEEP mode). See Section 3.6.5, "WAIT control", for the output timing of signal. 3 CPU AND BUS CONFIGURATION MPU mode HD7FFH, HFFFFFH HFFFFFH 2H2FFFFFH Table Selectable WAIT state numbers Selection No Insert states * One state is a /2 cycle of the clock in length. The WAIT states set in software are inserted between bus cycle states T3T4. Note, however, that WAIT states cannot be inserted when an internal register and internal memory are being accessed and when operating with the OSC oscillation circuit (see "5.4 Oscillation Circuits"). Consequently, WAIT state settings are meaningless in the single chip mode. Figure shows the memory read/write timing charts WAIT control In order to insure accessing of external low speed devices during high speed operations, the SC8865 is equipped with a WAIT function which prolongs access time. (See the "SC88 Core CPU Manual" for details of the WAIT function.) The WAIT state numbers to be inserted can be selected in software from a series of 8 as shown in Table CLK AA9 CE CE WR RD T T2 T3 T4 Address T T2 T3 T4 Address D7 Read data Write data Read cycle () No WAIT Write cycle WAIT (4 states inserted) WAIT (4 states inserted) CLK T T2 T3 Tw Tw2 Tw Tw2 T4 T T2 T3 Tw Tw2 Tw Tw2 T4 AA9 CE CE WR RD D7 Address Read data Address Write data Read cycle (2) WAIT state insertion Fig Memory read/write cycle Write cycle SC8865 TECHNICAL MANUAL EPSON 3

22 3 CPU AND BUS CONFIGURATION Bus authority release state The SC8865 is equipped with a bus authority release function on request from an external device so that DMA (Direct Memory Access) transfer can be conducted between external devices. The internal memory cannot be accessed by this function. There are two terminals used for this function: the bus authority release request signal (BREQ) input terminal and the bus authority release acknowledge signal (BACK) output terminal. The BREQ input terminal is shared with input port terminal K3 and the BACK output terminal with output port terminal R33, use with setting to BREQ/BACK terminals done in software. In the single chip mode, or when using a system which does not require bus authority release, set respective terminals as input and output ports. Input BREQ port input K3 Output BACK port output R33 Fig BREQ/BACK terminals When the bus authority release request (BREQ = LOW) is received from an external device, the SC8865 switches the address bus, data bus, RD/ WR signal, and CE signal lines to a high impedance state, outputs a LOW level from the BACK terminal and releases bus authority. As soon as a LOW level is output from the BACK terminal, the external device can use the external bus. When DMA is completed, the external device returns the BREQ terminal to HIGH and releases bus authority. Figure shows the bus authority release sequence. During bus authority release state, internal memory cannot be accessed from the external device. In cases where external memory has areas which overlap areas in internal memory, the external memory areas can be accessed accordance with the CE signal output by the external device. Note: Be careful with the system, such that an external device does not become the bus master, other than during the bus release status. After setting the BREQ terminal to LOW level, hold the BREQ terminal at LOW level until the BACK terminal becomes LOW level. If the BREQ terminal is returned to HIGH level, before the BACK terminal becomes LOW level, the shift to the bus authorization release status will become indefinite. CLK Tw2 T4 T T2 T3 Tw Tw2 T4 Tz Tz2 Tz Tz2 Tz Tz2 Tz Tz2 T T2 T3 AA9 IX HL PC D7 (IX) (IX) ANY WR RD BREQ L L L L H BACK Program exection status Bus authority release status Program exection status LD [HL],[IX] Fig Bus authority release sequence 4 EPSON SC8865 TECHNICAL MANUAL

23 4 INITIAL RESET 4 INITIAL RESET Initial reset in the SC8865 is required in order to initialize circuits. This section of the Manual contains a description of initial reset factors and the initial settings for internal registers, etc. 4. Initial Reset Factors There are two initial reset factors for the SC8865 as shown below. () External initial reset by the RESET terminal (2) External initial reset by the simultaneous LOW level input at input port terminals KK3 (mask option) Figure 4.. shows the configuration of the initial reset circuit. The CPU and peripheral circuits are initialized by means of initial reset factors. When the factor is canceled, the CPU commences reset exception processing. (See the "SC88 Core CPU Manual".) When this occurs, the reset exception processing vector, Bank, HH from program memory is read out and the program (initialization routine) which begins at the readout address is executed. 4.. RESET terminal Initial reset can be done by externally inputting a LOW level to the RESET terminal. Be sure to maintain the RESET terminal at LOW level for the regulation time after the power on to assure the initial reset. (See Section 8.6, "AC Characteristics".) In addition, be sure to use the RESET terminal for the first initial reset after the power is turned on. The RESET terminal is equipped with a pull-up resistor. You can select whether or not to use by mask option. Input port pull-up resistor RESET... With resistor Gate direct Operating clock status OSC3 OSC4 OSC3 oscillation circuit Divider fosc3/,24 Hz Selector OSC OSC2 OSC oscillation circuit Divider fosc/256 Hz Reset release clock K K Input port K Input port K Time authorize circuit Internal initial reset K2 Input port K R Q K3 Input port K3 SLEEP status Oscillation stability waiting signal VDD Mask option Reset signal S RESET Fig. 4.. Configuration of initial reset circuit SC8865 TECHNICAL MANUAL EPSON 5

24 4 INITIAL RESET 4..2 Simultaneous LOW level input at input port terminals KK3 Another way of executing initial reset externally is to input a LOW level simultaneously to the input ports (KK3) selected by mask option. Since there is a built-in time authorize circuit, be sure to maintain the designated input port terminal at LOW level for 65536/fOSC seconds (two seconds when the oscillation frequency is fosc = khz) or more to perform the initial reset by means of this function. However, the time authorize circuit is bypassed during the SLEEP (standby) status and oscillation stabilization waiting period, and initial reset is executed immediately after the simultaneous LOW level input to the designated input ports. The combination of input ports (KK3) that can be selected by mask option are as follows: Multiple key entry reset Not use K & K K & K & K2 K & K & K2 & K3 For instance, let's say that mask option "K & K & K2 & K3" is selected, when the input level at input ports KK3 is simultaneously LOW, initial reset will take place. When using this function, make sure that the designated input ports do not simultaneously switch to LOW level while the system is in normal operation Initial reset sequence After cancellation of the LOW level input to the RESET terminal, when the power is turned on, the start-up of the CPU is held back until the oscillation stabilization waiting time (52/fOSC3 sec.) have elapsed. Figure shows the operating sequence following initial reset release. The CPU starts operating in synchronization with the OSC3 clock after reset status is released. Also, when using the initial reset by simultaneous LOW level input into the input port, you should be careful of the following points. () During SLEEP status, since the time authorization circuit is bypassed, an initial reset is triggered immediately after a LOW level simultaneous input value. In this case, the CPU starts after waiting the oscillation stabilization time, following cancellation of the LOW level simultaneous input. (2) Other than during SLEEP status, an initial reset will be triggered 65536/fOSC3 seconds after a LOW level simultaneous input. In this case, since a reset differential pulse (64/fOSC seconds) is generated within the SC8865, the CPU will start even if the LOW level simultaneous input status is not canceled. Note: The oscillation stabilization time described in this section does not include oscillation start time. Therefore the time interval until the CPU starts executing instructions after power is turned on or SLEEP status is cancelled may be longer than that indicated in the figure below. fosc3 Reset signal Reset release Reset release clock Internal initial reset Internal initial reset release Internal address bus PC PC PC - Internal data bus Dummy Dummy VECL Internal read signal 52/fOSC3 [sec] Oscillation stable waiting time Dummy cycle Reset exception processing Reset status is maintained during this period. Fig Initial reset sequence 6 EPSON SC8865 TECHNICAL MANUAL

25 4 INITIAL RESET 4.2 Initial Settings After Initial Reset The CPU internal registers are initialized as follows during initial reset. Table 4.2. Initial settings Register name Code Bit length Setting value Data register A Data register B Index (data) register L Index (data) register H Index register IX Index register IY Program counter Stack pointer Base register Zero flag Carry flag Overflow flag Negative flag Decimal flag Unpack flag Interrupt flag Interrupt flag New code bank register Code bank register Expand page register Expand page register for IX Expand page register for IY A B L H IX IY PC SP BR Z C V N D U I I NB CB EP XP YP Undefined Undefined Undefined Undefined Undefined Undefined Undefined* Undefined Undefined H Undefined* H H H * Reset exception processing loads the preset values stored in bank, HH into the PC. At the same time, H of the NB initial value is loaded into CB. Initialize the registers which are not initialized at initial reset using software. Since the internal RAM and display memory are not initialized at initial reset, be sure to initialize using software. The respectively stipulated initializations are done for internal peripheral circuits. If necessary, the initialization should be done using software. For initial value at initial reset, see the sections on the I/O memory map and peripheral circuit descriptions in the following chapter of this manual. SC8865 TECHNICAL MANUAL EPSON 7

26 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) 5 PERIPHERAL CIRCUITS AND THEIR OPERATION The peripheral circuits of the SC8865 is interfaced with the CPU by means of the memory mapped I/O method. For this reason, just as with other memory access operations, peripheral circuits can be controlled by manipulating I/O memory. Below is a description of the operation and control method for each individual peripheral circuit. 5. I/O Memory Map WT D4 WT WT2 Table 5..(a) I/O Memory map (FFHFF3H) Address Bit Name Function SR Comment FF (MCU) D7 BUSMOD Bus mode CPUMOD CPU mode Expansion Maximum Single chip Minimum D4 D3 register register register Reserved register CE2 CE2 (R32) CE signal output Enable/Disable CE2 enable CE2 disable In Single chip mode, D CE CE (R3) Enable: CE signal output CE enable CE disable these setting are fixed CE CE (R3) Disable: DC (R3x) output CE enable CE disable at DC output. FF (MPU) D7 BUSMOD Bus mode CPUMOD CPU mode Expansion Maximum Minimum R Expansion mode only D4 D3 register register register Reserved register CE2 CE2 (R32) CE signal output Enable/Disable CE2 enable CE2 disable D CE CE (R3) Enable: CE signal output CE enable CE disable CE CE (R3) Disable: DC (R3x) output CE enable CE disable FF D7 D4 SPP7 SPP6 SPP5 SPP4 Stack pointer page address < SP page allocatable address > Single chip mode: only page (MSB) D3 D SPP3 SPP2 SPP Expansion mode: 27H page SPP (LSB) FF2 D7 EBR Bus release enable register K3 BREQ Input port (K3 and R33 terminal specification) R33 BACK Output port WT2 Wait control register Number of state WT WT No wait D3 CLKCHG CPU operating clock switch OSC3 OSC D SOSC3 OSC3 oscillation On/Off control register register On Off Reserved register FF3 D7 Constantly "" when being read D4 D3 D VDSEL Power source select for LCD voltage regulator V VDD DBON Power voltage booster On/Off control On Off Note: All the interrupts including NMI are disabled, until you write the optional value into both the "FFH" and "FFH" addresses. 8 EPSON SC8865 TECHNICAL MANUAL

27 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(b) I/O Memory map (FFHFF4H) Address Bit Name Function SR Comment FF D7 HLMOD Heavy load protection mode On Off SEGREV Reverse SEG assignment Reverse Normal D4 D3 DTFNT register register register LCD dot font selection /5 8 Reserved register D LDUTY LCD drive duty selection LDUTY LDUTY Duty Not allowed LDUTY /6 /32 /8 FF D7 FRMCS DSPAR LCDC LCD frame signal source clock selection LCD display memory area selection LCD display control LCDC LCDC LCD display All LCDs lit D4 LCDC All LCDs out Normal display Drive off D3 LC3 LCD contrast adjustment LC2 LC3 LC2 LC LC Contrast Dark D LC : : : : : : LC Light FF2 D7 SVDDT SVD detection data D4 SVDON SVD circuit On/Off D3 SVDS3 SVD criteria voltage setting SVDS2 SVDS3 SVDS2 SVDS SVDS (V) Voltage 2.7 D SVDS SVDS : : : : :.8 FF4 D7 PRPRT Programmable timer clock control PST2 Programmable timer division ratio PST2 PST PST (OSC3) (OSC) fosc3 / 496 fosc / 28 PST fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 D4 PST fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / D3 PRPRT Programmable timer clock control PST2 Programmable timer division ratio PST2 PST PST (OSC3) (OSC) fosc3 / 496 fosc / 28 D PST fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 PST fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / PTM fosc Display area Display area Low On On On Normal Off Off Off These bits are reset to (, ) when SLP instruction is executed. Constantly "" when being read R SC8865 TECHNICAL MANUAL EPSON 9

28 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(c) I/O Memory map (FF5HFF8H) Address Bit Name Function SR Comment FF5 D7 PRPRT3 Programmable timer 3 clock control On Off PST32 Programmable timer 3 division ratio PST32 PST3 PST3 (OSC3) (OSC) fosc3 / 496 fosc / 28 PST3 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 D4 PST3 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / D3 PRPRT2 Programmable timer 2 clock control PST22 Programmable timer 2 division ratio PST22 PST2 PST2 (OSC3) (OSC) fosc3 / 496 fosc / 28 D PST2 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 PST2 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / FF7 D7 D4 register D3 PRTF3 Programmable timer 3 source clock selection PRTF2 Programmable timer 2 source clock selection D PRTF Programmable timer source clock selection PRTF Programmable timer source clock selection FF8 D7 PRPRT5 Programmable timer 5 clock control PST52 PST5 D4 PST5 Programmable timer 5 division ratio PST52 PST5 PST5 (OSC3) (OSC) fosc3 / 496 fosc / 28 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / D3 PRPRT4 Programmable timer 4 clock control PST42 Programmable timer 4 division ratio PST42 PST4 PST4 (OSC3) (OSC) fosc3 / 496 fosc / 28 D PST4 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 PST4 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / On fosc fosc fosc fosc On On Off fosc3 fosc3 fosc3 fosc3 Off Off Constantly "" when being read Reserved register 2 EPSON SC8865 TECHNICAL MANUAL

29 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(d) I/O Memory map (FF9HFF22H) Address Bit Name Function SR Comment FF9 D7 PRPRT7 Programmable timer 7 clock control On Off PST72 Programmable timer 7 division ratio PST72 PST7 PST7 (OSC3) (OSC) fosc3 / 496 fosc / 28 PST7 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 D4 PST7 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / D3 PRPRT6 Programmable timer 6 clock control PST62 Programmable timer 6 division ratio PST62 PST6 PST6 (OSC3) (OSC) fosc3 / 496 fosc / 28 D PST6 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 PST6 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / FFB D7 D4 D3 PRTF7 Programmable timer 7 source clock selection PRTF6 Programmable timer 6 source clock selection D PRTF5 Programmable timer 5 source clock selection PRTF4 Programmable timer 4 source clock selection FF2 D7 PK KK7 interrupt priority register PK PSIF Serial interface interrupt priority register D4 PSIF D3 D PTM Clock timer interrupt priority register PTM FF2 D7 PPT3 D4 PPT2 D3 PPT PPT D FF22 D7 D4 D3 ETM32 ETM8 D ETM2 ETM Programmable timer 32 interrupt priority register Programmable timer interrupt priority register Clock timer 32 Hz interrupt enable register Clock timer 8 Hz interrupt enable register Clock timer 2 Hz interrupt enable register Clock timer Hz interrupt enable register On fosc fosc fosc fosc PK PSIF PTM PPT3 PPT Interrupt enable PK PSIF PTM PPT2 PPT Off fosc3 fosc3 fosc3 fosc3 Priority level Level 3 Level 2 Level Level Priority level Level 3 Level 2 Level Level Priority level Level 3 Level 2 Level Level Interrupt disable Constantly "" when being read Constantly "" when being read Constantly "" when being read Constantly "" when being read Constantly "" when being read SC8865 TECHNICAL MANUAL EPSON 2

30 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(e) I/O Memory map (FF23HFF28H) Address Bit Name Function SR FF23 D7 D4 D3 ESERR Serial I/F (error) interrupt enable register Interrupt Interrupt D ESREC Serial I/F (receiving) interrupt enable register enable disable ESTRA Serial I/F (transmitting) interrupt enable register FF24 D7 EK7 K7 interrupt enable EK6 K6 interrupt enable EK5 K5 interrupt enable D4 EK4 K4 interrupt enable Interrupt Interrupt D3 EK3 K3 interrupt enable enable disable EK2 K2 interrupt enable D EK K interrupt enable EK K interrupt enable FF25 D7 ETC3 PTM3 compare match interrupt enable ETU3 PTM3 underflow interrupt enable ETC2 PTM2 compare match interrupt enable D4 ETU2 PTM2 underflow interrupt enable Interrupt Interrupt D3 ETC PTM compare match interrupt enable enable disable ETU PTM underflow interrupt enable D ETC PTM compare match interrupt enable ETU PTM underflow interrupt enable FF26 D7 D4 D3 FTM32 Clock timer 32 Hz interrupt factor flag (R) (R) FTM8 Clock timer 8 Hz interrupt factor flag Generated Not generated D FTM2 Clock timer 2 Hz interrupt factor flag (W) (W) FTM Clock timer Hz interrupt factor flag Reset No operation FF27 D7 D4 D3 FSERR Serial I/F (error) interrupt factor flag (R) (R) Generated Not generated D FSREC Serial I/F (receiving) interrupt factor flag (W) (W) FSTRA Serial I/F (transmitting) interrupt factor flag Reset No operation FF28 D7 FK7 K7 interrupt factor flag (R) (R) FK6 K6 interrupt factor flag Interrupt No interrupt FK5 K5 interrupt factor flag factor is factor is D4 FK4 K4 interrupt factor flag generated generated D3 FK3 K3 interrupt factor flag FK2 K2 interrupt factor flag (W) (W) D FK K interrupt factor flag Reset No operation FK K interrupt factor flag Comment Constantly "" when being read Constantly "" when being read Constantly "" when being read 22 EPSON SC8865 TECHNICAL MANUAL

31 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(f) I/O Memory map (FF29HFF3H) Address Bit Name Function SR Comment FF29 D7 FTC3 FTU3 FTC2 PTM3 compare match interrupt factor flag PTM3 underflow interrupt factor flag PTM2 compare match interrupt factor flag (R) Interrupt factor is (R) No interrupt factor is D4 FTU2 PTM2 underflow interrupt factor flag generated generated D3 FTC PTM compare match interrupt factor flag D FTU FTC PTM underflow interrupt factor flag PTM compare match interrupt factor flag (W) Reset (W) No operation FTU PTM underflow interrupt factor flag FF2A D7 D4 Constantly "" when being read D3 PPT7 Programmable timer 76 interrupt PPT7 PPT6 Priority PPT5 PPT4 level PPT6 priority register Level 3 D PPT5 Programmable timer 54 interrupt Level 2 Level PPT4 priority register Level FF2C D7 ETC7 ETU7 ETC6 PTM7 compare match interrupt enable PTM7 underflow interrupt enable PTM6 compare match interrupt enable D4 ETU6 PTM6 underflow interrupt enable Interrupt Interrupt D3 ETC5 PTM5 compare match interrupt enable enable disable D ETU5 ETC4 ETU4 PTM5 underflow interrupt enable PTM4 compare match interrupt enable PTM4 underflow interrupt enable FF2E D7 FTC7 FTU7 FTC6 PTM7 compare match interrupt factor flag PTM7 underflow interrupt factor flag PTM6 compare match interrupt factor flag (R) Interrupt factor is (R) No interrupt factor is D4 FTU6 PTM6 underflow interrupt factor flag generated generated D3 FTC5 PTM5 compare match interrupt factor flag D FTU5 FTC4 FTU4 PTM5 underflow interrupt factor flag PTM4 compare match interrupt factor flag PTM4 underflow interrupt factor flag (W) Reset (W) No operation FF3 D7 MODE6_A PTM 8/6-bit mode selection PTNREN_A External clock noise rejecter selection 6-bit x Enable 8-bit x 2 Disable D4 register "" when being read Reserved register D3 PTOUT PTM clock output control PTRUN PTM Run/Stop control On Run Off Stop D PSET PTM preset Preset No operation W "" when being read CKSEL PTM input clock selection External clock Internal clock FF3 D7 D4 register Constantly "" when being read Reserved register D3 PTOUT PTM clock output control PTRUN PTM Run/Stop control On Run Off Stop D PSET PTM preset Preset No operation W "" when being read CKSEL PTM input clock selection External clock Internal clock SC8865 TECHNICAL MANUAL EPSON 23

32 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(g) I/O Memory map (FF32HFF37H) Address Bit Name Function SR Comment FF32 D7 RDR7 RDR6 RDR5 PTM reload data D7 (MSB) PTM reload data PTM reload data D4 RDR4 PTM reload data D4 D3 RDR3 PTM reload data D3 High Low D RDR2 RDR RDR PTM reload data PTM reload data D PTM reload data (LSB) FF33 D7 RDR7 RDR6 RDR5 PTM reload data D7 (MSB) PTM reload data PTM reload data D4 RDR4 PTM reload data D4 D3 RDR3 PTM reload data D3 High Low D RDR2 RDR RDR PTM reload data PTM reload data D PTM reload data (LSB) FF34 D7 CDR7 CDR6 CDR5 PTM compare data D7 (MSB) PTM compare data PTM compare data D4 CDR4 PTM compare data D4 D3 CDR3 PTM compare data D3 High Low D CDR2 CDR CDR PTM compare data PTM compare data D PTM compare data (LSB) FF35 D7 CDR7 CDR6 CDR5 PTM compare data D7 (MSB) PTM compare data PTM compare data D4 CDR4 PTM compare data D4 D3 CDR3 PTM compare data D3 High Low D CDR2 CDR CDR PTM compare data PTM compare data D PTM compare data (LSB) FF36 D7 PTM7 PTM6 PTM5 PTM data D7 (MSB) PTM data PTM data D4 PTM4 PTM data D4 D3 PTM3 PTM data D3 High Low R D PTM2 PTM PTM PTM data PTM data D PTM data (LSB) FF37 D7 PTM7 PTM6 PTM5 PTM data D7 (MSB) PTM data PTM data D4 PTM4 PTM data D4 D3 PTM3 PTM data D3 High Low R D PTM2 PTM PTM PTM data PTM data D PTM data (LSB) 24 EPSON SC8865 TECHNICAL MANUAL

33 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(h) I/O Memory map (FF38HFF3DH) Address Bit Name Function SR Comment FF38 D7 MODE6_B PTM23 8/6-bit mode selection 6-bit x 8-bit x 2 PTNREN_B External clock noise rejecter selection Enable Disable D4 D3 RPTOUT2 PTM2 inverted clock output control PTOUT2 PTM2 clock output control PTRUN2 PTM2 Run/Stop control On On Run Off Off Stop D PSET2 PTM2 preset Preset No operation CKSEL2 PTM2 input clock selection External clock Internal clock FF39 D7 D4 D3 RPTOUT3 PTM3 inverted clock output control PTOUT3 PTM3 clock output control PTRUN3 PTM3 Run/Stop control On On Run Off Off Stop D PSET3 PTM3 preset Preset No operation CKSEL3 PTM3 input clock selection External clock Internal clock FF3A D7 RDR27 RDR26 RDR25 PTM2 reload data D7 (MSB) PTM2 reload data PTM2 reload data D4 RDR24 PTM2 reload data D4 D3 RDR23 PTM2 reload data D3 High Low D RDR22 RDR2 RDR2 PTM2 reload data PTM2 reload data D PTM2 reload data (LSB) FF3B D7 RDR37 PTM3 reload data D7 (MSB) RDR36 PTM3 reload data RDR35 PTM3 reload data D4 RDR34 PTM3 reload data D4 D3 RDR33 PTM3 reload data D3 High Low RDR32 PTM3 reload data D RDR3 PTM3 reload data D RDR3 PTM3 reload data (LSB) FF3C D7 CDR27 PTM2 compare data D7 (MSB) CDR26 PTM2 compare data CDR25 PTM2 compare data D4 CDR24 PTM2 compare data D4 D3 CDR23 PTM2 compare data D3 High Low CDR22 PTM2 compare data D CDR2 PTM2 compare data D CDR2 PTM2 compare data (LSB) FF3D D7 CDR37 PTM3 compare data D7 (MSB) CDR36 PTM3 compare data CDR35 PTM3 compare data D4 CDR34 PTM3 compare data D4 D3 CDR33 PTM3 compare data D3 High Low CDR32 PTM3 compare data D CDR3 PTM3 compare data D CDR3 PTM3 compare data (LSB) "" when being read W "" when being read Constantly "" when being read W "" when being read SC8865 TECHNICAL MANUAL EPSON 25

34 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(i) I/O Memory map (FF3EHFF4H) Address Bit Name Function SR Comment FF3E D7 PTM27 PTM26 PTM25 PTM2 data D7 (MSB) PTM2 data PTM2 data D4 PTM24 PTM2 data D4 D3 PTM23 PTM2 data D3 High Low R D PTM22 PTM2 PTM2 PTM2 data PTM2 data D PTM2 data (LSB) FF3F D7 D4 D3 D PTM37 PTM36 PTM35 PTM34 PTM33 PTM32 PTM3 PTM3 FF4 D7 WDEN FOUT2 FOUT D4 FOUT PTM3 data D7 (MSB) PTM3 data PTM3 data PTM3 data D4 PTM3 data D3 PTM3 data PTM3 data D PTM3 data (LSB) Watchdog timer enable FOUT frequency selection FOUT2 FOUT FOUT Frequency fosc3 / 8 fosc3 / 4 fosc3 / 2 fosc3 / fosc / 8 fosc / 4 fosc / 2 fosc / High Enable Low Disable R D3 FOUTON FOUT output control On Off WDRST Watchdog timer reset Reset No operation W Constantly "" when D TMRST Clock timer reset Reset No operation W being read TMRUN Clock timer Run/Stop control Run Stop FF4 D7 TMD7 Clock timer data Hz TM Clock timer data 2 Hz TM Clock timer data 4 Hz D4 D3 TMD4 TMD3 Clock timer data Clock timer data 8 Hz 6 Hz High Low R TM Clock timer data 32 Hz D TMD Clock timer data 64 Hz TM Clock timer data 28 Hz 26 EPSON SC8865 TECHNICAL MANUAL

35 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(j) I/O Memory map (FF48HFF4BH) Address Bit Name Function SR Comment FF48 D7 "" when being read EPR PMD D4 SCS D3 SCS SMD D SM ESIF Parity enable register With parity Non parity Parity mode selection Odd Even Clock source selection SCS SCS Clock source Programmable timer fosc3 / 4 fosc3 / 8 fosc3 / 6 Serial I/F mode selection SMD SM Mode Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master Serial I/F enable register Serial I/F I/O port Only for asynchronous mode In the clock synchronous slave mode, external clock is selected. FF49 D7 "" when being read D4 D3 D FER PER OER RXTRG RXEN TXTRG TXEN Serial I/F framing error flag Serial I/F parity error flag Serial I/F overrun error flag Serial I/F receive trigger/status Serial I/F receive enable Serial I/F transmit trigger/status Serial I/F transmit enable R W R W R W R W R W Error Reset () Error Reset () Error Reset () Run Trigger Enable Run Trigger Enable No error No operation No error No operation No error No operation Stop No operation Disable Stop No operation Disable Only for asynchronous mode FF4A D7 TRXD7 TRX TRX Serial I/F transmit/receive data D7 (MSB) Serial I/F transmit/receive data Serial I/F transmit/receive data D4 TRXD4 Serial I/F transmit/receive data D4 D3 TRXD3 Serial I/F transmit/receive data D3 High Low X D TRX TRXD TRX Serial I/F transmit/receive data Serial I/F transmit/receive data D Serial I/F transmit/receive data (LSB) FF4B D7 D4 D3 Constantly "" when being read D STPB SDP Serial I/F stop bit selection Serial I/F data input/output permutation selection 2 bits MSB first bit LSB first SC8865 TECHNICAL MANUAL EPSON 27

36 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(k) I/O Memory map (FF52HFF6H) Address Bit Name Function SR Comment FF52 D7 KCP7 KCP6 KCP5 K7 input comparison register K6 input comparison register K5 input comparison register Interrupt Interrupt D4 KCP4 K4 input comparison register generated generated D3 KCP3 K3 input comparison register at falling at rising KCP2 K2 input comparison register edge edge D KCP KCP K input comparison register K input comparison register FF54 D7 K7D K6D K5D K7 input port data K6 input port data K5 input port data D4 K4D K4 input port data High level Low level D3 K3D K3 input port data input input R D K2D KD KD K2 input port data K input port data K input port data FF56 D7 PULK7 PULK6 PULK5 K7 pull-up control register K6 pull-up control register K5 pull-up control register D4 PULK4 K4 pull-up control register D3 PULK3 K3 pull-up control register On Off D PULK2 PULK PULK K2 pull-up control register K pull-up control register K pull-up control register FF58 D7 "" when being read CTK2H K4K7 port chattering-eliminate setup (Input level check time) Check time CTK2H CTKH CTKH [sec] CTKH 4/fOSC3 2/fOSC3 /fosc3 496/fOSC D4 CTKH 248/fOSC 52/fOSC 28/fOSC None D3 CTK2L KK3 port chattering-eliminate setup (Input level check time) Check time CTK2L CTKL CTKL [sec] D CTKL 4/fOSC3 2/fOSC3 /fosc3 496/fOSC CTKL 248/fOSC 52/fOSC 28/fOSC None FF6 D7 IOC7 P7 I/O control register IOC6 P6 I/O control register IOC5 P5 I/O control register D4 IOC4 P4 I/O control register D3 IOC3 P3 I/O control register IOC2 P2 I/O control register D IOC P I/O control register IOC P I/O control register Output Input "" when being read 28 EPSON SC8865 TECHNICAL MANUAL

37 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(l) I/O Memory map (FF6HFF7H) Address Bit Name Function SR Comment FF6 D7 IOC7 IOC6 IOC5 P7 I/O control register P6 I/O control register P5 I/O control register D4 IOC4 P4 I/O control register D3 IOC3 P3 I/O control register Output Input D IOC2 IOC IOC P2 I/O control register P I/O control register P I/O control register FF62 D7 P7D P6D P5D P7 I/O port data P6 I/O port data P5 I/O port data D4 P4D P4 I/O port data D3 P3D P3 I/O port data High Low D P2D PD PD P2 I/O port data P I/O port data P I/O port data FF63 D7 P7D P6D P5D P7 I/O port data P6 I/O port data P5 I/O port data D4 P4D P4 I/O port data D3 P3D P3 I/O port data High Low D P2D PD PD P2 I/O port data P I/O port data P I/O port data FF64 D7 PULP7 PULP6 PULP5 P7 pull-up control register P6 pull-up control register P5 pull-up control register D4 PULP4 P4 pull-up control register D3 PULP3 P3 pull-up control register On Off D PULP2 PULP PULP P2 pull-up control register P pull-up control register P pull-up control register FF65 D7 PULP7 PULP6 PULP5 P7 pull-up control register P6 pull-up control register P5 pull-up control register D4 PULP4 P4 pull-up control register D3 PULP3 P3 pull-up control register On Off D PULP2 PULP PULP P2 pull-up control register P pull-up control register P pull-up control register FF7 D7 D4 D3 HZRH register register register register R4R7 high impedance control Reserved register HZRL RR3 high impedance control High Complementary D HZRH R4R7 high impedance control impedance HZRL RR3 high impedance control SC8865 TECHNICAL MANUAL EPSON 29

38 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(m) I/O Memory map (FF7HFF76H) Address Bit Name Function SR Comment FF7 D7 register Reserved register D4 D3 D HZR25 HZR24 HZR23 HZR22 HZR2 HZR2 register R25 high impedance control R24 high impedance control R23 high impedance control R22 high impedance control R2 high impedance control R2 high impedance control High impedance Complementary FF72 D7 register register register D4 register D3 HZR33 R33 high impedance control HZR32 R32 high impedance control High Complementary D HZR3 R3 high impedance control impedance HZR3 R3 high impedance control FF73 D7 R7D R7 output port data R6D R6 output port data R5D R5 output port data D4 R4D R4 output port data D3 R3D R3 output port data High Low R2D R2 output port data D RD R output port data RD R output port data FF74 D7 R7D R7 output port data R6D R6 output port data R5D R5 output port data D4 R4D R4 output port data D3 R3D R3 output port data High Low R2D R2 output port data D RD R output port data RD R output port data FF75 D7 register register R25D R25 output port data D4 R24D R24 output port data D3 R23D R23 output port data R22D R22 output port data High Low D R2D R2 output port data R2D R2 output port data FF76 D7 register register register D4 register D3 R33D R33 output port data R32D R32 output port data D R3D R3 output port data High Low R3D R3 output port data Reserved register Reserved register Reserved register 3 EPSON SC8865 TECHNICAL MANUAL

39 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(n) I/O Memory map (FFBHFFB5H) Address Bit Name Function SR Comment FFB D7 MODE6_C PTM45 8/6-bit mode selection 6-bit x 8-bit x 2 PTNREN_C External clock 2 noise rejecter selection Enable Disable D4 D3 register register PTRUN4 PTM4 Run/Stop control Run Stop D PSET4 PTM4 preset Preset No operation CKSEL4 PTM4 input clock selection External clock Internal clock FFB D7 D4 D3 register register PTRUN5 PTM5 Run/Stop control Run Stop D PSET5 PTM5 preset Preset No operation CKSEL5 PTM5 input clock selection External clock Internal clock FFB2 D7 RDR47 RDR46 RDR45 PTM4 reload data D7 (MSB) PTM4 reload data PTM4 reload data D4 RDR44 PTM4 reload data D4 D3 RDR43 PTM4 reload data D3 High Low D RDR42 RDR4 RDR4 PTM4 reload data PTM4 reload data D PTM4 reload data (LSB) FFB3 D7 RDR57 PTM5 reload data D7 (MSB) RDR56 PTM5 reload data RDR55 PTM5 reload data D4 RDR54 PTM5 reload data D4 D3 RDR53 PTM5 reload data D3 High Low RDR52 PTM5 reload data D RDR5 PTM5 reload data D RDR5 PTM5 reload data (LSB) FFB4 D7 CDR47 PTM4 compare data D7 (MSB) CDR46 PTM4 compare data CDR45 PTM4 compare data D4 CDR44 PTM4 compare data D4 D3 CDR43 PTM4 compare data D3 High Low CDR42 PTM4 compare data D CDR4 PTM4 compare data D CDR4 PTM4 compare data (LSB) FFB5 D7 CDR57 PTM5 compare data D7 (MSB) CDR56 PTM5 compare data CDR55 PTM5 compare data D4 CDR54 PTM5 compare data D4 D3 CDR53 PTM5 compare data D3 High Low CDR52 PTM5 compare data D CDR5 PTM5 compare data D CDR5 PTM5 compare data (LSB) "" when being read Reserved register W "" when being read Constantly "" when being read Reserved register W "" when being read SC8865 TECHNICAL MANUAL EPSON 3

40 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(o) I/O Memory map (FFB6HFFBBH) Address Bit Name Function SR Comment FFB6 D7 PTM47 PTM46 PTM45 PTM4 data D7 (MSB) PTM4 data PTM4 data D4 PTM44 PTM4 data D4 D3 PTM43 PTM4 data D3 High Low R D PTM42 PTM4 PTM4 PTM4 data PTM4 data D PTM4 data (LSB) FFB7 D7 PTM57 PTM56 PTM55 PTM5 data D7 (MSB) PTM5 data PTM5 data D4 PTM54 PTM5 data D4 D3 PTM53 PTM5 data D3 High Low R D PTM52 PTM5 PTM5 PTM5 data PTM5 data D PTM5 data (LSB) FFB8 D7 MODE6_D PTM67 8/6-bit mode selection PTNREN_D External clock 3 noise rejecter selection 6-bit x Enable 8-bit x 2 Disable D4 D3 register register PTRUN6 PTM6 Run/Stop control Run Stop D PSET6 PTM6 preset Preset No operation CKSEL6 PTM6 input clock selection External clock Internal clock FFB9 D7 D4 D3 register register PTRUN7 PTM7 Run/Stop control Run Stop D PSET7 PTM7 preset Preset No operation CKSEL7 PTM7 input clock selection External clock Internal clock FFBA D7 RDR67 RDR66 RDR65 PTM6 reload data D7 (MSB) PTM6 reload data PTM6 reload data D4 RDR64 PTM6 reload data D4 D3 RDR63 PTM6 reload data D3 High Low D RDR62 RDR6 RDR6 PTM6 reload data PTM6 reload data D PTM6 reload data (LSB) FFBB D7 RDR77 PTM7 reload data D7 (MSB) RDR76 PTM7 reload data RDR75 PTM7 reload data D4 RDR74 PTM7 reload data D4 D3 RDR73 PTM7 reload data D3 High Low RDR72 PTM7 reload data D RDR7 PTM7 reload data D RDR7 PTM7 reload data (LSB) W "" when being read Reserved register "" when being read Constantly "" when being read Reserved register W "" when being read 32 EPSON SC8865 TECHNICAL MANUAL

41 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(p) I/O Memory map (FFBCHFFBFH) Address Bit Name Function SR Comment FFBC D7 CDR67 CDR66 CDR65 PTM6 compare data D7 (MSB) PTM6 compare data PTM6 compare data D4 CDR64 PTM6 compare data D4 D3 CDR63 PTM6 compare data D3 High Low D CDR62 CDR6 CDR6 PTM6 compare data PTM6 compare data D PTM6 compare data (LSB) FFBD D7 CDR77 CDR76 CDR75 PTM7 compare data D7 (MSB) PTM7 compare data PTM7 compare data D4 CDR74 PTM7 compare data D4 D3 CDR73 PTM7 compare data D3 High Low D CDR72 CDR7 CDR7 PTM7 compare data PTM7 compare data D PTM7 compare data (LSB) FFBE D7 PTM67 PTM66 PTM65 PTM6 data D7 (MSB) PTM6 data PTM6 data D4 PTM64 PTM6 data D4 D3 PTM63 PTM6 data D3 High Low R D PTM62 PTM6 PTM6 PTM6 data PTM6 data D PTM6 data (LSB) FFBF D7 PTM77 PTM76 PTM75 PTM7 data D7 (MSB) PTM7 data PTM7 data D4 PTM74 PTM7 data D4 D3 PTM73 PTM7 data D3 High Low R D PTM72 PTM7 PTM7 PTM7 data PTM7 data D PTM7 data (LSB) SC8865 TECHNICAL MANUAL EPSON 33

42 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control) 5.2 System Controller and Bus Control The system controller is a management unit which sets such items as the bus mode in accordance with memory system configuration factors. For the purposes of controlling the system, the following settings can be performed in software: () Bus and CPU mode settings (2) Chip enable (CE) signal output settings (3) WAIT state settings for external memory (4) Page address setting of the stack pointer Below is a description of the how these settings are to be made Bus mode and CPU mode settings The SC8865 has two bus modes and two CPU modes and the software must select appropriate modes according to the external memory size connected to the SC8865. As shown in Table 5.2.., these modes are specified usng the registers BUSMOD and CPUMOD. MCU/MPU terminal (MCU mode) (MPU mode) Table Bus and CPU mode settings Setting value BUSMOD CPUMOD Bus mode CPU mode Configuration of external memory Expansion Single chip Expansion Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum ROM+RAM>64K bytes (Program 64K bytes) ROM+RAM>64K bytes (Program<64K bytes) None (Program 64K bytes) None (Program<64K bytes) ROM+RAM>64K bytes (Program 64K bytes) ROM+RAM>64K bytes (Program<64K bytes) ROM+RAM>64K bytes (Program 64K bytes) ROM+RAM>64K bytes (Program<64K bytes) Terminal R R R2 R3 R4 R5 R6 R7 R R R2 R3 R4 R5 R6 R7 R2 R2 R22 R23 R24 R25 P P P2 P3 P4 P5 P6 P7 Table I/O terminal settings Bus mode Single chip Expansion Output port R Address bus A Output port R Address bus A Output port R2 Address bus A2 Output port R3 Address bus A3 Output port R4 Address bus A4 Output port R5 Address bus A5 Output port R6 Address bus A6 Output port R7 Address bus A7 Output port R Address bus A8 Output port R Address bus A9 Output port R2 Address bus A Output port R3 Address bus A Output port R4 Address bus A2 Output port R5 Address bus A3 Output port R6 Address bus A4 Output port R7 Address bus A5 Output port R2 Address bus A6 Output port R2 Address bus A7 Output port R22 Address bus A8 Output port R23 Address bus A9 Output port R24 RD signal Output port R25 WR signal I/O port P Data bus I/O port P Data bus D I/O port P2 Data bus I/O port P3 Data bus D3 I/O port P4 Data bus D4 I/O port P5 Data bus I/O port P6 Data bus I/O port P7 Data bus D7 The function of I/O terminals is set as shown in Table in accordance with mode selection. At initial reset, the bus mode (CPU mode) is set as explained below. In MCU mode: At initial reset, the SC8865 is set in single chip mode (minimum). Accordingly, in MCU mode, even if a memory has been externally expanded, the system is activated by the program written to internal ROM. In the system with externally expanded memory, perform the applicable bus mode settings during the initialization routine originating in internal ROM. In MPU mode: At initial reset, the SC8865 is set in expansion mode (minimum). Therefore, the internal ROM will be disabled Address decoder (CE output) settings As explained in Section 3.6.4, the SC8865 is equipped with address decoders that can output a maximum of three chip enable signals (CECE2) to external devices. 34 EPSON SC8865 TECHNICAL MANUAL

43 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control) CE signal CE CE CE2 Table Address settings of CECE2 Address range (expansion mode) MCU mode 3H3FFFFFH HFFFFFH 2H2FFFFFH MPU mode HD7FFH, HFFFFFH HFFFFFH 2H2FFFFFH The output terminals and output circuits for CE CE2 are shared with output ports R3R32. At initial reset, they are set as output port terminals. For this reason, when operating in expansion mode, the ports to be used as CE signal output terminals must be set as such. This setting is performed through software which writes "" to registers CECE2 corresponding the CE signals to be used. Table shows the address range assigned to the three chip enable (CE) signals. The arrangement of memory space for external devices does not necessarily have to be continuous from a subordinate address and any of the chip enable signals can be used to assign areas in memory. However, in the MPU mode, program memory must be assigned to CE. The CE signals are only output when the appointed external memory area is accessed and are not output when internal memory is accessed WAIT state settings In order to insure accessing of external low speed devices during high speed operations, the SC8865 is equipped with a WAIT function which prolongs access time. The number of wait states inserted can be selected from a choice of eight as shown in Table by means of registers WTWT2. Table Setting the number of WAIT states WT2 WT WT Number of inserted states No wait * The length of one state is a /2 clock cycle. WAIT states set in software are inserted between bus cycle states T3T4. Note, however, that WAIT states cannot be inserted when an internal register and internal memory are being accessed and when operating with the OSC oscillation circuit (see "5.4 Oscillation Circuits"). Consequently, WAIT state settings in single chip mode are meaningless. With regard to WAIT insertion timing, see Section 3.6.5, "WAIT control" Setting the bus authority release request signal With systems performing DMA transfer, the bus authority release request signal (BREQ) input terminal and acknowledge signal (BACK) output terminal have to be set. The BREQ input terminal is shared with input port terminal K3 and the BACK output terminal with output port terminal R33. At initial reset, these terminal facilities are set as input port terminal and output port terminal, respectively. The terminals can be altered to function as BREQ/BACK terminals by writing a "" to register EBR. For details on bus authority release, see "3.6.6 Bus authority release state" and "SC88 Core CPU Manual" Stack page setting Although the stack area used to evacuate registers during subroutine calls can be arbitrarily moved to any area in data RAM using the stack pointer SP, its page address is set in registers SPPSPP7 in I/O memory. At initial reset, SPPSPP7 are set to "H" (page ). Since the internal RAM is arranged on page (D8HF7FFH), the stack area in single chip mode is inevitably located in page. In order to place the stack area at the final address in internal RAM, the stack pointer SP is placed at an initial setting of "F8H". (SP is pre-decremented.) In the expansion mode, to place the stack in external expanded RAM, set a corresponding page to SPPSPP7. The page addresses to which SPP SPP7 can be set are H27H and must be within a RAM area. * A page is each recurrent 64K division of data memory beginning at address zero. SC8865 TECHNICAL MANUAL EPSON 35

44 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control) Control of system controller Table shows the control bits for the system controller. Table System controller control bits Address Bit Name Function SR Comment FF (MCU) D7 BUSMOD Bus mode CPUMOD CPU mode Expansion Maximum Single chip Minimum D4 D3 register register register Reserved register CE2 CE2 (R32) CE signal output Enable/Disable CE2 enable CE2 disable In Single chip mode, D CE CE (R3) Enable: CE signal output CE enable CE disable these setting are fixed CE CE (R3) Disable: DC (R3x) output CE enable CE disable at DC output. FF (MPU) D7 BUSMOD Bus mode CPUMOD CPU mode Expansion Maximum Minimum R Expansion mode only D4 D3 register register register Reserved register CE2 CE2 (R32) CE signal output Enable/Disable CE2 enable CE2 disable D CE CE (R3) Enable: CE signal output CE enable CE disable CE CE (R3) Disable: DC (R3x) output CE enable CE disable FF D7 D4 SPP7 SPP6 SPP5 SPP4 Stack pointer page address < SP page allocatable address > Single chip mode: only page (MSB) D3 D SPP3 SPP2 SPP Expansion mode: 27H page SPP (LSB) FF2 D7 EBR Bus release enable register K3 BREQ Input port (K3 and R33 terminal specification) R33 BACK Output port WT2 Wait control register Number of state WT D4 WT WT2 WT WT No wait D3 CLKCHG CPU operating clock switch OSC3 OSC D SOSC3 OSC3 oscillation On/Off control register register On Off Reserved register Note: All the interrupts including NMI are disabled, until you write the optional value into both the "FFH" and "FFH" addresses. 36 EPSON SC8865 TECHNICAL MANUAL

45 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control) BUSMOD, CPUMOD: FFH D7, Bus mode and CPU mode are set as shown in Table Table Bus mode and CPU mode settings MCU/MPU Setting value Bus mode CPU mode terminal BUSMOD CPUMOD (MCU mode) (MPU mode) Expansion Maximum Minimum Single Maximum chip Minimum Expansion Maximum Minimum Maximum Minimum The single chip mode configuration is only possible when this IC is used in the MCU mode. The single chip mode setting is incompatible with the MPU mode, since this mode does not utilize internal ROM. At initial reset, in the MCU mode the unit is set to single chip (minimum) mode and in the MPU mode the expansion (minimum) mode is used to select the applicable mode. CECE2: FFH Sets the CE output terminals being used. When "" is written: CE output enable When "" is written: CE output disable Reading: Valid CE output is enabled when a "" is written to registers CECE2 which correspond to the CE output being used. A "" written to any of the registers disables CE signal output from that terminal and it reverts to its alternate function as an output port terminal (R3R32). At initial reset, register CE is set to "" in the MCU mode and in the MPU mode, "" is set in the register. Registers CECE2 are always set to "" regardless of the MCU/MPU mode setting. Note: To avoid a malfunction from an interrupt generated before the bus configuration is initialized, all interrupts including NMI are masked until you write an optional value into address "FFH". SPPSPP7: FFH Sets the page address of stack area. In single chip mode, set page address to "H". In expansion mode, it can be set to any value within the range "H""27H". Since a carry and borrow from/to the stack pointer SP is not reflected in register SPP, the upper limit on continuous use of the stack area is 64K bytes. At initial reset, this register is set to "H" (page ). Note: To avoid a malfunction from an interrupt generated before the bus configuration is initialized, all interrupts including NMI are disabled, until you write an optional value into "FFH" address. Furthermore, to avoid generating an interrupt while the stack area is being set, all interrupts including NMI are disabled in one instruction execution period after writing to address "FFH". WTWT2: FF2H D4 How WAIT state settings are performed. The number of WAIT states to be inserted based on register settings is as shown in Table Table Setting WAIT states WT2 WT WT Number of inserted states No wait * The length of one state is a /2 clock cycle. At initial reset, this register is set to "" (no wait). EBR: FF2H D7 Sets the BREQ/BACK terminals function. When "" is written: BREQ/BACK enabled When "" is written: BREQ/BACK disabled Reading: Valid How BREQ and BACK terminal functions are set. Writing "" to EBR enables BREQ/BACK input/ output. Writing "" sets the BREQ terminal as input port terminal K3 and the BACK terminal as output port terminal R33. At initial reset, EBR is set to "" (BREQ/BACK disabled). SC8865 TECHNICAL MANUAL EPSON 37

46 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control) Programming notes () All the interrupts including NMI are masked, until you write the optional value into both the "FFH" and "FFH" addresses. Consequently, even if you do not change the content of this address (You use the initial value, as is.), you should still be sure to perform the writing operation using the initialization routine. (2) When setting stack fields, including page addresses as well, you should write them in the order of the register SPP ("FFH") and the stack pointer SP. Example: When setting the "78H" address LD EP, #H LD HL, #FFH LD [HL], #7H LD SP, #8H During this period the interrupts (including NMI) are masked. 38 EPSON SC8865 TECHNICAL MANUAL

47 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Watchdog Timer) 5.3 Watchdog Timer 5.3. Configuration of watchdog timer The SC8865 is equipped with a watchdog timer driven by OSC as source oscillation. The watchdog timer must be reset periodically by software, and if reset does not take place within the selected period, a non-maskable interrupt signal is generated and output to the CPU. The watchdog timer starts operating after initial reset, however, it can be stopped by the software. The NMI generation cycle by the watchdog timer can be selected by mask option. Watchdog timer NMI generation cycle 32768/fOSC (.75-sec cycle when fosc = 32 khz) 65536/fOSC (.52-sec cycle when fosc = 32 khz) 372/fOSC (34-sec cycle when fosc = 32 khz) 26244/fOSC (68-sec cycle when fosc = 32 khz) Figure is a block diagram of the watchdog timer. By running watchdog timer reset during the main routine of the program, it is possible to detect program runaway as if watchdog timer processing had not been applied. Normally, this routine is integrated at points that are regularly being processed. The watchdog timer continues to operate during HALT and when HALT state is continuous for longer than the selected period, the CPU starts exception processing. During SLEEP, the watchdog timer is stopped. Note: The NMI generation cycles in the watchdog timer mask option list represent maximum values. A maximum minus (<selected optional cycle> / 4) seconds of error occurs depending on the watchdog timer reset timing. For example, when 372/fOSC is selected by mask option, the actual NMI generation cycle is within the range of 9834/fOSC to 372/fOSC seconds Interrupt function In cases where the watchdog timer is not periodically reset in software, the watchdog timer outputs an interrupt signal to the CPU's NMI (level 4) input. Unmaskable and taking priority over other interrupts, this interrupt triggers the generation of exception processing. See the "SC88 Core CPU Manual" for more details on NMI exception processing. This exception processing vector is set at 4H. OSC oscillation circuit fosc Divider Mask option /6384 /32768 /65536 /372 Watchdog timer /4 Non-maskable interrupt (NMI) WDEN WDRST Watchdog timer enable signal Watchdog timer reset signal Fig Block diagram of watchdog timer SC8865 TECHNICAL MANUAL EPSON 39

48 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Watchdog Timer) Control of watchdog timer Table shows the control bits for the watchdog timer. Table Watchdog timer control bits Address Bit Name Function SR Comment FF4 D7 WDEN FOUT2 Watchdog timer enable FOUT frequency selection Enable Disable FOUT D4 FOUT FOUT2 FOUT FOUT D3 FOUTON FOUT output control D WDRST TMRST TMRUN Watchdog timer reset Clock timer reset Clock timer Run/Stop control Frequency fosc / fosc / 2 fosc / 4 fosc / 8 fosc3 / fosc3 / 2 fosc3 / 4 fosc3 / 8 On Reset Reset Run Off No operation No operation Stop W Constantly "" when W being read WDEN: FF4H D7 Selects whether the watchdog timer is used (enabled) or not (disabled). When "" is written: Enabled When "" is written: Disabled Reading: Valid When "" is written to the WDEN register, the watchdog timer starts count operation. When "" is written, the watchdog timer does not count and does not generate the interrupt (NMI). At initial reset, this register is set to "". WDRST: FF4H Resets the watchdog timer. When "" is written: Watchdog timer is reset When "" is written: No operation Reading: Constantly "" By writing "" to WDRST, the watchdog timer is reset, after which it is immediately restarted. Writing "" will mean no operation. Since WDRST is for writing only, it is constantly set to "" during readout Programming notes () When the watchdog timer is being used, the software must reset it within the cycles selected by mask option. (2) Do not execute the SLP instruction for 2 msec after a NMI interrupt has occurred (when fosc is khz). (3) Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled state (not used) before generating an interrupt (NMI) if it is not used. (4) The NMI generation cycles in the watchdog timer mask option list represent maximum values. A maximum minus (<selected optional cycle> / 4) seconds of error occurs depending on the watchdog timer reset timing. For example, when 372/fOSC is selected by mask option, the actual NMI generation cycle is within the range of 9834/fOSC to 372/fOSC seconds. 4 EPSON SC8865 TECHNICAL MANUAL

49 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Oscillation Circuits) 5.4 Oscillation Circuits 5.4. Configuration of oscillation circuits The SC8865 is twin clock system with two internal oscillation circuits (OSC and OSC3). The OSC3 oscillation circuit generates the mainclock (Max. 8.2 MHz) to run the CPU and some peripheral circuits in high speed, and the OSC oscillation circuit generates the sub-clock (Typ khz) for low-power operation. Figure shows the configuration of the oscillation circuit. SLEEP status OSC oscillation circuit OSC3 oscillation circuit Fig Configuration of oscillation circuits At initial reset, OSC3 oscillation circuit is selected for the CPU operating clock. ON/OFF switching of the OSC3 oscillation circuit and switching of the system clock between OSC3 and OSC are controlled in software. OSC3 circuit is utilized when high speed operation of the CPU and some peripheral circuits become necessary. Otherwise, OSC should be used to generate the operating clock and OSC3 circuit placed in a stopped state in order to reduce current consumption Mask option (fosc) (fosc3) Prescaler Clock switch To peripheral circuit To CPU (CLK) Oscillation circuit CPU clock control signal selection signal SOSC3 CLKCHG To some peripheral circuit OSC oscillation circuit Crystal oscillation circuit CR oscillation circuit OSC3 oscillation circuit Crystal oscillation circuit Ceramic oscillation circuit CR oscillation circuit In terms of the oscillation circuit types for OSC, either crystal oscillation or CR oscillation can be selected with the mask option. In terms of the oscillation circuit types for OSC3, either crystal oscillation, ceramic oscillation or CR oscillation can be selected with the mask option, in the same way as OSC OSC oscillation circuit The OSC oscillation circuit generates the khz (Typ.) system clock which is utilized during low speed operation (low power mode) of the CPU and peripheral circuits. Furthermore, even when OSC3 is utilized as the system clock, OSC continues to generate the source clock for the clock timer and stopwatch timer. This oscillation circuit stops when the SLP instruction is executed. In terms of the oscillation circuit types, either crystal oscillation or CR oscillation can be selected with the mask option. Figure shows the configuration of the OSC oscillation circuit. CG X'tal RCR VSS OSC OSC2 OSC OSC2 () Crystal oscillation circuit (2) CR oscillation circuit SLEEP status Fig OSC oscillation circuit SLEEP status fosc VSS fosc When crystal oscillation is selected, a crystal oscillation circuit can be easily formed by connecting a crystal oscillator X'tal (Typ khz) between the OSC and OSC2 terminals along with a trimmer capacitor CG (525 pf) between the OSC terminal and VSS. When CR oscillation is selected, the CR oscillation circuit (Max. 2 khz) is formed merely by connecting a resistor (RCR) between OSC and OSC2 terminals. Note: Do not select CR oscillation for the OSC oscillation circuit when crystal oscillation is selected for the OSC3 oscillation circuit. When such a selection is made, the OSC3 clock may be supplied to the internal circuits even though the OSC3 oscillation has not stabilized. SC8865 TECHNICAL MANUAL EPSON 4

50 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Oscillation Circuits) OSC3 oscillation circuit The OSC3 oscillation circuit generates the system clock when the CPU and some peripheral circuits are in high speed operation. This oscillation circuit stops when the SLP instruction is executed, or the SOSC3 register is set to "". In terms of oscillation circuit types, any one of crystal oscillation, ceramic oscillation or CR oscillation can be selected with the mask option. Figure shows the configuration of the OSC3 oscillation circuit. RCR3 CG2 Rf C VSS OSC3 OSC4 OSC3 OSC4 X'tal 2 or Ceramic fosc3 () Crystal/Ceramic oscillation circuit (2) CR oscillation circuit Fig OSC3 oscillation circuit Oscillation circuit control signal SLEEP status fosc3 Oscillation circuit control signal SLEEP status When crystal or ceramic oscillation circuit is selected, the crystal or ceramic oscillation circuit (Max. 8.2 MHz) are formed by connecting either a crystal oscillator (X'tal2) or a combination of ceramic oscillator (Ceramic) and feedback resistor (Rf) between OSC3 and OSC4 terminals and connecting two capacitors (CG2, C) between the OSC3 terminal and VSS, and between the OSC4 terminal and VSS, respectively. RESET When CR oscillation is selected, the CR oscillation circuit (Max. 2.2 MHz) is formed merely by connecting a resistor (RCR3) between OSC3 and OSC4 terminals Switching the CPU clocks You can use either OSC or OSC3 as the system clock for the CPU and you can switch over by means of software. You can save power by turning the OSC3 oscillation circuit off while the CPU is operating in OSC. When you must operate on OSC3, you can change to high speed operation by turning the OSC3 oscillation circuit ON and switching over the system clock. In this case, since several msec to several tens of msec are necessary for the oscillation to stabilize after turning the OSC3 oscillation circuit ON, you should switch over the clock after stabilization time has elapsed. When switching over from the OSC3 to the OSC, turn the OSC3 oscillation circuit OFF immediately following the clock changeover. When switching the system clock from OSC3 to OSC immediately after the power is turned on, it is necessary to wait for the OSC oscillation to stabilize before the clock can be switched. The OSC3 oscillation may take several tens of msec to several seconds until it has completely stabilized. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 8, "ELECTRICAL CHARACTERISTICS".) Figure indicates the status transition diagram for the clock changeover. Program Execution Status High speed operation CLKCHG= OSC ON OSC3 ON CPU clock OSC3 CLKCHG= Low speed operation OSC ON OSC3 ON CPU clock OSC SOSC3= SOSC3= Low speed and low power operation OSC ON OSC3 OFF CPU clock OSC Interrupt* HALT instruction Interrupt * (Input interrupt) SLP instruction HALT status OSC ON OSC3 ON or OFF CPU clock STOP SLEEP status OSC OFF OSC3 OFF CPU clock STOP Standby Status * The return destination from the standby status becomes the program execution status prior to shifting to the standby status. Fig Status transition diagram for the clock changeover 42 EPSON SC8865 TECHNICAL MANUAL

51 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Oscillation Circuits) Control of oscillation circuit Table shows the control bits for the oscillation circuits. Table Oscillation circuit control bits Address Bit Name Function SR FF2 D7 EBR Bus release enable register K3 BREQ Input port (K3 and R33 terminal specification) R33 BACK Output port WT2 Wait control register Number of state WT D4 WT WT2 WT WT D3 CLKCHG CPU operating clock switch D SOSC3 OSC3 oscillation On/Off control register register No wait OSC3 On OSC Off Comment Reserved register SOSC3: FF2H Controls the ON and OFF settings of the OSC3 oscillation circuit. When "" is written: OSC3 oscillation ON When "" is written: OSC3 oscillation OFF Reading: Valid When the CPU and some peripheral circuits are to be operated at high speed, SOSC3 is to be set to "". At all other times, it should be set to "" in order to reduce current consumption. At initial reset, SOSC3 is set to "" (OSC3 oscillation ON). CLKCHG: FF2H D3 Selects the operating clock for the CPU. When "" is written: OSC3 clock When "" is written: OSC clock Reading: Valid When the operating clock for the CPU is switched to OSC3, CLKCHG should be set to "" and when the clock is switched to OSC, CLKCHG should be set to "". At initial reset, CLKCHG is set to "" (OSC3 clock) Programming notes () When the high speed CPU operation is not necessary, you should operate the peripheral circuits according to the setting outline indicate below. CPU operating clock OSC OSC3 oscillation circuit OFF (When the OSC3 clock is not necessary for some peripheral circuits.) (2) Since several msec to several tens of msec are necessary for the oscillation to stabilize after turning the OSC3 oscillation circuit ON. Consequently, you should switch the CPU operating clock (OSC OSC3) after allowing for a sufficient waiting time once the OSC3 oscillation goes ON. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 8, "ELECTRICAL CHARACTERIS- TICS".) (3) When switching the clock from OSC3 to OSC, be sure to switch OSC3 oscillation OFF with separate instructions. Using a single instruction to process simultaneously can cause a malfunction of the CPU. (4) When switching the system clock from OSC3 to OSC immediately after the power is turned on, it is necessary to wait the OSC oscillation to stabilize before the clock can be switched. The OSC3 oscillation takes several tens of msec to several seconds until it has completely stabilized. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 8, "ELECTRICAL CHARACTERISTICS".) SC8865 TECHNICAL MANUAL EPSON 43

52 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports) 5.5 Input Ports (K ports) 5.5. Configuration of input ports The SC8865 is equipped with 8 input port bits (KK7) all of which are usable as general purpose input port terminals with interrupt function. K4K7 terminals doubles as the external clock (EXCLEXCL3) input terminal of the programmable timer (event counter) with input port functions sharing the input signal as is. (See "5. Programmable Timer") Furthermore, it should be noted, however, that K3 terminal is shared with the bus authority release request signal (BREQ) input terminal. Function assignment of this terminal can be selected in software. When this terminal is selected for BREQ signal, K3 cannot be used as an input port. (See "5.2 System Controller and Bus Control") In the explanation below, it is assumed that K3 is set as an input port. Figure shows the structure of the input port. VDD Pull-up control register Mask option Input port pull-up resistors K... With resistor Gate direct K... With resistor Gate direct K2... With resistor Gate direct K3... With resistor Gate direct K4... With resistor Gate direct K5... With resistor Gate direct K6... With resistor Gate direct K7... With resistor Gate direct Input port Input I/F level K... CMOS level CMOS schmitt K... CMOS level CMOS schmitt K2... CMOS level CMOS schmitt K3... CMOS level CMOS schmitt K4... CMOS level CMOS schmitt K5... CMOS level CMOS schmitt K6... CMOS level CMOS schmitt K7... CMOS level CMOS schmitt Input ports KK7 are all equipped with pull-up resistors. The mask option can be used to select 'With resistor' or 'Gate direct' for each port (bit). Also the interface level, either CMOS level or CMOS Schmitt level, can be selected for each port (in a bit units). Address Kxx Mask option KxxD Mask option Address Data bus Input interrupt VSS circuit Fig Structure of input port Each input port terminal is directly connected via a three-state buffer to the data bus. Furthermore, the input signal state at the instant of input port readout is read in that form as data. 44 EPSON SC8865 TECHNICAL MANUAL

53 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports) Pull-up control When "With resistor" is selected by mask option, the software can enable and disable the pull-up resistor for each port (-bit units). The pull-up resistor becomes effective by writing "" to the pull-up control register PULKx that corresponds to each port, and the input line is pulled up. When "" has been written, no pull-up is done. When "Gate direct" is selected by mask option, the corresponding pull-up control register is disconnected from the input line, so it can be used as a general-purpose register. At initial reset, the pull-up control register is set to "" (pulled up). The input port with a pull-up resistor suits input from the push switch and key matrix. When changing the input terminal from LOW level to HIGH with the built-in pull-up resistor, a delay in the waveform rise time will occur depending on the time constant of the pull-up resistor and the load capacitance of the terminal. It is necessary to set an appropriate wait time for introduction of an input port. In particular, special attention should be paid to key scan for key matrix formation. Make this wait time the amount of time or more calculated by the following expression. Wait time = RIN x (CIN + load capacitance on the board) x.6 [sec] RIN: Pull up resistance Max. value CIN: Terminal capacitance Max. value The input port without a pull-up resistor is suits for slide switch input and interfacing with other LSIs. In this case, take care that a floating state does not occur in input. For unused ports, select "With resistor" and enable pull-up using the pull-up control registers Interrupt function and input comparison register All the input ports (KK7) provide the interrupt functions. The conditions for issuing an interrupt can be set by the software. When the interrupt generation condition set for a terminal is met, the interrupt factor flag FKFK7 corresponding to the terminal is set at "" and an interrupt is generated. Interrupt can be prohibited by setting the interrupt enable registers EKEK7 for the corresponding interrupt factor flags. Furthermore, the priority level for input interrupt can be set at the desired level (3) using the interrupt priority registers PKPK. For details on the interrupt control registers for the above and on operations subsequent to interrupt generation, see "5.4 Interrupt and Standby Status". The exception processing vectors for each interrupt factor are set as follows: K7 input interrupt: 6H K6 input interrupt: 8H K5 input interrupt: AH K4 input interrupt: CH K3 input interrupt: EH K2 input interrupt: H K input interrupt: 2H K input interrupt: 4H Figure shows the configuration of the input interrupt circuit. The input comparison register KCP selects whether the interrupt for each input port will be generated on the rising edge or the falling edge of input. When the Kx input signal changes to the status set by the input comparison register KCPx, the interrupt factor flag FKx is set to "" and an interrupt occurs. The input port has a chattering-eliminate circuit that checks input level to avoid unnecessary interrupt generation due to chattering. There are two separate chattering-eliminate circuits for K K3 and K4K7 and they can be set up individually. The CTKxCTK2x registers allow selection of signal level check time as shown in Table SC8865 TECHNICAL MANUAL EPSON 45

54 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports) Table Setting the input level check time CTK2x CTKx CTKx Check time ( ) 4/fOSC3 (2 µs) 2/fOSC3 ( µs) /fosc3 (.5 µs) 496/fOSC (28 ms) 248/fOSC (64 ms) 52/fOSC (6 ms) 28/fOSC (4 ms) None : When OSC = 32 khz, OSC3 = 2 MHz Notes: Be sure to disable interrupts before changing the contents of the CTKx register. Unnecessary interrupts may occur if the register is changed when the corresponding input port interrupts have been enabled by the interrupt enable register EKx. The chattering-eliminate check time means the maximum pulse width that can be eliminated. The valid interrupt input needs a pulse width of the set check time (minimum) to twice that of the check time (maximum). The internal signal may oscillate if the rise / fall time of the input signal is too long because the input signal level transition to the threshold level duration of time is too long. This causes the input interrupt to malfunction, therefore setup the input signal so that the rise/fall time is 25 nsec or less. K Check time setup register CTKLCTK2L Address Input port KD Input comparison register KCP Chattering-eliminate circuit Interrupt factor flag FK Divider Divider fosc fosc3 OSC oscillation circuit OSC3 oscillation circuit Address Address Interrupt enable register EK Address Data bus K K2 K3 K4 Check time setup register CTKHCTK2H Address Interrupt priority level judgement circuit Interrupt request Input port K4D Chattering-eliminate circuit Input comparison register KCP4 Address K5 K6 K7 Interrupt factor flag FK4 Address Interrupt enable register EK4 Address Interrupt priority register PK, PK Address Fig Configuration of input interrupt circuit 46 EPSON SC8865 TECHNICAL MANUAL

55 5.5.5 Control of input ports 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports) Table shows the input port control bits. Table (a) Input port control bits Address Bit Name Function SR Comment FF52 D7 KCP7 KCP6 KCP5 K7 input comparison register K6 input comparison register K5 input comparison register Interrupt Interrupt D4 KCP4 K4 input comparison register generated generated D3 KCP3 K3 input comparison register at falling at rising KCP2 K2 input comparison register edge edge D KCP KCP K input comparison register K input comparison register FF54 D7 K7D K6D K5D K7 input port data K6 input port data K5 input port data D4 K4D K4 input port data High level Low level D3 K3D K3 input port data input input R D K2D KD KD K2 input port data K input port data K input port data FF56 D7 PULK7 PULK6 PULK5 K7 pull-up control register K6 pull-up control register K5 pull-up control register D4 PULK4 K4 pull-up control register D3 PULK3 K3 pull-up control register On Off D PULK2 PULK PULK K2 pull-up control register K pull-up control register K pull-up control register FF58 D7 "" when being read CTK2H K4K7 port chattering-eliminate setup (Input level check time) Check time CTK2H CTKH CTKH [sec] CTKH 4/fOSC3 2/fOSC3 /fosc3 496/fOSC D4 CTKH 248/fOSC 52/fOSC 28/fOSC None D3 CTK2L KK3 port chattering-eliminate setup (Input level check time) Check time CTK2L CTKL CTKL [sec] D CTKL 4/fOSC3 2/fOSC3 /fosc3 496/fOSC CTKL 248/fOSC 52/fOSC 28/fOSC None "" when being read SC8865 TECHNICAL MANUAL EPSON 47

56 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports) Table (b) Input port control bits Address Bit Name Function SR Comment FF2 D7 PK KK7 interrupt priority register PK PK Priority PSIF PSIF level PK Level 3 PSIF Serial interface interrupt priority register Level 2 Level D4 PSIF Level D3 Constantly "" when being read D PTM Clock timer interrupt priority register PTM PTM Priority level Level 3 PTM Level 2 Level Level FF24 D7 EK7 EK6 EK5 K7 interrupt enable K6 interrupt enable K5 interrupt enable D4 EK4 K4 interrupt enable Interrupt Interrupt D3 EK3 K3 interrupt enable enable disable D EK2 EK EK K2 interrupt enable K interrupt enable K interrupt enable FF28 D7 FK7 FK6 FK5 K7 interrupt factor flag K6 interrupt factor flag K5 interrupt factor flag (R) Interrupt factor is (R) No interrupt factor is D4 FK4 K4 interrupt factor flag generated generated D3 FK3 K3 interrupt factor flag (W) (W) FK2 K2 interrupt factor flag Reset No operation D FK K interrupt factor flag FK K interrupt factor flag KDK7D: FF54H Input data of input port terminal Kx can be read out. When "" is read: HIGH level When "" is read: LOW level Writing: Invalid The terminal voltage of each of the input port K K7 can be directly read out as either a "" for HIGH (VDD) level or a "" for LOW (VSS) level. This bit is exclusively for readout and are not usable for write operations. PULKPULK7: FF56H Controls the input pull-up resistor. When "" is written: Pull-up ON When "" is written: Pull-up OFF Reading: Valid PULKx is the pull-up control register corresponding to the input port Kx that turns the pull-up resistor built into the input port ON and OFF. When "Gate direct" is selected by mask option, the corresponding pull-up control register is disconnected from the input line, so it can be used as a general-purpose register. When "" is written to PULKx, the corresponding input port Kx is pulled up to high. When "" is written, the input port is not pulled up. At initial reset, this register is set to "" (Pull-up ON). 48 EPSON SC8865 TECHNICAL MANUAL

57 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports) KCPKCP7: FF52H Sets the interrupt generation condition (interrupt generation timing) for input port terminals K K7. When "" is written: Falling edge When "" is written: Rising edge Reading: Valid KCPx is the input comparison register which corresponds to the input port Kx. Interrupt in those ports which have been set to "" is generated on the falling edge of the input and in those set to "" on the rising edge. At initial reset, this register is set to "" (falling edge). CTKLCTK2L: FF58H Sets the input level check time of the chatteringeliminate circuit for the KK3 input port interrupts as shown in Table Table Setting the input level check time CTK2L CTKL CTKL Input level check time [sec] 4/fOSC3 2/fOSC3 /fosc3 496/fOSC 248/fOSC 52/fOSC 28/fOSC None Be sure to disable interrupts before changing the contents of this register. Unnecessary interrupts may occur if the register is changed when the corresponding input port interrupts have been enabled by the interrupt enable register EKx. At initial reset, this register is set to "" (None). CTKHCTK2H: FF58H D4 Sets the input level check time of the chatteringeliminate circuit for the K4K7 input port interrupts as shown in Table Table Setting the input level check time CTK2H CTKH CTKH Input level check time [sec] 4/fOSC3 2/fOSC3 /fosc3 496/fOSC 248/fOSC 52/fOSC 28/fOSC None Be sure to disable interrupts before changing the contents of this register. Unnecessary interrupt may occur if the register is changed when the corresponding input port interrupts have been enabled by the interrupt enable register EKx. At initial reset, this register is set to "" (None). PK, PK: FF2H, D7 Sets the input interrupt priority level. PK and PK are the interrupt priority registers corresponding to the input interrupts. Table shows the interrupt priority level which can be set by this register. Table Interrupt priority level settings PK PK Interrupt priority level Level 3 (IRQ3) Level 2 (IRQ2) Level (IRQ) Level (None) At initial reset, this register is set to "" (level ). EKEK7: FF24H How interrupt generation to the CPU is permitted or prohibited. When "" is written: Interrupt permitted When "" is written: Interrupt prohibited Reading: Valid EKx is the interrupt enable register which correspond to the input port Kx. Interrupt is permitted in those terminals set to "" and prohibited in those set to "". At initial reset, this register is set to "" (interrupt prohibited). FKFK7: FF28H Indicates the generation state for an input interrupt. When "" is read: Interrupt factor present When "" is read: Interrupt factor not present When "" is written: Reset factor flag When "" is written: Invalid The interrupt factor flag FKx corresponds to Kx is set to "" by the occurrence of an interrupt generation condition. When set in this manner, if the corresponding interrupt enable register is set to "" and the corresponding interrupt priority register is set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag will be set to "" by the occurrence of an interrupt generation condition. To accept the subsequent interrupt after interrupt generation, re-setting of the interrupt flags (set interrupt flag to lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and interrupt factor flag reset are necessary. The interrupt factor flag is reset to "" by writing "". At initial reset, this flag is all reset to "". SC8865 TECHNICAL MANUAL EPSON 49

58 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports) Programming notes () When changing the input terminal from LOW level to HIGH with the built-in pull-up resistor, a delay in the waveform rise time will occur depending on the time constant of the pull-up resistor and the load capacitance of the terminal. It is necessary to set an appropriate wait time for introduction of an input port. In particular, special attention should be paid to key scan for key matrix formation. Make this wait time the amount of time or more calculated by the following expression. Wait time = RIN x (CIN + load capacitance on the board) x.6 [sec] RIN: Pull up resistance Max. value CIN: Terminal capacitance Max. value (2) Be sure to disable interrupts before changing the contents of the CTKx register. Unnecessary interrupts may occur if the register is changed when the corresponding input port interrupts have been enabled by the interrupt enable register EKx. 5 EPSON SC8865 TECHNICAL MANUAL

59 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports) 5.6 Output Ports (R ports) 5.6. Configuration of output ports The SC8865 is equipped with 26 bits of output ports (RR7, RR7, R2R25, R3R33). Depending on the bus mode setting, the configuration of the output ports may vary as shown in the table below. Table Configuration of output ports Terminal R R R2 R3 R4 R5 R6 R7 R R R2 R3 R4 R5 R6 R7 R2 R2 R22 R23 R24 R25 R3 R3 R32 R33 Single chip Output port R Output port R Output port R2 Output port R3 Output port R4 Output port R5 Output port R6 Output port R7 Output port R Output port R Output port R2 Output port R3 Output port R4 Output port R5 Output port R6 Output port R7 Output port R2 Output port R2 Output port R22 Output port R23 Output port R24 Output port R25 Output port R3 Output port R3 Output port R32 Output port R33 Bus mode Expansion Address A Address A Address A2 Address A3 Address A4 Address A5 Address A6 Address A7 Address A8 Address A9 Address A Address A Address A2 Address A3 Address A4 Address A5 Address A6 Address A7 Address A8 Address A9 RD signal WR signal Output port R3/CE signal Output port R3/CE signal Output port R32/CE2 signal Output port R33/BACK signal Only the configuration of the output ports in single chip mode will be discussed here. With respect to bus control, see "5.2 System Controller and Bus Control". Figure shows the basic structure of the output ports. Data bus Address High impedance control register Data register VDD Rxx In expansion mode, the data registers and high impedance control registers of the output ports used for bus function can be used as general purpose registers with read/write capabilities. This will not in any way affect bus signal output. The output specification of each output port is as complementary output with high impedance control in software possible High impedance control The output port can be high impedance controlled in software. This makes it possible to share output signal lines with an other external device. A high impedance control register is set for each series of output port terminals as shown below. Either complementary output and high impedance state can be selected with this register. Table High impedance control registers Register Output port terminal HZRL RR3 HZRH R4R7 HZRL RR3 HZRH R4R7 HZR2 R2 HZR2 R2 HZR22 R22 HZR23 R23 HZR24 R24 HZR25 R25 HZR3 R3 HZR3 R3 HZR32 R32 HZR33 R33 When a high impedance control register HZRxx is set to "", the corresponding output port terminal becomes high impedance state and when set to "", it becomes complementary output DC output As Figure shows, when "" is written to the output port data register, the output terminal switches to HIGH (VDD) level and when "" is written it switches to LOW (VSS) level. When output is in a high impedance state, the data written to the data register is output from the terminal at the instant when output is switched to complementary. Address Fig Structure of output ports VSS SC8865 TECHNICAL MANUAL EPSON 5

60 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports) Control of output ports Table shows the output port control bits. Table (a) Output port control bits Address Bit Name Function SR Comment FF7 D7 register Reserved register D4 D3 D HZRH HZRL HZRH HZRL register register register R4R7 high impedance control RR3 high impedance control R4R7 high impedance control RR3 high impedance control High impedance Complementary FF7 D7 register register HZR25 R25 high impedance control D4 HZR24 R24 high impedance control D3 HZR23 R23 high impedance control High Complementary HZR22 R22 high impedance control impedance D HZR2 R2 high impedance control HZR2 R2 high impedance control FF72 D7 register register register D4 register D3 HZR33 R33 high impedance control HZR32 R32 high impedance control High Complementary D HZR3 R3 high impedance control impedance HZR3 R3 high impedance control FF73 D7 R7D R7 output port data R6D R6 output port data R5D R5 output port data D4 R4D R4 output port data D3 R3D R3 output port data High Low R2D R2 output port data D RD R output port data RD R output port data FF74 D7 R7D R7 output port data R6D R6 output port data R5D R5 output port data D4 R4D R4 output port data D3 R3D R3 output port data High Low R2D R2 output port data D RD R output port data RD R output port data FF75 D7 register register R25D R25 output port data D4 R24D R24 output port data D3 R23D R23 output port data R22D R22 output port data High Low D R2D R2 output port data R2D R2 output port data Reserved register Reserved register Reserved register 52 EPSON SC8865 TECHNICAL MANUAL

61 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports) Table (b) Output port control bits Address Bit Name Function SR Comment FF76 D7 D4 D3 R33D register register register register R33 output port data Reserved register R32D R32 output port data D R3D R3 output port data High Low R3D R3 output port data HZRL, HZRH: FF7H, D HZRL, HZRH: FF7H, D3 HZR2HZR25: FF7H HZR3HZR33: FF72H D3 Sets the output terminals to a high impedance state. When "" is written: High impedance When "" is written: Complementary Reading: Valid HZRxx is the high impedance control register which correspond as shown in Table to the various output port terminals. When "" is set to the HZRxx register, the corresponding output port terminal becomes high impedance state and when "" is set, it becomes complementary output. At initial reset, this register is set to "" (complementary). RDR7D: FF73H RDR7D: FF74H R2DR25D: FF75H R3DR33D: FF76H D3 Sets the data output from the output port terminal Rxx. When "" is written: HIGH level output When "" is written: LOW level output Reading: Valid RxxD is the data register for each output port. When "" is set, the corresponding output port terminal switches to HIGH (VDD) level, and when "" is set, it switches to LOW (VSS) level. At initial reset, this register is set to "" (HIGH level output). The output data registers set for bus signal output can be used as general purpose registers with read/ write capabilities which do not affect the output terminals. SC8865 TECHNICAL MANUAL EPSON 53

62 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports) 5.7 I/O Ports (P ports) 5.7. Configuration of I/O ports The SC8865 is equipped with 6 bits of I/O ports (PP7, PP7). The configuration of these I/O ports will vary according to the bus mode as shown below. Table Configuration of I/O ports Terminal P P P2 P3 P4 P5 P6 P7 P P P2 P3 P4 P5 P6 P7 Single chip Bus mode Expansion I/O port P Data bus I/O port P Data bus D I/O port P2 Data bus I/O port P3 Data bus D3 I/O port P4 Data bus D4 I/O port P5 Data bus I/O port P6 Data bus I/O port P7 Data bus D7 I/O port P (SIN) I/O port P (SOUT) I/O port P2 (SCLK) I/O port P3 (SRDY) I/O port P4 (TOUT/TOUT) I/O port P5 (TOUT2/TOUT3) I/O port P6 (FOUT) I/O port P7 (TOUT2/TOUT3) With respect to the data bus, see "5.2 System Controller and Bus Control". Figure shows the structure of an I/O port. Data bus Pull-up control register I/O control register Data register * Input *2 control VSS *3 *: During output mode *2: During input mode *3: Schmitt input can be selected for PP7 by mask option. VDD Mask option Pxx Fig Structure of I/O port I/O port can be set for input or output mode in one bit unit. These settings are performed by writing data to the I/O control registers. I/O port terminals PP3 are shared with serial interface input/output terminals and the function of each terminal is switchable in software. With respect to serial interface see "5.8 Serial Interface". The data registers and I/O control registers of I/O ports set for data bus and serial interface output terminals use are usable as general purpose registers with read/write capabilities which do not affect I/O activities of the terminal. The same as above, the I/O control register of I/O port set for serial interface input terminal use is usable as general purpose register. In addition to the general-purpose DC output, special output can be selected for the I/O ports P4P7 with the software Mask option I/O port pull-up resistors P... With resistor P... With resistor P2... With resistor P3... With resistor P4... With resistor P5... With resistor P6... With resistor P7... With resistor P... With resistor P... With resistor P2... With resistor P3... With resistor P4... With resistor P5... With resistor P6... With resistor P7... With resistor Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct I/O port input interface level P... CMOS level CMOS Schmitt P... CMOS level CMOS Schmitt P2... CMOS level CMOS Schmitt P3... CMOS level CMOS Schmitt P4... CMOS level CMOS Schmitt P5... CMOS level CMOS Schmitt P6... CMOS level CMOS Schmitt P7... CMOS level CMOS Schmitt I/O ports PP7 and PP7 are equipped with a pull-up resistor which goes ON in the input mode. Whether this resistor is used or not can be selected for each port (one bit unit). Furthermore, the interface level for each port in PP7 can be selected from CMOS level and CMOS Schmitt level I/O control registers and I/O mode I/O ports PP7 and PP7 are set either to input or output modes by writing data to the I/O control registers IOCIOC7 and IOCIOC7 which correspond to each bit. To set an I/O port to input mode, write "" to the I/ O control register. An I/O port which is set to input mode will shift to a high impedance state and functions as an input port. 54 EPSON SC8865 TECHNICAL MANUAL

63 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports) Readout in input mode consists simply of a direct readout of the input terminal state: the data being "" when the input terminal is at HIGH (VDD) level and "" when it is at LOW (VSS) level. When the built-in pull-up resistor is enabled with the software, the port terminal will be pulled-up to high during input mode. Even in input mode, data can be written to the data registers without affecting the terminal state. To set an I/O port to output mode, write "" to the I/O control register. An I/O port which is set to output mode functions as an output port. When port output data is "", a HIGH (VDD) level is output and when it is "", a LOW (VSS) level is output. Readout in output mode consists of the contents of the data register. At initial reset, I/O control registers are set to "" (I/O ports are set to input mode) Pull-up control When "With resistor" is selected by mask option, the software can enable and disable the pull-up resistor for each port (-bit units). The pull-up resistor becomes effective by writing "" to the pull-up control register PULPxx that corresponds to each port, and the Pxx terminal is pulled up during the input mode. When "" has been written, no pull-up is done. When "Gate direct" is selected by mask option, the corresponding pull-up control register is disconnected from the input line, so it can be used as a general-purpose register. When the port is set in the output mode, the setting of the pull-up control register becomes invalid (no pull-up is done during output). At initial reset, the pull-up control registers are set to "" (pulled up). When changing the port terminal from LOW level to HIGH with the built-in pull-up resistor, a delay in the waveform rise time will occur depending on the time constant of the pull-up resistor and the load capacitance of the terminal. It is necessary to set an appropriate wait time for introduction of an I/O port. Make this wait time the amount of time or more calculated by the following expression. Wait time = RIN x (CIN + load capacitance on the board) x.6 [sec] RIN: Pull up resistance Max. value CIN: Terminal capacitance Max. value For unused ports, select "With resistor" and enable pull-up using the pull-up control registers Special output Besides general purpose DC input/output, I/O ports P4P7 can also be assigned special output functions in software as shown in Table Table Special output ports Output port Special output P4 TOUT/TOUT output P5 TOUT2/TOUT3 output P6 FOUT output P7 TOUT2/TOUT3 output When using P4P7 as a special output port, write "" to the corresponding I/O control register (IOC4IOC7) to set the port to the output mode. TOUT output (P4, P5) In order for the SC8865 to provide clock signal to an external device, the terminals P4 and P5 can be used to output a TOUTx signal (clock output by the programmable timer). The output control for the TOUTx signals (x = 3) is done by the registers PTOUTx. When PTOUTx is set to "", the TOUTx signal is output from the corresponding port terminal, when "" is set, the port is set for DC output. When PTOUTx is "", settings of the I/O control register IOC4/IOC5 and data register P4D/P5D become invalid. The TOUTTOUT3 signals are generated from the underflow and compare-match signals of the programmable timers 3. With respect to frequency control, see "5. Programmable Timer". Since the TOUTx signals are generated asynchronously from the registers PTOUTx, when the signals are turned ON or OFF by the register settings, a hazard of a /2 cycle or less is generated. Figure shows the output waveform of the TOUT signal. PTOUTx TOUTx output (P4/5) Note: Fig Output waveform of TOUT signal If PTOUT and PTOUT are set to "" at the same time, PTOUT is effective. Similarly, if PTOUT2 and PTOUT3 are set to "", PTOUT3 is effective. SC8865 TECHNICAL MANUAL EPSON 55

64 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports) FOUT output (P6) In order for the SC8865 to provide clock signal to an external device, a FOUT signal (oscillation clock fosc or fosc3 dividing clock) can be output from the P6 port terminal. The output control for the FOUT signal is done by the register FOUTON. When FOUTON is set to "", the FOUT signal is output from the P6 port terminal, when "" is set, the port is set for DC output. When FOUTON is "", settings of the I/O control register IOC6 and data register P6D become invalid. The frequency of the FOUT signal can be selected in software by setting the registers FOUTFOUT2. The frequency is selected any one from among eight settings as shown in Table Table FOUT frequency setting FOUT2 FOUT FOUT FOUT frequency fosc3 / 8 fosc3 / 4 fosc3 / 2 fosc3 / fosc / 8 fosc / 4 fosc / 2 fosc / fosc: OSC oscillation frequency fosc3: OSC3 oscillation frequency When the FOUT frequency is made "fosc3/n", you must turn on the OSC3 oscillation circuit before outputting FOUT. A time interval of several msec to several msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes, is necessary, due to the oscillation element that is used. Consequently, if an abnormality occurs as the result of an unstable FOUT signal being output externally, you should allow an adequate waiting time after turning ON of the OSC3 oscillation, before turning outputting FOUT. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 8, "ELECTRICAL CHARACTERISTICS".) Since the FOUT signal is generated asynchronously from the register FOUTON, when the signal is turned ON or OFF by the register settings, a hazard of a /2 cycle or less is generated. Figure shows the output waveform of the FOUT signal. Inverted TOUT output (P7) The SC8865 provides an output of the TOUT2 or TOUT3 inverted signal (programmable timer output clock) to supply a clock to external devices or to drive a buzzer. By using this output with the TOUT2 or TOUT3 output from the P5 terminal, the bias level to be applied to the buzzer can be increased. The output control for the TOUTx signals (x = 2 or 3) is done by the registers RPTOUTx. When RPTOUTx is set to "", the TOUTx signal is output from the P7 port terminal, when "" is set, the port is set for DC output. When RPTOUTx is "", settings of the I/O control register IOC7 and data register P7D become invalid. The TOUT2 and TOUT3 signals are generated from the underflow and compare-match signals of the programmable timers 2 and 3. With respect to frequency control, see "5. Programmable Timer". Since the TOUTx signals are generated asynchronously from the registers RPTOUTx, when the signals are turned ON or OFF by the register settings, a hazard of a /2 cycle or less is generated. Figure shows the output waveform of the TOUT signal. RPTOUTx TOUTx output (P7) Fig Output waveform of TOUT signal Note: If RPTOUT2 and RPTOUT3 are set to "" at the same time, RPTOUT3 is effective. FOUTON FOUT output (P6) Fig Output waveform of FOUT signal 56 EPSON SC8865 TECHNICAL MANUAL

65 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports) Control of I/O ports Table shows the I/O port control bits. Table (a) I/O port control bits Address Bit Name Function SR FF6 D7 IOC7 IOC6 IOC5 P7 I/O control register P6 I/O control register P5 I/O control register D4 IOC4 P4 I/O control register D3 IOC3 P3 I/O control register Output Input D IOC2 IOC IOC P2 I/O control register P I/O control register P I/O control register FF6 D7 IOC7 IOC6 IOC5 P7 I/O control register P6 I/O control register P5 I/O control register D4 IOC4 P4 I/O control register D3 IOC3 P3 I/O control register Output Input D IOC2 IOC IOC P2 I/O control register P I/O control register P I/O control register FF62 D7 P7D P6D P5D P7 I/O port data P6 I/O port data P5 I/O port data D4 P4D P4 I/O port data D3 P3D P3 I/O port data High Low D P2D PD PD P2 I/O port data P I/O port data P I/O port data FF63 D7 P7D P7 I/O port data P6D P6 I/O port data P5D P5 I/O port data D4 P4D P4 I/O port data D3 P3D P3 I/O port data High Low P2D P2 I/O port data D PD P I/O port data PD P I/O port data FF64 D7 PULP7 P7 pull-up control register PULP6 P6 pull-up control register PULP5 P5 pull-up control register D4 PULP4 P4 pull-up control register D3 PULP3 P3 pull-up control register On Off PULP2 P2 pull-up control register D PULP P pull-up control register PULP P pull-up control register FF65 D7 PULP7 P7 pull-up control register PULP6 P6 pull-up control register PULP5 P5 pull-up control register D4 PULP4 P4 pull-up control register D3 PULP3 P3 pull-up control register On Off PULP2 P2 pull-up control register D PULP P pull-up control register PULP P pull-up control register Comment SC8865 TECHNICAL MANUAL EPSON 57

66 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports) Table (b) I/O port control bits Address Bit Name Function SR Comment FF3 D7 MODE6_A PTM 8/6-bit mode selection 6-bit x 8-bit x 2 PTNREN_A External clock noise rejecter selection Enable Disable D4 register D3 PTOUT PTM clock output control PTRUN PTM Run/Stop control On Run Off Stop D PSET PTM preset Preset No operation CKSEL PTM input clock selection External clock Internal clock FF3 D7 D4 register D3 PTOUT PTM clock output control PTRUN PTM Run/Stop control On Run Off Stop D PSET PTM preset Preset No operation CKSEL PTM input clock selection External clock Internal clock FF38 D7 MODE6_B PTM23 8/6-bit mode selection PTNREN_B External clock noise rejecter selection D4 D3 RPTOUT2 PTM2 inverted clock output control PTOUT2 PTM2 clock output control PTRUN2 PTM2 Run/Stop control D PSET2 PTM2 preset CKSEL2 PTM2 input clock selection FF39 D7 D4 RPTOUT3 PTM3 inverted clock output control D3 PTOUT3 PTM3 clock output control PTRUN3 PTM3 Run/Stop control D PSET3 PTM3 preset CKSEL3 PTM3 input clock selection FF4 D7 WDEN Watchdog timer enable FOUT2 FOUT frequency selection 6-bit x 8-bit x 2 Enable Disable On Off On Off Run Stop "" when being read Reserved register W "" when being read Constantly "" when being read Reserved register W "" when being read "" when being read Preset No operation W "" when being read External clock Internal clock On Off On Off Run Stop Preset No operation External clock Internal clock Enable Disable Constantly "" when being read W "" when being read D4 FOUT FOUT FOUT2 FOUT FOUT Frequency fosc3 / 8 fosc3 / 4 fosc3 / 2 fosc3 / fosc / 8 fosc / 4 fosc / 2 fosc / D3 FOUTON FOUT output control On Off WDRST Watchdog timer reset Reset No operation W Constantly "" when D TMRST Clock timer reset Reset No operation W being read TMRUN Clock timer Run/Stop control Run Stop 58 EPSON SC8865 TECHNICAL MANUAL

67 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports) DC output control PDP7D: FF62H PDP7D: FF63H How I/O port terminal Pxx data readout and output data settings are performed. When writing data: When "" is written: HIGH level When "" is written: LOW level When the I/O port is set to output mode, the data written is output as is to the I/O port terminal. In terms of port data, when "" is written, the port terminal goes to HIGH (VDD) level and when "" is written to a LOW (VSS) level. Even when the port is in input mode, data can still be written in. When reading out data: When "" is read: HIGH level ("") When "" is read: LOW level ("") When an I/O port is in input mode, the voltage level being input to the port terminal is read out. When terminal voltage is HIGH (VDD), it is read as a "", and when it is LOW (VSS), it is read as a "". Furthermore, in output mode, the contents of the data register are read out. At initial reset, this register is set to "" (HIGH level). Note: The data registers of the ports that are configured to the data bus, serial interface outputs and special outputs can be used as general purpose registers that do not affect the terminal inputs/outputs. IOCIOC7: FF6H IOCIOC7: FF6H Sets the I/O ports to input or output mode. When "" is written: Output mode When "" is written: Input mode Reading: Valid IOCxx is the I/O control register which correspond to each I/O port in a bit unit. Writing "" to the IOCxx register will switch the corresponding I/O port Pxx to output mode, and writing "" will switch it to input mode. When the special output is used, "" must always be set for the I/O control registers (IOC4IOC7) of I/O ports which will become output terminals. At initial reset, this register is set to "" (input mode). Note: The I/O control registers of the ports that are configured to the data bus, serial interface inputs/outputs and special outputs can be used as general purpose registers that do not affect the terminal inputs/outputs. PULPPULP7: FF64H PULPPULP7: FF65H The pull-up during the input mode are set with these registers. When "" is written: Pull-up ON When "" is written: Pull-up OFF Reading: Valid PULPxx is the pull-up control register corresponding to each I/O port (in bit units). When "Gate direct" is selected by mask option, the corresponding pull-up control register is disconnected from the input line, so it can be used as a general-purpose register. By writing "" to the PULPxx register, the corresponding I/O ports are pulled up (during input mode), while writing "" turns the pull-up function OFF. At initial reset, these registers are all set to "", so the pull-up function is set to ON. Note: The pull-up control registers of the ports that are configured to the serial interface outputs or special outputs can be used as general purpose registers that do not affect the pullup control. The pull-up control registers of the port that are configured to the serial interface inputs function the same as the I/O port. Special output control PTOUT: FF3H D3 PTOUT: FF3H D3 PTOUT2: FF38H D3 PTOUT3: FF39H D3 Controls the TOUT (programmable timer output clock) signal output. When "" is written: TOUT signal output When "" is written: DC output Reading: Valid PTOUTPTOUT3 are the output control registers for the TOUTTOUT3 signals. When PTOUT (or PTOUT) is set to "", the TOUT (or TOUT) signal is output from the P4 port terminal. When PTOUT2 (or PTOUT3) is set to "", the TOUT2 (or TOUT3) signal is output from the P5 port terminal. When "" is set, P4/P5 is set for DC output. At this time, settings of the I/O control register IOC4/IOC5 and data register P4D/P5D become invalid. At initial reset, PTOUT is set to "" (DC output). Note: If PTOUT and PTOUT are set to "" at the same time, PTOUT is effective. Similarly, if PTOUT2 and PTOUT3 are set to "", PTOUT3 is effective. Furthermore, if the programmable timer is set in 6-bit mode, the TOUT and TOUT2 signals cannot be output. SC8865 TECHNICAL MANUAL EPSON 59

68 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports) RPTOUT2: FF38H D4 RPTOUT3: FF39H D4 Controls the TOUT2/TOUT3 (inverted TOUT2/ TOUT3) signal output. When "" is written: TOUT signal output When "" is written: DC output Reading: Valid RPTOUT2 and RPTOUT3 are the output control registers for the TOUT2 and TOUT3 signals, respectively. When RPTOUT2 (or RPTOUT3) is set to "", the TOUT2 (or TOUT3) signal is output from the P7 port terminal. When "" is set, P7 is set for DC output. At this time, settings of the I/O control register IOC7 and data register P7D become invalid. At initial reset, RPTOUT is set to "" (DC output). Note: If RPTOUT2 and RPTOUT3 are set to "" at the same time, RPTOUT3 is effective. Furthermore, if the programmable timer is set in 6-bit mode, the TOUT2 signal cannot be output. FOUTON: FF4H D3 Controls the FOUT (fosc/fosc3 dividing clock) signal output. When "" is written: FOUT signal output When "" is written: DC output Reading: Valid FOUTON is the output control register for FOUT signal. When "" is set, the FOUT signal is output from the P6 port terminal and when "" is set, P6 is set for DC output. At this time, settings of the I/ O control register IOC6 and data register P6D become invalid. At initial reset, FOUTON is set to "" (DC output). FOUTFOUT2: FF4H D4 FOUT signal frequency is set as shown in Table Table FOUT frequency settings FOUT2 FOUT FOUT FOUT frequency fosc3 / 8 fosc3 / 4 fosc3 / 2 fosc3 / fosc / 8 fosc / 4 fosc / 2 fosc / fosc: OSC oscillation frequency fosc3: OSC3 oscillation frequency At initial reset, this register is set to "" (fosc/) Programming notes () When changing the port terminal in which the pull-up resistor is enabled from LOW level to HIGH, a delay in the waveform rise time will occur depending on the time constant of the pull-up resistor and the load capacitance of the terminal. It is necessary to set an appropriate wait time for introduction of an I/O port. Make this wait time the amount of time or more calculated by the following expression. Wait time = RIN x (CIN + load capacitance on the board) x.6 [sec] RIN: Pull up resistance Max. value CIN: Terminal capacitance Max. value (2) Since the special output signals (TOUT3, _ TOUT23, and FOUT) are generated asynchronously from the output control registers (PTOUT3, RPTOUT23, and FOUTON), when the signals is turned ON or OFF by the output control register settings, a hazard of a /2 cycle or less is generated. (3) When the FOUT frequency is made "fosc3/n", you must turn on the OSC3 oscillation circuit before outputting FOUT. A time interval of several msec to several msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes, is necessary, due to the oscillation element that is used. Consequently, if an abnormality occurs as the result of an unstable FOUT signal being output externally, you should allow an adequate waiting time after turning ON of the OSC3 oscillation, before turning outputting FOUT. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 8, "ELECTRICAL CHARACTERISTICS".) (4) The SLP instruction has executed when the _ special output signals (TOUT3, TOUT23, and FOUT) are in the enable status, an unstable clock is output for the special output at the time of return from the SLEEP state. Consequently, when shifting to the SLEEP state, you should set the special output signal to the disable status prior to executing the SLP instruction. 6 EPSON SC8865 TECHNICAL MANUAL

69 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) 5.8 Serial Interface 5.8. Configuration of serial interface The SC8865 incorporates a full duplex serial interface (when asynchronous system is selected) that allows the user to select either clock synchronous system or asynchronous system. The data transfer method can be selected in software. When the clock synchronous system is selected, 8- bit data transfer is possible. When the asynchronous system is selected, either 7- bit or 8-bit data transfer is possible, and a parity check of received data and the addition of a parity bit for transmitting data can automatically be done by selecting in software. Figure shows the configuration of the serial interface Switching of terminal functions Serial interface input/output terminals, SIN, SOUT, SCLK and SRDY are shared with I/O ports P P3. In order to utilize these terminals for the serial interface input/output terminals, "" must be written to the ESIF register. At initial reset, these terminals are set as I/O port terminals. The direction of I/O port terminals set for serial interface input/output terminals are determined by the signal and transfer mode for each terminal. Furthermore, the settings for the corresponding I/ O control registers for the I/O ports become invalid. Table Configuration of input/output terminals Terminal When serial interface is selected P SIN P SOUT P2 SCLK P3 SRDY * The terminals used may vary depending on the transfer mode. Data bus Serial I/O control & status register Received data buffer Error detection circuit Interrupt control circuit Interrupt request SIN(P) Serial input control circuit Received data shift register Transmitting data shift register Serial output control circuit SOUT(P) SCLK(P2) Start bit detection circuit Clock control circuit READY output control circuit Programmable timer underflow signal SRDY(P3) Fig Configuration of serial interface SC8865 TECHNICAL MANUAL EPSON 6

70 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) The serial interface terminals are configured according to the transfer mode set using the registers SM and SMD. SIN and SOUT are serial data input and output terminals which function identically in clock synchronous system and asynchronous system. SCLK is exclusively for use with clock synchronous system and functions as a synchronous clock input/output terminal. SRDY is exclusively for use in clock synchronous slave mode and functions as a send-receive ready signal output terminal. When asynchronous system is selected, since SCLK and SRDY are superfluous, the I/O port terminals P2 and P3 can be used as I/O ports. In the same way, when clock synchronous master mode is selected, since SRDY is superfluous, the I/O port terminal P3 can be used as I/O port Transfer modes There are four transfer modes for the serial interface and mode selection is made by setting the two bits of the mode selection registers SM and SMD as shown in the table below. Table Transfer modes SMD SM Mode Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master Table Terminal settings corresponding to each transfer mode Mode SIN SOUT SCLK SRDY Asynchronous 8-bit Input Output P2 P3 Asynchronous 7-bit Input Output P2 P3 Clock synchronous slave Input Output Input Output Clock synchronous master Input Output Output P3 At initial reset, transfer mode is set to clock synchronous master mode. Clock synchronous master mode In this mode, the internal clock is utilized as a synchronous clock for the built-in shift registers, and clock synchronous 8-bit serial transfers can be performed with this serial interface as the master. The synchronous clock is also output from the SCLK terminal which enables control of the external (slave side) serial I/O device. Since the SRDY terminal is not utilized in this mode, it can be used as an I/O port. Figure (a) shows the connection example of input/output terminals in the clock synchronous master mode. Clock synchronous slave mode In this mode, a synchronous clock from the external (master side) serial input/output device is utilized and clock synchronous 8-bit serial transfers can be performed with this serial interface as the slave. The synchronous clock is input to the SCLK terminal and is utilized by this interface as the synchronous clock. Furthermore, the SRDY signal indicating the transmit-receive ready status is output from the SRDY terminal in accordance with the serial interface operating status. In the slave mode, the settings for registers SCS and SCS used to select the clock source are invalid. Figure (b) shows the connection example of input/output terminals in the clock synchronous slave mode. Asynchronous 7-bit mode In this mode, asynchronous 7-bit transfer can be performed. Parity check during data reception and addition of parity bit (odd/even/none) during transmitting can be specified and data processed in 7 bits with or without parity. Since this mode employs the internal clock, the SCLK terminal is not used. Furthermore, since the SRDY terminal is not utilized either, both of these terminals can be used as I/O ports. Figure (c) shows the connection example of input/output terminals in the asynchronous mode. Asynchronous 8-bit mode In this mode, asynchronous 8-bit transfer can be performed. Parity check during data reception and addition of parity bit (odd/even/none) during transmitting can be specified and data processed in 8 bits with or without parity. Since this mode employs the internal clock, the SCLK terminal is not used. Furthermore, since the SRDY terminal is not utilized either, both of these terminals can be used as I/O ports. Figure (c) shows the connection example of input/output terminals in the asynchronous mode. 62 EPSON SC8865 TECHNICAL MANUAL

71 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) SC8865 SIN(P) SOUT(P) SCLK(P2) Input port(kxx) SC8865 SIN(P) SOUT(P) SCLK(P2) SRDY(P3) External serial device Data input Data output CLOCK input READY output (a) Clock synchronous master mode External serial device Data input Data output CLOCK output READY input (b) Clock synchronous slave mode SC8865 SIN(P) SOUT(P) (c) Asynchronous 7-bit/8-bit mode Fig Connection examples of serial interface I/O terminals Clock source External serial device Data input Data output There are four clock sources and selection is made by setting the two bits of the clock source selection register SCS and SCS as shown in table below. Table Clock source SCS SCS Clock source Programmable timer fosc3 / 4 fosc3 / 8 fosc3 / 6 OSC3 oscillation circuit fosc3 This register setting is invalid in clock synchronous slave mode and the external clock input from the SCLK terminal is used. When the "programmable timer" is selected, the programmable timer underflow signal is divided by 2 and this signal is used as the clock source. With respect to the transfer rate setting, see "5. Programmable Timer". At initial reset, the synchronous clock is set to "fosc3/6". Whichever clock is selected, the signal is further divided by 6 and then used as the synchronous clock. Furthermore, external clock input is used as is for SCLK in clock synchronous slave mode. Table shows an examples of transfer rates and OSC3 oscillation frequencies when the clock source is set to programmable timer. When the demultiplied signal of the OSC3 oscillation circuit is made the clock source, it is necessary to turn the OSC3 oscillation ON, prior to using the serial interface. A time interval of several msec to several msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes, is necessary, due to the oscillation element that is used. Consequently, you should allow an adequate waiting time after turning ON of the OSC3 oscillation, before starting transmitting/receiving of serial interface. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 8, "ELECTRICAL CHARACTERISTICS".) At initial reset, the OSC3 oscillation circuit is set to ON status. /4 /8 Divider /6 Selector /6 Selector Synchronous clock Fig Programmable timer underflow signal /2 Division of the synchronous clock (Clock synchronous slave mode) SCLK Table OSC3 oscillation frequencies and transfer rates OSC3 oscillation frequency / Programmable timer settings Transfer rate fosc3 = MHz fosc3 = 3.72 MHz fosc3 = MHz (bps) PSTX RDRX PSTX RDRX PSTX RDRX 9,2 9,6 4,8 2,4, H H H H H H 2H 2H 3H 7H FH FH 3FH 7FH FH 3FH H H H H H H 3H 3H 4H 9H 3H 27H 4FH 9FH 9H 3H H H H H H H H 2H 5H BH 7H 2FH 5FH BFH BFH 5FH Since the underflow signal only is used as the clock source, the CDRX register value does not affect the transfer rates. SC8865 TECHNICAL MANUAL EPSON 63

72 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Transmit-receive control Below is a description of the registers which handle transmit-receive control. With respect to transmitreceive control procedures and operations, please refer to the following sections in which these are discussed on a mode by mode basis. Shift register and received data buffer Exclusive shift registers for transmitting and receiving are installed in this serial interface. Consequently, duplex communication simultaneous transmit and receive is possible when the asynchronous system is selected. Data being transmitted are written to TRX TRXD7 and converted to serial through the shift register and is output from the SOUT terminal. In the reception section, a received data buffer is installed separate from the shift register. Data being received are input to the SIN terminal and is converted to parallel through the shift register and written to the received data buffer. Since the received data buffer can be read even during serial input operation, the continuous data is received efficiently. However, since buffer functions are not used in clock synchronous mode, be sure to read out data before the next data reception begins. Transmit enable register and transmit control bit For transmitting control, use the transmit enable register TXEN and transmit control bit TXTRG. The transmit enable register TXEN is used to set the transmitting enable/disable status. When "" is written to this register to set the transmitting enable status, clock input to the shift register is enabled and the system is ready to transmit data. In the clock synchronous mode, synchronous clock input/ output from the SCLK terminal is also enabled. The transmit control bit TXTRG is used as the trigger to start transmitting data. Data to be transmitted is written to the transmit data shift register, and when transmitting preparations a recomplete, "" is written to TXTRG whereupon data transmitting begins. When interrupt has been enabled, an interrupt is generated when the transmission is completed. If there is subsequent data to be transmitted it can be sent using this interrupt. In addition, TXTRG can be read as the status. When set to "", it indicates transmitting operation, and "" indicates transmitting stop. For details on timing, see the timing chart which gives the timing for each mode. When not transmitting, set TXEN to "" to disable transmitting status. Receive enable register, receive control bit For receiving control, use the receive enable register RXEN and receive control bit RXTRG. Receive enable register RXEN is used to set receiving enable/disable status. When "" is written into this register to set the receiving enable status, clock input to the shift register is enabled and the system is ready to receive data. In the clock synchronous mode, synchronous clock input/output from the SCLK terminal is also enabled. With the above setting, receiving begins and serial data input from the SIN terminal goes to the shift register. The operation of the receive control bit RXTRG is slightly different depending on whether a clock synchronous system or an asynchronous system is being used. In the clock synchronous system, the receive control bit RXTRG is used as the trigger to start receiving data. When received data has been read and the preparation for next data receiving is completed, write "" into RXTRG to start receiving. (When "" is written to RXTRG in slave mode, SRDY switches to "".) In an asynchronous system, RXTRG is used to prepare for next data receiving. After reading the received data from the received data buffer, write "" into RXTRG to signify that the received data buffer is empty. If "" is not written into RXTRG, the overrun error flag OER will be set to "" when the next receiving operation is completed. (An overrun error will be generated when receiving is completed between reading the received data and the writing of "" to RXTRG.) In addition, RXTRG can be read as the status. In either clock synchronous mode or asynchronous mode, when RXTRG is set to "", it indicates receiving operation and when set to "", it indicates that receiving has stopped. For details on timing, see the timing chart which gives the timing for each mode. When you do not receive, set RXEN to "" to disable receiving status. 64 EPSON SC8865 TECHNICAL MANUAL

73 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Operation of clock synchronous transfer Clock synchronous transfer involves the transfer of 8-bit data by synchronizing it to eight clocks. The same synchronous clock is used by both the transmitting and receiving sides. When the serial interface is used in the master mode, the clock signal selected using SCS and SCS is further divided by /6 and employed as the synchronous clock. This signal is then sent via the SCLK terminal to the slave side (external serial I/O device). When used in the slave mode, the clock input to the SCLK terminal from the master side (external serial input/output device) is used as the synchronous clock. In the clock synchronous mode, since one clock line (SCLK) is shared for both transmitting and receiving, transmitting and receiving cannot be performed simultaneously. (Half duplex only is possible in clock synchronous mode.) The transfer data length is fixed at 8 bits. Data can be switched using a register whether it is transmitted/received from LSB (bit ) or MSB (bit 7). LSB first SCLK Data MSB first SCLK Data LSB MSB D D3 D4 D7 MSB LSB D7 D4 D3 D Fig Transfer data configuration using clock synchronous mode Below is a description of initialization when performing clock synchronous transfer, transmitreceive control procedures and operations. With respect to serial interface interrupt, see "5.8.8 Interrupt function". Initialization of serial interface When performing clock synchronous transfer, the following initial settings must be made. () Setting of transmitting/receiving disable To set the serial interface into a status in which both transmitting and receiving are disabled, "" must be written to both the transmit enable register TXEN and the receive enable register RXEN. Fix these two registers to a disable status until data transfer actually begins. (2) Port selection Because serial interface input/output ports SIN, SOUT, SCLK and SRDY are set as I/O port terminals PP3 at initial reset, "" must be written to the serial interface enable register ESIF in order to set these terminals for serial interface use. (3) Setting of transfer mode Select the clock synchronous mode by writing the data as indicated below to the two bits of the mode selection registers SM and SMD. Master mode: SM = "", SMD = "" Slave mode: SM = "", SMD = "" (4) Clock source selection In the master mode, select the synchronous clock source by writing data to the two bits of the clock source selection registers SCS and SCS. (See Table ) This selection is not necessary in the slave mode. Since all the registers mentioned in (2)(4) are assigned to the same address, it's possible to set them all with one instruction. The parity enable register EPR is also assigned to this address, however, since parity is not necessary in the clock synchronous mode, parity check will not take place regardless of how they are set. (5) Clock source control When the master mode is selected and programmable timer for the clock source is selected, set transfer rate on the programmable timer side. (See "5. Programmable Timer".) When the divided signal of OSC3 oscillation circuit is selected for the clock source, be sure that the OSC3 oscillation circuit is turned ON prior to commencing data transfer. (See "5.4 Oscillation Circuits".) (6) Serial data input/output permutation The SC8865 provides the data input/output permutation select register SDP to select whether the serial data bits are transfered from the LSB or MSB. The SDP register should be set before writing data to TRXTRXD7. SC8865 TECHNICAL MANUAL EPSON 65

74 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Data transmit procedure The control procedure and operation during transmitting is as follows. () Write "" in the transmit enable register TXEN and the receive enable register RXEN to reset the serial interface. (2) Write "" in the transmit enable register TXEN to set into the transmitting enable status. (3) Write the transmitting data into TRX TRXD7. (4) In case of the master mode, confirm the receive ready status on the slave side (external serial input/output device), if necessary. Wait until it reaches the receive ready status. (5) Write "" in the transmit control bit TXTRG and start transmitting. In the master mode, this control causes the synchronous clock to change to enable and to be provided to the shift register for transmitting and output from the SCLK terminal. In the slave mode, it waits for the synchronous clock to be input from the SCLK terminal. The transmitting data of the shift register shifts one bit at a time at each falling edge of the synchronous clock and is output from the SOUT terminal. When the final bit (MSB when "LSB first" is selected, or LSB when "MSB first" is selected) is output, the SOUTx terminal is maintained at that level, until the next transmitting begins. The transmitting complete interrupt factor flag FSTRA is set to "" at the point where the data transmitting of the shift register is completed. When interrupt has been enabled, a transmitting complete interrupt is generated at this point. Set the following transmitting data using this interrupt. (6) Repeat steps (3) to (5) for the number of bytes of transmitting data, and then set the transmit disable status by writing "" to the transmit enable register TXEN, when the transmitting is completed. Data transmitting TXEN, RXEN TXEN Set transmitting data to TRXTRXD7 No Receiver ready? In case of master mode Yes TXTRG No FSTRA =? Yes No Transmit complete? Yes TXEN End Fig Transmit procedure in clock synchronous mode 66 EPSON SC8865 TECHNICAL MANUAL

75 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Data receive procedure The control procedure and operation during receiving is as follows. () Write "" in the receive enable register RXEN and transmit enable register TXEN to reset the serial interface. (2) Write "" in the receive enable register RXEN to set into the receiving enable status. (3) In case of the master mode, confirm the transmit ready status on the slave side (external serial input/output device), if necessary. Wait until it reaches the transmit ready status. (4) Write "" in the receive control bit RXTRG and start receiving. In the master mode, this control causes the synchronous clock to change to enable and is provided to the shift register for receiving and output from the SCLK terminal. In the slave mode, it waits for the synchronous clock to be input from the SCLK terminal. The received data input from the SIN terminal is successively incorporated into the shift register in synchronization with the rising edge of the synchronous clock. At the point where the data of the 8th bit has been incorporated at the final (8th) rising edge of the synchronous clock, the content of the shift register is sent to the received data buffer and the receiving complete interrupt factor flag FSREC is set to "". When interrupt has been enabled, a receiving complete interrupt is generated at this point. (5) Read the received data from TRXTRXD7 using receiving complete interrupt. (6) Repeat steps (3) to (5) for the number of bytes of receiving data, and then set the receive disable status by writing "" to the receive enable register RXEN, when the receiving is completed. Data receiving RXEN, TXEN RXEN No Transmitter ready? In case of master mode Yes RXTRG No FSREC =? Yes Received data reading from TRXTRXD7 No Receiving complete? Yes RXEN End Fig Receiving procedure in clock synchronous mode SC8865 TECHNICAL MANUAL EPSON 67

76 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Transmit/receive ready (SRDY) signal When this serial interface is used in the clock synchronous slave mode (external clock input), an SRDY signal is output to indicate whether or not this serial interface can transmit/receive to the master side (external serial input/output device). This signal is output from the SRDY terminal and when this interface enters the transmit or receive enable (READY) status, it becomes "" (LOW level) and becomes "" (HIGH level) when there is a BUSY status, such as during transmit/receive operation. The SRDY signal changes the "" to "," immediately after writing "" into the transmit control bit TXTRG or the receive control bit RXTRG and returns from "" to "", at the point where the first synchronous clock has been input (falling edge). When you have set in the master mode, control the transfer by inputting the same signal from the slave side using the input port or I/O port. At this time, since the SRDY terminal is not set and instead P3 functions as the I/O port, you can apply this port for said control. Timing chart The timing chart for the clock synchronous system transmission is shown in Figure TXEN TXTRG (RD) TXTRG (WR) SCLK SOUT D D3 D4 D7 Interrupt (a) Transmit timing for master mode RXEN RXTRG (RD) RXTRG (WR) SCLK SIN D D3 D4 D7 TRXD 7F st data Interrupt (c) Receive timing for master mode TXEN TXTRG (RD) RXEN RXTRG (RD) TXTRG (WR) SCLK SOUT D D3 D4 D7 SRDY Interrupt (b) Transmit timing for slave mode RXTRG (WR) SCLK SIN D D3 D4 D7 TRXD 7F st data SRDY Interrupt (d) Receive timing for slave mode 7F Fig Timing chart (clock synchronous system transmission, LSB first) 68 EPSON SC8865 TECHNICAL MANUAL

77 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Operation of asynchronous transfer Asynchronous transfer is a mode that transfers by adding a start bit and a stop bit to the front and the back of each piece of serial converted data. In this mode, there is no need to use a clock that is fully synchronized clock on the transmit side and the receive side, but rather transmission is done while adopting the synchronization at the start/stop bits that have attached before and after each piece of data. The RS-232C interface functions can be easily realized by selecting this transfer mode. This interface has separate transmit and receive shift registers and is designed to permit full duplex transmission to be done simultaneously for transmitting and receiving. For transfer data in the asynchronous 7-bit mode, either 7 bits data (no parity) or 7 bits data + parity bit can be selected. In the asynchronous 8-bit mode, either 8 bits data (no parity) or 8 bits data + parity bit can be selected. Parity can be even or odd, and parity checking of received data and adding a party bit to transmitting data will be done automatically. Thereafter, it is not necessary to be conscious of parity itself in the program. The start bit length is fixed at bit. For the stop bit length, either bit or 2 bits can be selected using the stop bit select register STPB. Whether data is transmitted/received from LSB (bit ) or MSB (bit 7) it can be switched using the data input/output permutation select register SDP. LSB first Sampling clock 7bit data 7bit data +parity 8bit data 8bit data +parity MSB first Sampling clock 7bit data 7bit data +parity 8bit data 8bit data +parity s s s s s s D D3 D4 D D3 D4 D D3 D4 D7 D4 D3 D D4 D3 D D7 D4 D3 D p s2 s2 s D7 D4 D3 D p s2 s : Start bit (Low level, bit) s2 : Stop bit (High level, bit or 2 bits) p : Parity bit p s2 s2 s2 s D D3 D4 D7 p s2 Fig Transfer data configuration for asynchronous system Here following, we will explain the control sequence and operation for initialization and transmitting /receiving in case of asynchronous data transfer. See "5.8.8 Interrupt function" for the serial interface interrupts. s2 Initialization of serial interface The below initialization must be done in cases of asynchronous system transfer. () Setting of transmitting/receiving disable To set the serial interface into a status in which both transmitting and receiving are disabled, "" must be written to both the transmit enable register TXEN and the receive enable register RXEN. Fix these two registers to a disable status until data transfer actually begins. (2) Port selection Because serial interface input/output terminals SIN and SOUT are set as I/O port terminals P and P at initial reset, "" must be written to the serial interface enable register ESIF in order to set these terminals for serial interface use. SCLK and SRDY terminals set in the clock synchronous mode are not used in the asynchronous mode. These terminals function as I/O port terminals P2 and P3. (3) Setting of transfer mode Select the asynchronous mode by writing the data as indicated below to the two bits of the mode selection registers SM and SMD. 7-bit mode: SM = "", SMD = "" 8-bit mode: SM = "", SMD = "" (4) Parity bit selection When checking and adding parity bits, write "" into the parity enable register EPR to set to "with parity check". As a result of this setting, in the asynchronous 7-bit mode, it has a 7 bits data + parity bit configuration and in the asynchronous 8-bit mode it has an 8 bits data + parity bit configuration.in this case, parity checking for receiving and adding a party bit for transmitting is done automatically in hardware. Moreover, when "with parity check" has been selected, "odd" or "even" parity must be further selected in the parity mode selection register PMD. When "" is written to the PMD register to select "without parity check" in the asynchronous 7-bit mode, data configuration is set to 7 bits data (no parity) and in the asynchronous 8-bit mode (no parity) it is set to 8 bits data (no parity) and parity checking and parity bit adding will not be done. (5) Clock source selection Select the clock source by writing data to the two bits of the clock source selection registers SCS and SCS. (See Table ) Since all the registers mentioned in (2)(5) are assigned to the same address, it's possible to set them all with one instruction. SC8865 TECHNICAL MANUAL EPSON 69

78 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) (6) Clock source control When the programmable timer is selected for the clock source, set transfer rate on the programmable timer side. (See "5. Programmable Timer".) When the divided signal of OSC3 oscillation circuit is selected for the clock source, be sure that the OSC3 oscillation circuit is turned ON prior to commencing data transfer. (See "5.4 Oscillation Circuits".) (7) Stop bit length selection The stop bit length can be configured to bit or 2 bits using the stop bit select register STPB. Table Stop bit and parity bit settings STPB EPR PMD Settings Stop bit Parity bit 2 bits 2 bits 2 bits bit bit bit Odd Even Non parity Odd Even Non parity (8) Serial data input/output permutation The SC8865 provides the data input/output permutation select register SDP to select whether the serial data bits are transfered from the LSB or MSB. The SDP register should be set before writing data to TRXTRXD7. Data transmit procedure The control procedure and operation during transmitting is as follows. () Write "" in the transmit enable register TXEN to reset the serial interface. (4) Write "" in the transmit control bit TXTRG and start transmitting. This control causes the shift clock to change to enable and a start bit (LOW) is output to the SOUT terminal in synchronize to its rising edge. The transmitting data set to the shift register is shifted one bit at a time at each rising edge of the clock thereafter and is output from the SOUT terminal. After the data output, it outputs a stop bit (HIGH) and HIGH level is maintained until the next start bit is output. The transmitting complete interrupt factor flag FSTRA is set to "" at the point where the data transmitting is completed. When interrupt has been enabled, a transmitting complete interrupt is generated at this point. Set the following transmitting data using this interrupt. (5) Repeat steps (3) to (4) for the number of bytes of transmitting data, and then set the transmit disable status by writing "" to the transmit enable register TXEN, when the transmitting is completed. Data transmitting TXEN TXEN Set transmitting data to TRXTRXD7 TXTRG (2) Write "" in the transmit enable register TXEN to set into the transmitting enable status. (3) Write the transmitting data into TRXTRXD7. Also, when 7-bit data is selected, the TRXD7 data becomes invalid. No FSTRA =? Yes Transmit complete? Yes TXEN No End Fig Transmit procedure in asynchronous mode 7 EPSON SC8865 TECHNICAL MANUAL

79 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Data receive procedure The control procedure and operation during receiving is as follows. () Write "" in the receive enable register RXEN to set the receiving disable status and to reset the respective PER, OER, FER flags that indicate parity, overrun and framing errors. (2) Write "" in the receive enable register RXEN to set into the receiving enable status. (3) The shift clock will change to enable from the point where the start bit (LOW) has been input from the SIN terminal and the receive data will be synchronized to the rising edge following the second clock, and will thus be successively incorporated into the shift register. After data bits have been incorporated, the stop bit is checked and, if it is not HIGH, it becomes a framing error and the error interrupt factor flag FSERR is set to "". When interrupt has been enabled, an error interrupt is generated at this point. When receiving is completed, data in the shift register is transferred to the received data buffer and the receiving complete interrupt flag FSREC is set to "". When interrupt has been enabled, a receiving complete interrupt is generated at this point. (When an overrun error is generated, the interrupt factor flag FSREC is not set to "" and a receiving complete interrupt is not generated.) If "with parity check" has been selected, a parity check is executed when data is transferred into the received data buffer from the shift register and if a parity error is detected, the error interrupt factor flag is set to "". When the interrupt has been enabled, an error interrupt is generated at this point just as in the framing error mentioned above. (4) Read the received data from TRXTRXD7 using receiving complete interrupt. (5) Write "" to the receive control bit RXTRG to inform that the receive data has been read out. When the following data is received prior to writing "" to RXTRG, it is recognized as an overrun error and the error interrupt factor flag is set to "". When the interrupt has been enabled, an error interrupt is generated at this point just as in the framing error and parity error mentioned above. (6) Repeat steps (3) to (5) for the number of bytes of receiving data, and then set the receive disable status by writing "" to the receive enable register RXEN, when the receiving is completed. No No Data receiving RXEN Resets error flags PER, OER and FER RXEN Error generated? Receiving interrupt? Yes Received data reading from TRXTRXD7 RXTRG Receiving complete? Yes RXEN End No Yes Error processing Fig Receiving procedure in asynchronous mode SC8865 TECHNICAL MANUAL EPSON 7

80 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Receive error During receiving the following three types of errors can be detected by an interrupt. () Parity error When writing "" to the EPR register to select "with parity check", a parity check (vertical parity check) is executed during receiving. After each data bit is sent a parity check bit is sent. The parity check bit is a "" or a "". Even parity checking will cause the sum of the parity bit and the other bits to be even. Odd parity causes the sum to be odd. This is checked on the receiving side. The parity check is performed when data received in the shift register is transferred to the received data buffer. It checks whether the parity check bit is a "" or a "" (the sum of the bits including the parity bit) and the parity set in the PMD register match. When it does not match, it is recognized as an parity error and the parity error flag PER and the error interrupt factor flag FSERR are set to "". When interrupt has been enabled, an error interrupt is generated at this point. The PER flag is reset to "" by writing "". Even when this error has been generated, the received data corresponding to the error is transferred in the received data buffer and the receive operation also continues. The received data at this point cannot assured because of the parity error. (2) Framing error In asynchronous transfer, synchronization is adopted for each character at the start bit ("") and the stop bit (""). When receiving has been done with the stop bit set at "", the serial interface judges the synchronization to be off and a framing error is generated. When this error is generated, the framing error flag FER and the error interrupt factor flag FSERR are set to "". When interrupt has been enabled, an error interrupt is generated at this point. The FER flag is reset to "" by writing "". Even when this error has been generated, the received data for it is loaded into the receive data buffer and the receive operation also continues. However, even when it does not become a framing error with the following data receipt, such data cannot be assured. Even when this error has been generated, the received data corresponding to the error is transferred in the received data buffer and the receive operation also continues. However, even when it does not become a framing error with the following data receiving, such data cannot be assured. (3) Overrun error When the next data is received before "" is written to RXTRG, an overrun error will be generated, because the previous receive data will be overwritten. When this error is generated, the overrun error flag OER and the error interrupt factor flag FSERR are set to "". When interrupt has been enabled, an error interrupt is generated at this point. The OER flag is reset to "" by writing "" into it. Even when this error has been generated, the received data corresponding to the error is transferred in the received data buffer and the receive operation also continues. Furthermore, when the timing for writing "" to RXTRG and the timing for the received data transfer to the received data buffer overlap, it will be recognized as an overrun error. Timing chart Figure show the asynchronous transfer timing chart. 72 EPSON SC8865 TECHNICAL MANUAL

81 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) TXEN TXTRG(RD) TXTRG(WR) Sumpling clock SOUT D D3 D4 D7 (In 8-bit mode/non parity) Interrupt (a) Transmit timing RXEN RXTRG(RD) RXTRG(WR) Sumpling clock SIN D D3 D4 D7 D D3 D4 D7 D D3 D4 D7 (In 8-bit mode/non parity) TRXD st data 2st data OER control signal OER Interrupt (b) Receive timing Fig Timing chart (asynchronous transfer, LSB first, stop bit = bit) Interrupt function This serial interface includes a function that generates the below indicated three types of interrupts. Transmitting complete interrupt Receiving complete interrupt Error interrupt The interrupt factor flag FSxxx and the interrupt enable register ESxxx for the respective interrupt factors are provided and then the interrupt enable/ disable can be selected by the software. In addition, a priority level of the serial interface interrupt for the CPU can be optionally set at levels to 3 by the interrupt priority registers PSIF and PSIF. For details on the above mentioned interrupt control register and the operation following generation of an interrupt, see "5.4 Interrupt and Standby Status". Figure shows the configuration of the serial interface interrupt circuit. Transmitting complete interrupt This interrupt factor is generated at the point where the sending of the data written into the shift register has been completed and sets the interrupt factor flag FSTRA to "". When set in this manner, if the corresponding interrupt enable register ESTRA is set to "" and the corresponding interrupt priority registers PSIF and PSIF are set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. When "" has been written into the interrupt enable register ESTRA and interrupt has been disabled, an interrupt is not generated to the CPU. Even in this case, the interrupt factor flag FSTRA is set to "". The interrupt factor flag FSTRA is reset to "" by writing "". The following transmitting data can be set and the transmitting start (writing "" to TXTRG) can be controlled by generation of this interrupt factor. The exception processing vector address is set as follows: Transmitting complete interrupt: 2CH SC8865 TECHNICAL MANUAL EPSON 73

82 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Address Interrupt priority register PSIF, PSIF Error generation Address Interrupt factor flag FSERR Address Interrupt enable register ESERR Data bus Receive completion Address Address Interrupt factor flag FSREC Interrupt enable register ESREC Interrupt priority level judgement circuit Interrupt request Transmit completion Address Interrupt factor flag FSTRA Address Interrupt enable register ESTRA Fig Configuration of serial interface interrupt circuit Receiving complete interrupt This interrupt factor is generated at the point where receiving has been completed and the receive data incorporated into the shift register has been transferred into the received data buffer and it sets the interrupt factor flag FSREC to "". When set in this manner, if the corresponding interrupt enable register ESREC is set to "" and the corresponding interrupt priority registers PSIF and PSIF are set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. When "" has been written into the interrupt enable register ESREC and interrupt has been disabled, an interrupt is not generated to the CPU. Even in this case, the interrupt factor flag FSREC is set to "". The interrupt factor flag FSREC is reset to "" by writing "". The generation of this interrupt factor permits the received data to be read. Also, the interrupt factor flag is set to "" when a parity error or framing error is generated. The exception processing vector address is set as follows: Receiving complete interrupt: 2AH. Error interrupt This interrupt factor is generated at the point where a parity error, framing error or overrun error is detected during receiving and it sets the interrupt factor flag FSERR to "". When set in this manner, if the corresponding interrupt enable register ESERR is set to "" and the corresponding interrupt priority registers PSIF and PSIF are set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. When "" has been written in the interrupt enable register ESERR and interrupt has been disabled, an interrupt is not generated to the CPU. Even in this case, the interrupt factor flag FSERR is set to "". The interrupt factor flag FSERR is reset to "" by writing "". Since all three types of errors result in the same interrupt factor, you should identify the error that has been generated by the error flags PER (parity error), OER (overrun error) and FER (framing error). The exception processing vector address is set as follows: Receive error interrupt: 28H. 74 EPSON SC8865 TECHNICAL MANUAL

83 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Control of serial interface Table show the serial interface control bits. Table (a) Serial interface control bits Address Bit Name Function SR FF48 D7 EPR PMD D4 SCS D3 SCS SMD D SM ESIF FF49 D7 FER PER D4 OER D3 RXTRG RXEN D TXTRG TXEN Parity enable register Parity mode selection Clock source selection SCS SCS Clock source Programmable timer fosc3 / 4 fosc3 / 8 fosc3 / 6 Serial I/F mode selection SMD SM Mode Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master Serial I/F enable register Serial I/F framing error flag Serial I/F parity error flag Serial I/F overrun error flag Serial I/F receive trigger/status Serial I/F receive enable Serial I/F transmit trigger/status Serial I/F transmit enable FF4A D7 D4 D3 D TRXD7 TRX TRX TRXD4 TRXD3 TRX TRXD TRX Serial I/F transmit/receive data D7 (MSB) Serial I/F transmit/receive data Serial I/F transmit/receive data Serial I/F transmit/receive data D4 Serial I/F transmit/receive data D3 Serial I/F transmit/receive data Serial I/F transmit/receive data D Serial I/F transmit/receive data (LSB) FF4B D7 D4 D3 D STPB Serial I/F stop bit selection SDP Serial I/F data input/output permutation selection R W R W R W R W R W With parity Odd Serial I/F Error Reset () Error Reset () Error Reset () Run Trigger Enable Run Trigger Enable High 2 bits MSB first Non parity Even I/O port No error No operation No error No operation No error No operation Stop No operation Disable Stop No operation Disable Low X bit LSB first Comment "" when being read Only for asynchronous mode In the clock synchronous slave mode, external clock is selected. "" when being read Only for asynchronous mode Constantly "" when being read SC8865 TECHNICAL MANUAL EPSON 75

84 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Table (b) Serial interface control bits Address Bit Name Function SR Comment FF2 D7 PK KK7 interrupt priority register PK PK Priority PSIF PSIF level PK Level 3 PSIF Serial interface interrupt priority register Level 2 Level D4 PSIF Level D3 Constantly "" when being read D PTM Clock timer interrupt priority register PTM PTM Priority level Level 3 PTM Level 2 Level Level FF23 D7 D4 D3 Constantly "" when being read ESERR Serial I/F (error) interrupt enable register Interrupt Interrupt D ESREC Serial I/F (receiving) interrupt enable register enable disable ESTRA Serial I/F (transmitting) interrupt enable register FF27 D7 D4 Constantly "" when being read D3 FSERR D FSREC FSTRA Serial I/F (error) interrupt factor flag Serial I/F (receiving) interrupt factor flag Serial I/F (transmitting) interrupt factor flag (R) Generated (W) Reset (R) No generated (W) No operation ESIF: FF48H Sets the serial interface terminals (PP3). When "" is written: Serial input/output terminal When "" is written: I/O port terminal Reading: Valid The ESIF is the serial interface enable register and PP3 terminals become serial input/output terminals (SIN, SOUT, SCLK, SRDY) when "" is written, and they become I/O port terminals when "" is written. Also, see Table for the terminal settings according to the transfer modes. At initial reset, ESIF is set to "" (I/O port). SM, SMD: FF48H D, Set the transfer modes according to Table Table Transfer mode settings SMD SM Mode Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master SM and SMD can also read out. At initial reset, this register is set to "" (clock synchronous master mode). 76 EPSON SC8865 TECHNICAL MANUAL

85 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) SCS, SCS: FF48H D3, D4 Select the clock source according to Table Table Clock source selection SCS SCS Clock source Programmable timer fosc3 / 4 fosc3 / 8 fosc3 / 6 SCS and SCS can also be read out. In the clock synchronous slave mode, setting of this register is invalid. At initial reset, this register is set to "" (fosc3/6). SDP: FF4BH Selects the serial data input/output permutation. When "" is written: MSB first When "" is written: LSB first Reading: Valid Select whether the data input/output permutation will be MSB first or LSB first. At initial reset, SDP is set to "" (LSB first). STPB: FF4BH D Selects the stop bit length for asynchronous data transfer. When "" is written: 2 bits When "" is written: bit Reading: Valid STPB is the stop bit select register that is effective in asynchronous mode. When "" is written to STPB, the stop bit length is set to 2 bits, and when "" is written, it is set to bit. In clock synchronous mode, no start/stop bits can be added to transfer data. Therefore, setting STPB becomes invalid. At initial reset, STPB is set to "" ( bit). EPR: FF48H Selects the parity function. When "" is written: With parity When "" is written: Non parity Reading: Valid Selects whether or not to check parity of the received data and to add a parity bit to the transmitting data. When "" is written to EPR, the most significant bit of the received data is considered to be the parity bit and a parity check is executed. A parity bit is added to the transmitting data. When "" is written, neither checking is done nor is a parity bit added. Parity is valid only in asynchronous mode and the EPR setting becomes invalid in the clock synchronous mode. At initial reset, EPR is set to "" (non parity). PMD: FF48H Selects odd parity/even parity. When "" is written: Odd parity When "" is written: Even parity Reading: Valid When "" is written to PMD, odd parity is selected and even parity is selected when "" is written. The parity check and addition of a parity bit is only valid when "" has been written to EPR. When "" has been written to EPR, the parity setting by PMD becomes invalid. At initial reset, PMD is set to "" (even parity). TXEN: FF49H Sets the serial interface to the transmitting enable status. When "" is written: Transmitting enable When "" is written: Transmitting disable Reading: Valid When "" is written to TXEN, the serial interface shifts to the transmitting enable status and shifts to the transmitting disable status when "" is written. Set TXEN to "" when making the initial settings of the serial interface and similar operations. At initial reset, TXEN is set to "" (transmitting disable). TXTRG: FF49H D Functions as the transmitting start trigger and the operation status indicator (transmitting/stop status). When "" is read: During transmitting When "" is read: During stop When "" is written: Transmitting start When "" is written: Invalid Starts the transmitting when "" is written to TXTRG after writing the transmitting data. TXTRG can be read as the status. When set to "", it indicates transmitting operation, and "" indicates transmitting stop. At initial reset, TXTRG is set to "" (during stop). RXEN: FF49H Sets the serial interface to the receiving enable status. When "" is written: Receiving enable When "" is written: Receiving disable Reading: Valid When "" is written to RXEN, the serial interface shifts to the receiving enable status and shifts to the receiving disable status when "" is written. Set RXEN to "" when making the initial settings of the serial interface and similar operations. At initial reset, RXEN is set to "" (receiving disable). SC8865 TECHNICAL MANUAL EPSON 77

86 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) RXTRG: FF49H D3 Functions as the receiving start trigger or preparation for the following data receiving and the operation status indicator (during receiving/during stop). When "" is read: During receiving When "" is read: During stop When "" is written: Receiving start/following data receiving preparation When "" is written: Invalid RXTRG has a slightly different operation in the clock synchronous system and the asynchronous system. The RXTRG in the clock synchronous system, is used as the trigger for the receiving start. Writes "" into RXTRG to start receiving at the point where the receive data has been read and the following receive preparation has been done. (In the slave mode, SRDY becomes "" at the point where "" has been written into into the RXTRG.) RXTRG is used in the asynchronous system for preparation of the following data receiving. Reads the received data located in the received data buffer and writes "" into RXTRG to inform that the received data buffer has shifted to empty. When "" has not been written to RXTRG, the overrun error flag OER is set to "" at the point where the following receiving has been completed. (When the receiving has been completed between the operation to read the received data and the operation to write "" into RXTRG, an overrun error occurs.) In addition, RXTRG can be read as the status. In either clock synchronous mode or asynchronous mode, when RXTRG is set to "", it indicates receiving operation and when set to "", it indicates that receiving has stopped. At initial reset, RXTRG is set to "" (during stop). TRXTRXD7: FF4AH During transmitting Write the transmitting data into the transmit shift register. When "" is written: HIGH level When "" is written: LOW level Write the transmitting data prior to starting transmitting. In the case of continuous transmitting, wait for the transmitting complete interrupt, then write the data. The TRXD7 becomes invalid for the asynchronous 7-bit mode. Converted serial data for which the bits set at "" as HIGH (VDD) level and for which the bits set at "" as LOW (VSS) level are output from the SOUT terminal. During receiving Read the received data. When "" is read: HIGH level When "" is read: LOW level The data from the received data buffer can be read out. Since the sift register is provided separately from this buffer, reading can be done during the receive operation in the asynchronous mode. (The buffer function is not used in the clock synchronous mode.) Read the data after waiting for the receiving complete interrupt. When performing parity check in the asynchronous 7-bit mode, "" is loaded into the 8th bit (TRXD7) that corresponds to the parity bit. The serial data input from the SIN terminal is level converted, making the HIGH (VDD) level bit "" and the LOW (VSS) level bit "" and is then loaded into this buffer. At initial reset, the buffer content is undefined. OER: FF49H D4 Indicates the generation of an overrun error. When "" is read: Error When "" is read: No error When "" is written: Reset to "" When "" is written: Invalid OER is an error flag that indicates the generation of an overrun error and becomes "" when an error has been generated. An overrun error is generated when the receiving of data has been completed prior to the writing of "" to RXTRG in the asynchronous mode. OER is reset to "" by writing "". At initial reset and when RXEN is "", OER is set to "" (no error). PER: FF49H Indicates the generation of a parity error. When "" is read: Error When "" is read: No error When "" is written: Reset to "" When "" is written: Invalid PER is an error flag that indicates the generation of a parity error and becomes "" when an error has been generated. When a parity check is performed in the asynchronous mode, if data that does not match the parity is received, a parity error is generated. PER is reset to "" by writing "". At initial reset and when RXEN is "", PER is set to "" (no error). 78 EPSON SC8865 TECHNICAL MANUAL

87 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) FER: FF49H Indicates the generation of a framing error. When "" is read: Error When "" is read: No error When "" is written: Reset to "" When "" is written: Invalid FER is an error flag that indicates the generation of a framing error and becomes "" when an error has been generated. When the stop bit for the receiving of the asynchronous mode has become "", a framing error is generated. FER is reset to "" by writing "". At initial reset and when RXEN is "", FER is set to "" (no error). PSIF, PSIF: FF2H D4, Sets the priority level of the serial interface interrupt. The two bits PSIF and PSIF are the interrupt priority register corresponding to the serial interface interrupt. Table shows the interrupt priority level which can be set by this register. Table Interrupt priority level settings PSIF PSIF Interrupt priority level Level 3 (IRQ3) Level 2 (IRQ2) Level (IRQ) Level (None) At initial reset, this register is set to "" (level ). ESTRA, ESREC, ESERR: FF23H, D, Enables or disables the generation of an interrupt for the CPU. When "" is written: Interrupt enabled When "" is written: Interrupt disabled Reading: Valid ESTRA, ESREC and ESERR are interrupt enable registers that respectively correspond to the interrupt factors for transmitting complete, receiving complete and receiving error. Interrupts set to "" are enabled and interrupts set to "" are disabled. At initial reset, this register is set to "" (interrupt disabled). FSTRA, FSREC, FSERR: FF27H, D, Indicates the serial interface interrupt generation status. When "" is read: Interrupt factor present When "" is read: Interrupt factor not present When "" is written: Resets factor flag When "" is written: Invalid FSTRA, FSREC and FSERR are interrupt factor flags that respectively correspond to the interrupts for transmitting complete, receiving complete and receiving error and are set to "" by generation of each factor. Transmitting complete interrupt factor is generated at the point where the data transmitting of the shift register has been completed. Receiving complete interrupt factor is generated at the point where the received data has been transferred into the received data buffer. Receive error interrupt factor is generated when a parity error, framing error or overrun error has been detected during data receiving. When set in this manner, if the corresponding interrupt enable register is set to "" and the corresponding interrupt priority register is set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag will be set to "" by the occurrence of an interrupt generation condition. To accept the subsequent interrupt after interrupt generation, re-setting of the interrupt flags (set interrupt flag to lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and interrupt factor flag reset are necessary. The interrupt factor flag is reset to "" by writing "". At initial reset, this flag is reset to "". SC8865 TECHNICAL MANUAL EPSON 79

88 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) 5.8. Programming notes () Be sure to initialize the serial interface mode in the transmitting/receiving disable status (TXEN = RXEN = ""). (2) Do not perform double trigger (writing "") to TXTRG (RXTRG) when the serial interface is in the transmitting (receiving) operation. Furthermore, do not execute the SLP instruction. (When executing the SLP instruction, set TXEN = RXEN = "".) (3) In the clock synchronous mode, since one clock line (SCLK) is shared for both transmitting and receiving, transmitting and receiving cannot be performed simultaneously. (Half duplex only is possible in clock synchronous mode.) Consequently, be sure not to write "" to RXTRG (TXTRG) when TXTRG (RXTRG) is "". (4) When a parity error or flaming error is generated during receiving in the asynchronous mode, the receiving error interrupt factor flag FSERR is set to "" prior to the receiving complete interrupt factor flag FSREC for the time indicated in Table Consequently, when an error is generated, you should reset the receiving complete interrupt factor flag FSREC to "" by providing a wait time in error processing routines and similar routines. When an overrun error is generated, the receiving complete interrupt factor flag FSREC is not set to "" and a receiving complete interrupt is not generated. Table Time difference between FSERR and FSREC on error generation Clock source Time difference fosc3 / n /2 cycles of fosc3 / n Programmable timer cycle of timer underflow (5) When the demultiplied signal of the OSC3 oscillation circuit is made the clock source, it is necessary to turn the OSC3 oscillation ON, prior to using the serial interface. A time interval of several msec to several msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes, is necessary, due to the oscillation element that is used. Consequently, you should allow an adequate waiting time after turning ON of the OSC3 oscillation, before starting transmitting/receiving of serial interface. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 8, "ELECTRICAL CHARACTERISTICS".) At initial reset, the OSC3 oscillation circuit is set to ON status. 8 EPSON SC8865 TECHNICAL MANUAL

89 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Clock Timer) 5.9 Clock Timer 5.9. Configuration of clock timer The SC8865 has built in a clock timer that uses the OSC oscillation circuit as clock source. The clock timer is composed of an 8-bit binary counter that uses the 256 Hz signal dividing fosc as its input clock and can read the data of each bit (28 Hz) by software. Normally, this clock timer is used for various timing functions such as clocks. The configuration of the clock timer is shown in Figure Interrupt function The clock timer can generate an interrupt by each of the 32 Hz, 8 Hz, 2 Hz and Hz signals. The configuration of the clock timer interrupt circuit is shown in Figure Interrupts are generated by respectively setting the corresponding interrupt factor flags FTM32, FTM8, FTM2 and FTM at the falling edge of the 32 Hz, 8 Hz, 2 Hz and Hz signals to "". Interrupt can be prohibited by the setting the interrupt enable registers ETM32, ETM8, ETM2 and ETM corresponding to each interrupt factor flag. In addition, a priority level of the clock timer interrupt for the CPU can be optionally set at levels to 3 by the interrupt priority registers PTM and PTM. For details on the above mentioned interrupt control register and the operation following generation of an interrupt, see "5.4 Interrupt and Standby Status". The exception processing vector addresses for each interrupt factor are respectively set as shown below. 32 Hz interrupt: 34H 8 Hz interrupt: 36H 2 Hz interrupt: 38H Hz interrupt: 3AH Figure shows the timing chart for the clock timer. Data bus OSC oscillation circuit fosc Divider 256 Hz Clock timer 28 Hz 64 Hz 32 Hz 6 Hz 8 Hz TMTMD7 4 Hz 2 Hz Hz TMRST TMRUN Clock timer reset Clock timer Run/Stop Interrupt control circuit Interrupt request Fig Configuration of clock timer SC8865 TECHNICAL MANUAL EPSON 8

90 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Clock Timer) Address Interrupt priority register PTM, PTM 32 Hz falling edge Address Interrupt factor flag FTM32 Address Interrupt enable register ETM32 8 Hz falling edge Address Interrupt factor flag FTM8 Data bus Address 2 Hz falling edge Address Interrupt enable register ETM8 Interrupt factor flag FTM2 Interrupt priority level judgement circuit Interrupt request Address Interrupt enable register ETM2 Hz falling edge Address Interrupt factor flag FTM Address Interrupt enable register ETM Fig Configuration of clock timer interrupt circuit OSC/ Hz TM 28 Hz TMD 64 Hz TM 32 Hz TMD3 6 Hz TMD4 8 Hz TM 4 Hz TM 2 Hz TMD7 Hz 32 Hz interrupt 8 Hz interrupt 2 Hz interrupt Hz interrupt Fig Timing chart of clock timer 82 EPSON SC8865 TECHNICAL MANUAL

91 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Clock Timer) Control of clock timer Table shows the clock timer control bits. Table Clock timer control bits Address Bit Name Function SR FF4 D7 WDEN FOUT2 Watchdog timer enable FOUT frequency selection Enable Disable FOUT D4 FOUT FOUT2 FOUT FOUT D3 FOUTON FOUT output control D WDRST TMRST TMRUN Watchdog timer reset Clock timer reset Clock timer Run/Stop control FF4 D7 TMD7 TM TM D4 TMD4 D3 TMD3 TM D TMD TM FF2 D7 PK PK PSIF D4 PSIF D3 D PTM PTM FF22 D7 D4 D3 ETM32 ETM8 D ETM2 ETM FF26 D7 D4 D3 FTM32 FTM8 D FTM2 FTM Frequency fosc / fosc / 2 fosc / 4 fosc / 8 fosc3 / fosc3 / 2 fosc3 / 4 fosc3 / 8 Clock timer data Hz Clock timer data 2 Hz Clock timer data 4 Hz Clock timer data 8 Hz Clock timer data 6 Hz Clock timer data 32 Hz Clock timer data 64 Hz Clock timer data 28 Hz KK7 interrupt priority register Serial interface interrupt priority register Clock timer interrupt priority register Clock timer 32 Hz interrupt enable register Clock timer 8 Hz interrupt enable register Clock timer 2 Hz interrupt enable register Clock timer Hz interrupt enable register Clock timer 32 Hz interrupt factor flag Clock timer 8 Hz interrupt factor flag Clock timer 2 Hz interrupt factor flag Clock timer Hz interrupt factor flag On Reset Reset Run High PK PSIF PTM Interrupt enable PK PSIF PTM (R) Generated (W) Reset Off No operation No operation Stop Low Priority level Level 3 Level 2 Level Level Priority level Level 3 Level 2 Level Level Interrupt disable (R) Not generated (W) No operation W W R Comment Constantly "" when being read Constantly "" when being read Constantly "" when being read Constantly "" when being read SC8865 TECHNICAL MANUAL EPSON 83

92 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Clock Timer) TMTMD7: FF4H The clock timer data can be read out. Each bit of TMTMD7 and frequency correspondence are as follows: TM: 28 Hz TMD4: 8 Hz TMD: 64 Hz TM: 4 Hz TM: 32 Hz TM: 2 Hz TMD3: 6 Hz TMD7: Hz Since the TMTMD7 is exclusively for reading, the write operation is invalid. At initial reset, the timer data is set to "H". TMRST: FF4H D Resets the clock timer. When "" is written: Clock timer reset When "" is written: No operation Reading: Always "" The clock timer is reset by writing "" to the TMRST. When the clock timer is reset in the RUN status, it restarts immediately after resetting. In the case of the STOP status, the reset data "H" is maintained. No operation results when "" is written to the TMRST. Since the TMRST is exclusively for writing, it always becomes "" during reading. TMRUN: FF4H Controls RUN/STOP of the clock timer. When "" is written: RUN When "" is written: STOP Reading: Valid The clock timer starts up-counting by writing "" to the TMRUN and stops by writing "". In the STOP status, the count data is maintained until it is reset or set in the next RUN status. Also, when the STOP status changes to the RUN status, the data that was maintained can be used for resuming the count. At initial reset, the TMRUN is set to "" (STOP). PTM, PTM: FF2H, D Sets the priority level of the clock timer interrupt. The two bits PTM and PTM are the interrupt priority register corresponding to the clock timer interrupt. Table shows the interrupt priority level which can be set by this register. Table Interrupt priority level settings PTM PTM Interrupt priority level Level 3 (IRQ3) Level 2 (IRQ2) Level (IRQ) Level (None) At initial reset, this register is set to "" (level ). ETM, ETM2, ETM8, ETM32: FF22H D3 Enables or disables the generation of an interrupt for the CPU. When "" is written: Interrupt enabled When "" is written: Interrupt disabled Reading: Valid The ETM, ETM2, ETM8 and ETM32 are interrupt enable registers that respectively correspond to the interrupt factors for Hz, 2 Hz, 8 Hz and 32 Hz. Interrupts set to "" are enabled and interrupts set to "" are disabled. At initial reset, this register is set to "" (interrupt disabled). FTM, FTM2, FTM8, FTM32: FF26H D3 Indicates the clock timer interrupt generation status. When "" is read: When "" is read: Interrupt factor present Interrupt factor not present When "" is written: Resets factor flag When "" is written: Invalid The FTM, FTM2, FTM8 and FTM32 are interrupt factor flags that respectively correspond to the interrupts for Hz, 2 Hz, 8 Hz and 32 Hz and are set to "" at the falling edge of each signal. When set in this manner, if the corresponding interrupt enable register is set to "" and the corresponding interrupt priority register is set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag will be set to "" by the occurrence of an interrupt generation condition. To accept the subsequent interrupt after interrupt generation, re-setting of the interrupt flags (set interrupt flag to lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and interrupt factor flag reset are necessary. The interrupt factor flag is reset to "" by writing "". At initial reset, this flag is reset to "". 84 EPSON SC8865 TECHNICAL MANUAL

93 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Clock Timer) Programming notes () The clock timer is actually made to RUN/STOP in synchronization with the falling edge of the 256 Hz signal after writing to the TMRUN register. Consequently, when "" is written to the TMRUN, the timer shifts to STOP status when the counter is incremented "". The TMRUN maintains "" for reading until the timer actually shifts to STOP status. Figure shows the timing chart of the RUN/STOP control. 256 Hz TMRUN(RD) TMRUN(WR) TMDX 57H 58H 59H 5AH 5BH 5CH Fig Timing chart of RUN/STOP control (2) The SLP instruction is executed when the clock timer is in the RUN status (TMRUN = ""). The clock timer operation will become unstable when returning from SLEEP status. Therefore, when shifting to SLEEP status, set the clock timer to STOP status (TMRUN = "") prior to executing the SLP instruction. SC8865 TECHNICAL MANUAL EPSON 85

94 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) 5. Programmable Timer 5.. Configuration of programmable timer The SC8865 has four built-in 6-bit programmable timer systems. Each system timer consists of a 6-bit presettable down counter, and can be used as 6-bit channel or 8-bit 2 channels of programmable timer. Furthermore, they function as event counters using the input port terminal. Figures 5... and shows the configuration of the 6-bit programmable timers. Two 8-bit down counters, the reload data register and compare data register corresponding to each down counter are arranged in the 6-bit programmable timer. The reload data register is used to set an initial value to the down counter. The compare data register stores data for comparison with the content of the down counter. By setting these registers, a PWM waveform is generated and it can be output to external devices as the TOUT,, 2 or 3 signal. Furthermore, the serial interface clock is generated from the Timer underflow signal. The Timer 5 underflow signal can be used to set the frame frequency for the LCD driver. fosc3/fosc Input port (K4) Prescaler/clock control circuit INCL EXCL Clock selection circuit Timer 8-bit reload data register (RDR) 8-bit down counter (PTM) Clock output Underflow interrupt Compare match interrupt Clock output circuit Interrupt circuit TOUT Control circuit Underflow signal Underflow Compare match Comparator 8-bit compare data register (CDR) Timer control registers fosc3/fosc Input port (K4) Prescaler/clock control circuit INCL EXCL Clock selection circuit Timer 8-bit reload data register (RDR) Clock output To serial I/F Underflow interrupt Compare match interrupt fosc3/fosc Input port (K5) Clock output circuit Interrupt circuit Prescaler/clock control circuit TOUT INCL2 EXCL Control circuit Clock selection circuit Underflow Compare match 8-bit down counter (PTM) Comparator 8-bit compare data register (CDR) Timer control registers Timer 2 8-bit reload data register (RDR2) Data bus Clock output Underflow interrupt Compare match interrupt Clock output circuit Interrupt circuit TOUT2 TOUT2 Control circuit Underflow signal Underflow Compare match 8-bit down counter (PTM2) Comparator 8-bit compare data register (CDR2) Timer 2 control registers fosc3/fosc Input port (K5) Prescaler/clock control circuit INCL3 EXCL Clock selection circuit Timer 3 8-bit reload data register (RDR3) Clock output Underflow interrupt Compare match interrupt Clock output circuit Interrupt circuit TOUT3 TOUT3 Control circuit Underflow Compare match 8-bit down counter (PTM3) Comparator 8-bit compare data register (CDR3) Timer 3 control registers Fig Configuration of 6-bit programmable timer (Timers 3) 86 EPSON SC8865 TECHNICAL MANUAL

95 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) fosc3/fosc Input port (K6) Prescaler/clock control circuit INCL4 EXCL2 Clock selection circuit Timer 4 8-bit reload data register (RDR4) 8-bit down counter (PTM4) Underflow interrupt Compare match interrupt Interrupt circuit Control circuit Underflow Compare match Comparator 8-bit compare data register (CDR4) Underflow signal Timer 4 control registers fosc3/fosc Input port (K6) Prescaler/clock control circuit INCL5 EXCL2 Clock selection circuit Timer 5 8-bit reload data register (RDR5) To LCD driver Underflow interrupt Compare match interrupt Interrupt circuit Control circuit Underflow Compare match 8-bit down counter (PTM5) Comparator 8-bit compare data register (CDR5) fosc3/fosc Input port (K7) Prescaler/clock control circuit INCL6 EXCL3 Clock selection circuit Timer 5 control registers Timer 6 8-bit reload data register (RDR6) Data bus 8-bit down counter (PTM6) Underflow interrupt Compare match interrupt Interrupt circuit Control circuit Underflow Compare match Comparator 8-bit compare data register (CDR6) Underflow signal Timer 6 control registers fosc3/fosc Input port (K7) Prescaler/clock control circuit INCL7 EXCL3 Clock selection circuit Timer 7 8-bit reload data register (RDR7) 8-bit down counter (PTM7) Underflow interrupt Compare match interrupt Interrupt circuit Control circuit Underflow Compare match Comparator 8-bit compare data register (CDR7) Timer 7 control registers Fig Configuration of 6-bit programmable timer (Timers 47) 5..2 Operation mode Timers and, Timers 2 and 3, Timers 4 and 5, or Timers 6 and 7 can be used as two channels of 8-bit timers or one channel of 6-bit timer. Two kinds of operation modes are provided corresponding to this configuration, and it can be selected by the 8/ 6-bit mode selection registers MODE6_A (for Timer ) through MODE6_D (for Timer 67). When "" is set to the MODE6_A register, Timers and enter the 8-bit mode (8-bit 2 channels) and when "" is set, they enter the 6-bit mode (6-bit channel). In the 8-bit mode, Timers and can be controlled individually. In the 6-bit mode, the underflow signal of Timer is used as the input clock of Timer so that the down counters operate as a 6-bit counter. The timer in the 6-bit mode is controlled with the control registers for Timer except for the clock output. MODE6_B through MODE6_D have the same function. Figure shows the timer configuration depending on the operation mode and Table shows the configuration of the control registers. SC8865 TECHNICAL MANUAL EPSON 87

96 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) [8-bit mode] 8-bit data [6-bit mode] Low-order 8-bit data Timer input clock Timer Interrupt request TOUT output Timer input clock Timer Timer input clock Timer Interrupt request TOUT output Timer underflow signal Timer Interrupt request TOUT output 8-bit data High-order 8-bit data Fig Counter configuration in 8- and 6-bit mode (example of Timers and ) Table 5..2.(a) Control registers in 8-bit mode (example of Timers and ) Address Bit Name Function SR Comment FF3 D7 MODE6_A PTM 8/6-bit mode selection 6-bit x 8-bit x 2 PTNREN_A External clock noise rejecter selection Enable Disable D4 register D3 PTOUT PTM clock output control PTRUN PTM Run/Stop control On Run Off Stop D PSET PTM preset Preset No operation CKSEL PTM input clock selection External clock Internal clock FF3 D7 D4 register D3 PTOUT PTM clock output control PTRUN PTM Run/Stop control On Run Off Stop D PSET PTM preset Preset No operation CKSEL PTM input clock selection External clock Internal clock "" when being read Reserved register W "" when being read Constantly "" when being read Reserved register W "" when being read Table 5..2.(b) Control registers in 6-bit mode (example of Timers and ) Address Bit Name Function SR Comment FF3 D7 MODE6_A PTM 8/6-bit mode selection 6-bit x 8-bit x 2 PTNREN_A External clock noise rejecter selection Enable Disable D4 register D3 PTOUT Invalid (fixed at "") PTRUN PTM Run/Stop control Invalid Run Fixed at "" Stop D PSET PTM preset Preset No operation CKSEL PTM input clock selection External clock Internal clock FF3 D7 D4 register D3 PTOUT PTM clock output control PTRUN Invalid (fixed at "") On Invalid Off Fixed at "" D PSET CKSEL Invalid (fixed at "") Invalid (fixed at "") Invalid Invalid Fixed at "" Fixed at "" "" when being read Reserved register W "" when being read Constantly "" when being read Reserved register W "" when being read Note: The register names contain a timer number (7) to identify the timer to which the register belongs. The following explanation uses "x" instead of the timer number except when it is required. For example, PTRUNx represents PTRUN through PTRUN7. Furthermore, a pair of timers are described as Timer(L) and Timer(H) in explanations for 6-bit mode. Timer(L) = Timer, Timer 2, Timer 4 or Timer 6 Timer(H) = Timer, Timer 3, Timer 5 or Timer 7 This is used for register names. 88 EPSON SC8865 TECHNICAL MANUAL

97 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) 5..3 Setting of input clock The clock to be input to the counter can be selected from either the internal clock or external clock by the input clock selection register (CKSEL) provided for each timer. The internal clock is an output of the prescaler. The external clock is used for the event counter function. A signal from the input port is used as the count clock. Table shows the input clock selection register and input clock of each timer. Table Input clock selection Timer Timer Timer Timer 2 Timer 3 Timer 4 Timer 5 Timer 6 Timer 7 Register setting CKSEL = "" CKSEL = "" CKSEL = "" CKSEL = "" CKSEL2 = "" CKSEL2 = "" CKSEL3 = "" CKSEL3 = "" CKSEL4 = "" CKSEL4 = "" CKSEL5 = "" CKSEL5 = "" CKSEL6 = "" CKSEL6 = "" CKSEL7 = "" CKSEL7 = "" Input clock INCL (Prescaler) EXCL (K4 input) INCL (Prescaler) EXCL (K4 input) INCL2 (Prescaler) EXCL (K5 input) INCL3 (Prescaler) EXCL (K5 input) INCL4 (Prescaler) EXCL2 (K6 input) INCL5 (Prescaler) EXCL2 (K6 input) INCL6 (Prescaler) EXCL3 (K7 input) INCL7 (Prescaler) EXCL3 (K7 input) When the external clock is selected, a signal from the input port is input to the programmable timer. An noise rejecter is incorporated in the external clock input circuit and it can be enabled/disabled using the external clock noise rejecter select registers PTNREN_A through PTNREN_D corresponding to the EXCL through EXCL3 inputs. Writing "" to PTNREN_A (D) enables the noise rejecter for the external clock EXCL (3). The noise rejecter regards pulses less than a 6/fOSC seconds in width as noise and rejects them (an external clock must have a pulse width at least double the rejected width). When PTNREN_A (D) is "", the external clock bypasses the noise rejecter. When the internal clock is used, select a source clock and a division ratio of the prescaler to set the clock frequency for each timer. The source clock is specified using the source clock selection register PRTFx provided for each timer. When "" is written to PRTFx, the OSC clock is selected as the source clock for Timer x. When "" is written, the OSC3 clock is selected. The OSC3 oscillation circuit must be on before the OSC3 can be used. See "5.4 Oscillation Circuits" for the controlling of the OSC3 oscillation circuit. The prescaler provides the division ratio selection register PSTxPSTx2 for each timer. Note that the division ratio varies depending on the selected source clock. Table Division ratio and control registers Register Dividing ratio PSTx2 PSTx PSTx (OSC3) fosc3/496 fosc3/24 fosc3/256 fosc3/64 fosc3/32 fosc3/8 fosc3/2 fosc3/ (OSC) fosc/28 fosc/64 fosc/32 fosc/6 fosc/8 fosc/4 fosc/2 fosc/ The set clock is output to Timer x by writing "" to the clock control register PRPRTx. When the 6-bit mode is selected, the programmable timer operates with the clock input to Timer(L), and Timer(H) inputs the Timer(L) underflow signal as the clock. Therefore, the setting of Timer(H) input clock is invalid Operation and control of timer Reload data register and setting of initial value The reload data register (RDRx) is used to set an initial value of the down counter. In the 8-bit mode, RDRx is used as an 8-bit register separated for each timer. In the 6-bit mode, the RDR(L) register is handled as low-order 8 bits of reload data, and the RDR(H) register is as high-order 8 bits. The reload data register can be read and written, and all the registers are set to FFH at initial reset. Data written in this register is loaded into the down counter, and a down counting starts from the value. The down counter is preset, in the following two cases: ) When software presets The software preset can be done using the preset control bits PSETx corresponding to Timer x. When the preset control bit is set to "", the content of the reload data register is loaded into the down counter at that point. In the 6-bit mode, a 6-bit reload data is loaded all at one time by setting PSET(L). In this case, writing to PSET(H) is invalid. 2) When down counter has underflowed during a count Since the down counter presets the reload data by the underflow, the underflow period is decided according to the value set in the reload data register. This underflow generates an interrupt, and controls the clock (TOUTx signal) output. SC8865 TECHNICAL MANUAL EPSON 89

98 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) Compare data register The programmable timer has a built-in data comparator so that count data can be compared with an optional value. The compare data register (CDRx) is used to set the value to be compared. In the 8-bit mode, CDRx is used as an 8-bit register separated for each timer. In the 6-bit mode, the CDR(L) register is handled as low-order 8 bits of compare data, and the CDR(H) register is as high-order 8 bits. The compare data register can be read and written, and all the registers are set to H at initial reset. The programmable timer compares count data with the compare data register (CDRx), and generates a compare match signal when they become the same value. This compare match signal generates an interrupt, and controls the clock (TOUTx signal) output. Timer operation Timer is equipped with PTRUNx register which controls the RUN/STOP of the timer. Timer x starts down counting by writing "" to the PTRUNx register. However, it is necessary to control the input clock and to preset the reload data before starting a count. When "" is written to PTRUNx register, clock input is prohibited, and the count stops. This RUN/STOP control does not affect data in the counter. The data in the counter is maintained during count deactivation, so it is possible to resume counting from the data. In the 8-bit mode, the timers can be controlled individually by the PTRUNx register. In the 6-bit mode, the PTRUN(L) register controls a pair of timers as a 6-bit timer. In this case, control of the PTRUN(H) register is invalid. The buffers PTMx is attached to the counter, and reading is possible in optional timing. When the counter agrees with the data set in the compare data register during down counting, the timer generates a compare match interrupt. And, when the counter underflows, an underflow interrupt is generated, and the initial value set in the reload data register is loaded to the counter. The interrupt generated does not stop the down counting. After an underflow interrupt is generated, the counter continues counting from the initial value reloaded. PTRUNx PSETx RDRx CDRx Input clock PTMx7 PTMx6 PTMx5 PTMx4 PTMx3 PTMx2 PTMx PTMx Note: Preset A6H 58H A6H 58H Compare match interrupt generation Fig Basic operation timing of counter (an example of 8-bit mode) F3H 58H Reload Underflow interrupt generation The programmable timer counts down at the falling edge of the input clock and at the same time it generates an interrupt if the counter underflows. Then it starts loading the reload data to the counter and the counter data is determined at the next rising edge of the input clock (period shown in as in the figure). To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter data is determined including the reloading period. Be especially careful when using the OSC (low-speed clock) as the clock source of the programmable timer and the CPU is operating with the OSC3 (high-speed clock). 9 EPSON SC8865 TECHNICAL MANUAL

99 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) 5..5 Interrupt function The 6-bit programmable timer can generate an interrupt with the compare match signal and underflow signal of each timer. Figure shows the configuration of the 6- bit programmable timer interrupt circuit. The compare match signal and underflow signal of each timer set the corresponding interrupt factor flag to "". At that point, the interrupt is generated. The interrupt can also be prohibited by setting the interrupt enable register to correspond with the interrupt factor flag. Furthermore, the priority level of the interrupt for the CPU can be set to an optional level (3) using the interrupt priority register. Table shows the interrupt factor flags, interrupt enable registers and interrupt priority registers corresponding to the interrupt factors. In the 8-bit mode, the compare match interrupt factor flag and underflow interrupt factor flag are individually set to "" by the timers. In the 6-bit mode, the interrupt factor flags of Timer(H) are set to "" by the compare match and underflow in 6 bits. Refer to Section 5.4, "Interrupt and Standby Status", for details of the interrupt control registers and operations subsequent to interrupt generation. The exception processing vector addresses for the 6- bit programmable timer interrupt are set as follows: Timer underflow interrupt: 6H Timer compare match interrupt: 8H Timer underflow interrupt: AH Timer compare match interrupt: CH Timer 2 underflow interrupt: EH Timer 2 compare match interrupt: 2H Timer 3 underflow interrupt: 22H Timer 3 compare match interrupt: 24H Timer 4 underflow interrupt: 3CH Timer 4 compare match interrupt: 3EH Timer 5 underflow interrupt: 4H Timer 5 compare match interrupt: 42H Timer 6 underflow interrupt: 44H Timer 6 compare match interrupt: 46H Timer 7 underflow interrupt: 48H Timer 7 compare match interrupt: 4AH Timer Timer Timer 2 Timer 3 Timer 4 Timer 5 Timer 6 Timer 7 Interrupt factor Counter underflow Compare match Counter underflow Compare match Counter underflow Compare match Counter underflow Compare match Counter underflow Compare match Counter underflow Compare match Counter underflow Compare match Counter underflow Compare match Table Interrupt control registers Interrupt factor flag Interrupt enable register Interrupt priority register Name FTU FTC FTU FTC FTU2 FTC2 FTU3 FTC3 FTU4 FTC4 FTU5 FTC5 FTU6 FTC6 FTU7 FTC7 Address Dx FF29H FF29H D FF29H FF29H D3 FF29H D4 FF29H FF29H FF29H D7 FF2EH FF2EH D FF2EH FF2EH D3 FF2EH D4 FF2EH FF2EH FF2EH D7 Name ETU ETC ETU ETC ETU2 ETC2 ETU3 ETC3 ETU4 ETC4 ETU5 ETC5 ETU6 ETC6 ETU7 ETC7 Address Dx FF25H FF25H D FF25H FF25H D3 FF25H D4 FF25H FF25H FF25H D7 FF2CH FF2CH D FF2CH FF2CH D3 FF2CH D4 FF2CH FF2CH FF2CH D7 Name PPT PPT PPT2 PPT3 PPT4 PPT5 PPT6 PPT7 Address Dx FF2H FF2H D3 FF2H D4 FF2H FF2AH FF2AH D FF2AH FF2AH D3 SC8865 TECHNICAL MANUAL EPSON 9

100 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) Address Underflow Address Interrupt priority register PPT, PPT Interrupt factor flag FTU Address Compare match Address Address Interrupt enable register ETU Interrupt factor flag FTC Interrupt enable register ETC Interrupt priority level judgment circuit Timer Timer Timer interrupt request Timer interrupt request Address Underflow Address Interrupt priority register PPT2, PPT3 Interrupt factor flag FTU2 Data bus Address Compare match Address Address Address Underflow Address Interrupt enable register ETU2 Interrupt factor flag FTC2 Interrupt enable register ETC2 Interrupt priority register PPT4, PPT5 Interrupt factor flag FTU4 Interrupt priority level judgment circuit Timer 2 Timer 3 Timer 2 interrupt request Timer 3 interrupt request Address Compare match Address Address Interrupt enable register ETU4 Interrupt factor flag FTC4 Interrupt enable register ETC4 Interrupt priority level judgment circuit Timer 4 Timer 5 Timer 4 interrupt request Timer 5 interrupt request Address Underflow Address Address Compare match Address Address Interrupt priority register PPT6, PPT7 Interrupt factor flag FTU6 Interrupt enable register ETU6 Interrupt factor flag FTC6 Interrupt enable register ETC6 Interrupt priority level judgment circuit Timer 6 Timer 7 Fig Configuration of 6-bit programmable timer interrupt circuit Timer 6 interrupt request Timer 7 interrupt request 92 EPSON SC8865 TECHNICAL MANUAL

101 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) 5..6 Setting of TOUT output The 6-bit programmable timer can generate TOUT signals with the underflow and compare match signals of each timer. The TOUT signal generated in the 6-bit programmable timer can be output from the I/O port terminal shown in Table so that a clock is supplied for external devices or it can be used as a PWM waveform output. Table TOUT output terminal Timer Timer Timer Timer 2 Timer 3 Output clock name TOUT TOUT TOUT2 TOUT2 TOUT3 TOUT3 Output terminal P4 P4 P5 P7 P5 P7 The TOUT signal rises at the falling edge of the underflow signal and falls at the falling edge of the compare match signal. TOUT is the inverted TOUT signal. Therefore, it is possible to change the frequency and duty ratio of the TOUT signal by setting the reload data register (RDR) and compare data register (CDR). However, it needs a condition setting: RDR > CDR, CDR. In the case of RDR CDR, TOUT signal is fixed at "". The TOUT output can be controlled ON and OFF using the clock output control register PTOUTx of each timer and the TOUT output can be controlled using the inverted clock output control register RPTOUTx of Timer 2 or Timer 3. When PTOUTx (RPTOUTx) is set to "", the TOUTx (TOUTx) signal is output from the corresponding port terminal, when "" is set, the port is set for DC output. When PTOUTx (RPTOUTx) is "", settings of the I/O control register IOC4/IOC5/IOC7 and data register P4D/P5D/P7D become invalid. Note: If PTOUT and PTOUT are set to "" at the same time, PTOUT is effective. Similarly, if PTOUT2 (RPTOUT2) and PTOUT3 (RPTOUT3) are set to "", PTOUT3 (RPTOUT3) is effective. In the 6-bit mode, the output is controlled by the control register PTOUT(H) for Timer(H). The clock is output from Timer(H). Since the TOUTx (TOUTx) signal is generated asynchronously from the register PTOUTx (RPTOUTx), when the signal is turned ON or OFF by the register settings, a hazard of a /2 cycle or less is generated. Figure shows the output waveform of TOUT signal. Input clock RDRx register CDRx register Down counter Compare match signal Underflow signal TOUTx signal CDR register value RDR register value + PTOUTx/RPTOUTx Output from TOUTx (P4/P5) terminal Output from TOUTx (P7) terminal Fig Output waveform of TOUT signal SC8865 TECHNICAL MANUAL EPSON 93

102 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) 5..7 Transfer rate setting of serial interface The underflow signal of Timer can be used to clock the serial interface. The transfer rate setting in this case is made in the registers PSTX and RDRX (since only the underflow signal is used as the serial interface clock source, the CDRX register value does not affect the transfer rates. It can be set to any value). Transfer rate (bps) 9,2 9,6 4,8 2,4, Since the underflow signal of Timer is divided by 32 in the serial interface, the value set in the register RDRX which corresponds to the transfer rate is shown in the following expression: fdiv RDRX = - 32 bps fdiv: Input clock frequency (setteing of PSTX) bps: Transfer rate Table Example of transfer rate setting OSC3 oscillation frequency / Programmable timer settings fosc3 = MHz fosc3 = 3.72 MHz fosc3 = MHz PSTX RDRX PSTX RDRX PSTX RDRX H 3H H 4H H 5H H 7H H 9H H BH H FH H 3H H 7H H FH H 27H H 2FH H 3FH H 4FH H 5FH H 7FH H 9FH H BFH 2H FH 3H 9H H BFH 2H 3FH 3H 3H 2H 5FH Since the underflow signal only is used as the clock source, the CDRX register value does not affect the transfer rates Setting frame frequency for LCD driver The underflow signal of Timer 5 can be used as the source clock to generate the frame signal for the LCD driver. The frame frequency is set up using the registers PST5X and RDR5X (since only the underflow signal is used as the source clock, the CDR5X register value does not affect the frame signal. It can be set to any value). The Timer 5 underflow signal is divided by 28 (for /6 or /3 duty) or 256 (for /8 duty) in the LCD driver, so set a value represented by the following expressions to the register RDR5X. (for /6 or /32 duty) fdiv RDR5X = - 28 ffrm (for /8 duty) fdiv RDR5X = ffrm fdiv: Input clock frequency (setteing of PST5X) ffrm: Frame frequency (Hz) 94 EPSON SC8865 TECHNICAL MANUAL

103 5..9 Control of programmable timer 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) Table shows the programmable timer control bits. Table 5..9.(a) Programmable timer control bits Address Bit Name Function SR Comment FF4 D7 PRPRT Programmable timer clock control On Off PST2 Programmable timer division ratio PST2 PST PST (OSC3) (OSC) fosc3 / 496 fosc / 28 PST fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 D4 PST fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / D3 PRPRT Programmable timer clock control PST2 Programmable timer division ratio PST2 PST PST (OSC3) (OSC) fosc3 / 496 fosc / 28 D PST fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 PST fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / FF5 D7 PRPRT3 Programmable timer 3 clock control PST32 PST3 D4 PST3 Programmable timer 3 division ratio PST32 PST3 PST3 (OSC3) (OSC) fosc3 / 496 fosc / 28 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / D3 PRPRT2 Programmable timer 2 clock control PST22 Programmable timer 2 division ratio PST22 PST2 PST2 (OSC3) (OSC) fosc3 / 496 fosc / 28 D PST2 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 PST2 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / FF8 D7 PRPRT5 Programmable timer 5 clock control PST52 PST5 D4 PST5 Programmable timer 5 division ratio PST52 PST5 PST5 (OSC3) (OSC) fosc3 / 496 fosc / 28 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / D3 PRPRT4 Programmable timer 4 clock control PST42 Programmable timer 4 division ratio PST42 PST4 PST4 (OSC3) (OSC) fosc3 / 496 fosc / 28 D PST4 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 PST4 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / On On On On On Off Off Off Off Off SC8865 TECHNICAL MANUAL EPSON 95

104 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) Table 5..9.(b) Programmable timer control bits Address Bit Name Function SR Comment FF9 D7 PRPRT7 Programmable timer 7 clock control On Off PST72 Programmable timer 7 division ratio PST72 PST7 PST7 (OSC3) (OSC) fosc3 / 496 fosc / 28 PST7 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 D4 PST7 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / D3 PRPRT6 Programmable timer 6 clock control PST62 Programmable timer 6 division ratio PST62 PST6 PST6 (OSC3) (OSC) fosc3 / 496 fosc / 28 D PST6 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 PST6 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / FF7 D7 D4 register D3 PRTF3 Programmable timer 3 source clock selection PRTF2 Programmable timer 2 source clock selection D PRTF Programmable timer source clock selection PRTF Programmable timer source clock selection FFB D7 D4 D3 PRTF7 Programmable timer 7 source clock selection PRTF6 Programmable timer 6 source clock selection D PRTF5 Programmable timer 5 source clock selection PRTF4 Programmable timer 4 source clock selection FF2 D7 PPT3 Programmable timer 32 interrupt D4 PPT2 priority register D3 PPT Programmable timer interrupt PPT priority register D FF2A D7 D4 D3 PPT7 Programmable timer 76 interrupt PPT6 priority register D PPT5 Programmable timer 54 interrupt PPT4 priority register On fosc fosc fosc fosc fosc fosc fosc fosc PPT3 PPT PPT7 PPT5 PPT2 PPT PPT6 PPT4 Off fosc3 fosc3 fosc3 fosc3 fosc3 fosc3 fosc3 fosc3 Priority level Level 3 Level 2 Level Level Priority level Level 3 Level 2 Level Level Constantly "" when being read Reserved register Constantly "" when being read Constantly "" when being read Constantly "" when being read Constantly "" when being read 96 EPSON SC8865 TECHNICAL MANUAL

105 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) Table 5..9.(c) Programmable timer control bits Address Bit Name Function SR FF25 D7 D4 D3 D ETC3 ETU3 ETC2 ETU2 ETC ETU ETC ETU PTM3 compare match interrupt enable PTM3 underflow interrupt enable PTM2 compare match interrupt enable PTM2 underflow interrupt enable PTM compare match interrupt enable PTM underflow interrupt enable PTM compare match interrupt enable PTM underflow interrupt enable Interrupt enable Interrupt disable FF29 D7 D4 D3 D FTC3 FTU3 FTC2 FTU2 FTC FTU FTC FTU PTM3 compare match interrupt factor flag PTM3 underflow interrupt factor flag PTM2 compare match interrupt factor flag PTM2 underflow interrupt factor flag PTM compare match interrupt factor flag PTM underflow interrupt factor flag PTM compare match interrupt factor flag PTM underflow interrupt factor flag FF2C D7 ETC7 PTM7 compare match interrupt enable ETU7 PTM7 underflow interrupt enable ETC6 PTM6 compare match interrupt enable D4 ETU6 PTM6 underflow interrupt enable D3 ETC5 PTM5 compare match interrupt enable ETU5 PTM5 underflow interrupt enable D ETC4 PTM4 compare match interrupt enable ETU4 PTM4 underflow interrupt enable FF2E D7 FTC7 PTM7 compare match interrupt factor flag FTU7 PTM7 underflow interrupt factor flag FTC6 PTM6 compare match interrupt factor flag D4 FTU6 PTM6 underflow interrupt factor flag D3 FTC5 PTM5 compare match interrupt factor flag FTU5 PTM5 underflow interrupt factor flag D FTC4 PTM4 compare match interrupt factor flag FTU4 PTM4 underflow interrupt factor flag FF3 D7 MODE6_A PTM 8/6-bit mode selection PTNREN_A External clock noise rejecter selection D4 register D3 PTOUT PTM clock output control PTRUN PTM Run/Stop control D PSET PTM preset CKSEL PTM input clock selection FF3 D7 D4 register D3 PTOUT PTM clock output control PTRUN PTM Run/Stop control D PSET PTM preset CKSEL PTM input clock selection (R) Interrupt factor is generated (W) Reset Interrupt enable (R) Interrupt factor is generated (W) Reset 6-bit x Enable On Run Preset (R) No interrupt factor is generated (W) No operation Interrupt disable (R) No interrupt factor is generated (W) No operation 8-bit x 2 Disable Off Stop No operation External clock Internal clock On Off Run Stop Preset No operation External clock Internal clock W W Comment "" when being read Reserved register "" when being read Constantly "" when being read Reserved register "" when being read SC8865 TECHNICAL MANUAL EPSON 97

106 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) Table 5..9.(d) Programmable timer control bits Address Bit Name Function SR Comment FF32 D7 RDR7 RDR6 RDR5 PTM reload data D7 (MSB) PTM reload data PTM reload data D4 RDR4 PTM reload data D4 D3 RDR3 PTM reload data D3 High Low D RDR2 RDR RDR PTM reload data PTM reload data D PTM reload data (LSB) FF33 D7 RDR7 RDR6 RDR5 PTM reload data D7 (MSB) PTM reload data PTM reload data D4 RDR4 PTM reload data D4 D3 RDR3 PTM reload data D3 High Low D RDR2 RDR RDR PTM reload data PTM reload data D PTM reload data (LSB) FF34 D7 CDR7 CDR6 CDR5 PTM compare data D7 (MSB) PTM compare data PTM compare data D4 CDR4 PTM compare data D4 D3 CDR3 PTM compare data D3 High Low D CDR2 CDR CDR PTM compare data PTM compare data D PTM compare data (LSB) FF35 D7 CDR7 CDR6 CDR5 PTM compare data D7 (MSB) PTM compare data PTM compare data D4 CDR4 PTM compare data D4 D3 CDR3 PTM compare data D3 High Low D CDR2 CDR CDR PTM compare data PTM compare data D PTM compare data (LSB) FF36 D7 PTM7 PTM6 PTM5 PTM data D7 (MSB) PTM data PTM data D4 PTM4 PTM data D4 D3 PTM3 PTM data D3 High Low R D PTM2 PTM PTM PTM data PTM data D PTM data (LSB) FF37 D7 PTM7 PTM6 PTM5 PTM data D7 (MSB) PTM data PTM data D4 PTM4 PTM data D4 D3 PTM3 PTM data D3 High Low R D PTM2 PTM PTM PTM data PTM data D PTM data (LSB) 98 EPSON SC8865 TECHNICAL MANUAL

107 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) Table 5..9.(e) Programmable timer control bits Address Bit Name Function SR Comment FF38 D7 MODE6_B PTM23 8/6-bit mode selection 6-bit x 8-bit x 2 PTNREN_B External clock noise rejecter selection Enable Disable D4 D3 RPTOUT2 PTM2 inverted clock output control PTOUT2 PTM2 clock output control PTRUN2 PTM2 Run/Stop control On On Run Off Off Stop D PSET2 PTM2 preset Preset No operation CKSEL2 PTM2 input clock selection External clock Internal clock FF39 D7 D4 D3 RPTOUT3 PTM3 inverted clock output control PTOUT3 PTM3 clock output control PTRUN3 PTM3 Run/Stop control On On Run Off Off Stop D PSET3 PTM3 preset Preset No operation CKSEL3 PTM3 input clock selection External clock Internal clock FF3A D7 RDR27 RDR26 RDR25 PTM2 reload data D7 (MSB) PTM2 reload data PTM2 reload data D4 RDR24 PTM2 reload data D4 D3 RDR23 PTM2 reload data D3 High Low D RDR22 RDR2 RDR2 PTM2 reload data PTM2 reload data D PTM2 reload data (LSB) FF3B D7 RDR37 PTM3 reload data D7 (MSB) RDR36 PTM3 reload data RDR35 PTM3 reload data D4 RDR34 PTM3 reload data D4 D3 RDR33 PTM3 reload data D3 High Low RDR32 PTM3 reload data D RDR3 PTM3 reload data D RDR3 PTM3 reload data (LSB) FF3C D7 CDR27 PTM2 compare data D7 (MSB) CDR26 PTM2 compare data CDR25 PTM2 compare data D4 CDR24 PTM2 compare data D4 D3 CDR23 PTM2 compare data D3 High Low CDR22 PTM2 compare data D CDR2 PTM2 compare data D CDR2 PTM2 compare data (LSB) FF3D D7 CDR37 PTM3 compare data D7 (MSB) CDR36 PTM3 compare data CDR35 PTM3 compare data D4 CDR34 PTM3 compare data D4 D3 CDR33 PTM3 compare data D3 High Low CDR32 PTM3 compare data D CDR3 PTM3 compare data D CDR3 PTM3 compare data (LSB) "" when being read W "" when being read Constantly "" when being read W "" when being read SC8865 TECHNICAL MANUAL EPSON 99

108 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) Table 5..9.(f) Programmable timer control bits Address Bit Name Function SR Comment FF3E D7 PTM27 PTM26 PTM25 PTM2 data D7 (MSB) PTM2 data PTM2 data D4 PTM24 PTM2 data D4 D3 PTM23 PTM2 data D3 High Low R D PTM22 PTM2 PTM2 PTM2 data PTM2 data D PTM2 data (LSB) FF3F D7 PTM37 PTM36 PTM35 PTM3 data D7 (MSB) PTM3 data PTM3 data D4 PTM34 PTM3 data D4 D3 PTM33 PTM3 data D3 High Low R D PTM32 PTM3 PTM3 PTM3 data PTM3 data D PTM3 data (LSB) FFB D7 MODE6_C PTM45 8/6-bit mode selection PTNREN_C External clock 2 noise rejecter selection 6-bit x Enable 8-bit x 2 Disable D4 D3 register register PTRUN4 PTM4 Run/Stop control Run Stop D PSET4 PTM4 preset Preset No operation CKSEL4 PTM4 input clock selection External clock Internal clock FFB D7 D4 D3 register register PTRUN5 PTM5 Run/Stop control Run Stop D PSET5 PTM5 preset Preset No operation CKSEL5 PTM5 input clock selection External clock Internal clock FFB2 D7 RDR47 RDR46 RDR45 PTM4 reload data D7 (MSB) PTM4 reload data PTM4 reload data D4 RDR44 PTM4 reload data D4 D3 RDR43 PTM4 reload data D3 High Low D RDR42 RDR4 RDR4 PTM4 reload data PTM4 reload data D PTM4 reload data (LSB) FFB3 D7 RDR57 PTM5 reload data D7 (MSB) RDR56 PTM5 reload data RDR55 PTM5 reload data D4 RDR54 PTM5 reload data D4 D3 RDR53 PTM5 reload data D3 High Low RDR52 PTM5 reload data D RDR5 PTM5 reload data D RDR5 PTM5 reload data (LSB) W "" when being read Reserved register "" when being read Constantly "" when being read Reserved register W "" when being read EPSON SC8865 TECHNICAL MANUAL

109 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) Table 5..9.(g) Programmable timer control bits Address Bit Name Function SR Comment FFB4 D7 CDR47 CDR46 CDR45 PTM4 compare data D7 (MSB) PTM4 compare data PTM4 compare data D4 CDR44 PTM4 compare data D4 D3 CDR43 PTM4 compare data D3 High Low D CDR42 CDR4 CDR4 PTM4 compare data PTM4 compare data D PTM4 compare data (LSB) FFB5 D7 CDR57 CDR56 CDR55 PTM5 compare data D7 (MSB) PTM5 compare data PTM5 compare data D4 CDR54 PTM5 compare data D4 D3 CDR53 PTM5 compare data D3 High Low D CDR52 CDR5 CDR5 PTM5 compare data PTM5 compare data D PTM5 compare data (LSB) FFB6 D7 PTM47 PTM46 PTM45 PTM4 data D7 (MSB) PTM4 data PTM4 data D4 PTM44 PTM4 data D4 D3 PTM43 PTM4 data D3 High Low R D PTM42 PTM4 PTM4 PTM4 data PTM4 data D PTM4 data (LSB) FFB7 D7 PTM57 PTM56 PTM55 PTM5 data D7 (MSB) PTM5 data PTM5 data D4 PTM54 PTM5 data D4 D3 PTM53 PTM5 data D3 High Low R D PTM52 PTM5 PTM5 PTM5 data PTM5 data D PTM5 data (LSB) FFB8 D7 MODE6_D PTM67 8/6-bit mode selection PTNREN_D External clock 3 noise rejecter selection 6-bit x Enable 8-bit x 2 Disable D4 D3 register register PTRUN6 PTM6 Run/Stop control Run Stop D PSET6 PTM6 preset Preset No operation CKSEL6 PTM6 input clock selection External clock Internal clock FFB9 D7 D4 D3 register register PTRUN7 PTM7 Run/Stop control Run Stop D PSET7 PTM7 preset Preset No operation CKSEL7 PTM7 input clock selection External clock Internal clock W "" when being read Reserved register "" when being read Constantly "" when being read Reserved register W "" when being read SC8865 TECHNICAL MANUAL EPSON

110 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) Table 5..9.(h) Programmable timer control bits Address Bit Name Function SR Comment FFBA D7 RDR67 RDR66 RDR65 PTM6 reload data D7 (MSB) PTM6 reload data PTM6 reload data D4 RDR64 PTM6 reload data D4 D3 RDR63 PTM6 reload data D3 High Low D RDR62 RDR6 RDR6 PTM6 reload data PTM6 reload data D PTM6 reload data (LSB) FFBB D7 RDR77 RDR76 RDR75 PTM7 reload data D7 (MSB) PTM7 reload data PTM7 reload data D4 RDR74 PTM7 reload data D4 D3 RDR73 PTM7 reload data D3 High Low D RDR72 RDR7 RDR7 PTM7 reload data PTM7 reload data D PTM7 reload data (LSB) FFBC D7 CDR67 CDR66 CDR65 PTM6 compare data D7 (MSB) PTM6 compare data PTM6 compare data D4 CDR64 PTM6 compare data D4 D3 CDR63 PTM6 compare data D3 High Low D CDR62 CDR6 CDR6 PTM6 compare data PTM6 compare data D PTM6 compare data (LSB) FFBD D7 CDR77 CDR76 CDR75 PTM7 compare data D7 (MSB) PTM7 compare data PTM7 compare data D4 CDR74 PTM7 compare data D4 D3 CDR73 PTM7 compare data D3 High Low D CDR72 CDR7 CDR7 PTM7 compare data PTM7 compare data D PTM7 compare data (LSB) FFBE D7 PTM67 PTM66 PTM65 PTM6 data D7 (MSB) PTM6 data PTM6 data D4 PTM64 PTM6 data D4 D3 PTM63 PTM6 data D3 High Low R D PTM62 PTM6 PTM6 PTM6 data PTM6 data D PTM6 data (LSB) FFBF D7 PTM77 PTM76 PTM75 PTM7 data D7 (MSB) PTM7 data PTM7 data D4 PTM74 PTM7 data D4 D3 PTM73 PTM7 data D3 High Low R D PTM72 PTM7 PTM7 PTM7 data PTM7 data D PTM7 data (LSB) 2 EPSON SC8865 TECHNICAL MANUAL

111 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) MODE6_A: FF3H D7 MODE6_B: FF38H D7 MODE6_C: FFBH D7 MODE6_D: FFB8H D7 Selects either the 8/6 bit mode. When "" is written: 6 bits channel When "" is written: 8 bits 2 channels Reading: Valid MODE6_A, MODE6_B, MODE6_C and MODE6_D are the 8/6-bit mode selection registers corresponding to Timers and, Timers 2 and 3, Timers 4 and 5, and Timers 6 and 7, respectively. Select whether Timer(L) and Timer(H) are used as 2 channels independent 8-bit timers or as channel combined 6-bit timer. When "" is written to the MODE6_A (D) register, 8-bit 2 channels is selected and when "" is written, 6-bit channel is selected. At initial reset, this register is set to "" (8-bit 2 channels). PTNREN_A: FF3H PTNREN_B: FF38H PTNREN_C: FFBH PTNREN_D: FFB8H Enables/disables the noise rejecter in the external clock input circuit. When "" is written: Enabled When "" is written: Disabled Reading: Valid Writing "" to PTNREN_A (D) enables the noise rejecter for the external clock EXCL (3). The noise rejecter regards pulses less than a 6/fOSC seconds in width as noise and rejects them. When PTNREN_A (D) is "", the external clock bypasses the noise rejecter. At initial reset, this register is set to "" (disabled). CKSEL: FF3H CKSEL: FF3H CKSEL2: FF38H CKSEL3: FF39H CKSEL4: FFBH CKSEL5: FFBH CKSEL6: FFB8H CKSEL7: FFB9H Selects the input clock for each timer. When "" is written: External clock When "" is written: Internal clock Reading: Valid The clock to be input to each timer is selected from either the external clock (input signal of input port) or the internal clock (prescaler output clock). When "" is written to the CKSELx register, the internal clock (prescaler output INCLx) is selected as the input clock for Timer x. When "" is written, the external clock (EXCL (K4 input) for Timers and, EXCL (K5 input) for Timers 2 and 3, EXCL2 (K6 input) for Timers 4 and 5, EXCL3 (K7 input) for Timers 6 and 7) is selected and the timer functions as an event counter. In the 6-bit mode, the setting of the CKSEL(H) register is invalid. At initial reset, this register is set to "" (internal clock). PRTF: FF7H PRTF: FF7H D PRTF2: FF7H PRTF3: FF7H D3 PRTF4: FFBH PRTF5: FFBH D PRTF6: FFBH PRTF7: FFBH D3 Selects the source clock for each timer (when internal clock is used). When "" is written: fosc When "" is written: fosc3 Reading: Valid When "" is written to the PRTFx register, the OSC clock is selected as the source clock for Timer x. When "" is written, the OSC3 clock is selected. At initial reset, this register is set to "" (fosc3). PSTPST2: FF4H PSTPST2: FF4H D4 PST2PST22: FF5H PST3PST32: FF5H D4 PST4PST42: FF8H PST5PST52: FF8H D4 PST6PST62: FF9H PST7PST72: FF9H D4 Selects the input clock for each timer (when internal clock is used). It can be selected from 8 types of division ratio shown in Tables 5..9.(a) and (b). This register can also be read. At initial reset, this register is set to "". SC8865 TECHNICAL MANUAL EPSON 3

112 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) PRPRT: FF4H D3 PRPRT: FF4H D7 PRPRT2: FF5H D3 PRPRT3: FF5H D7 PRPRT4: FF8H D3 PRPRT5: FF8H D7 PRPRT6: FF9H D3 PRPRT7: FF9H D7 Controls the clock supply of each timer (when internal clock is used). When "" is written: ON When "" is written: OFF Reading: Valid By writing "" to the PRPRTx register, the clock that is selected with the PSTx register is output to Timer x. When "" is written, the clock is not output. At initial reset, the this register is set to "" (OFF). RDRRDR7: FF32H RDRRDR7: FF33H RDR2RDR27: FF3AH RDR3RDR37: FF3BH RDR4RDR47: FFB2H RDR5RDR57: FFB3H RDR6RDR67: FFBAH RDR7RDR77: FFBBH Sets the initial value for the counter of each timer. Each counter loads the reload data set in this register and counts using it as the initial value. The reload data set in this register is loaded into the counter when "" is written to PSETx, or when a counter underflow occurs. This register can also be read. At initial reset, this register is set to "FFH". CDRCDR7: FF34H CDRCDR7: FF35H CDR2CDR27: FF3CH CDR3CDR37: FF3DH CDR4CDR47: FFB4H CDR5CDR57: FFB5H CDR6CDR67: FFBCH CDR7CDR77: FFBDH Sets the compare data for each timer. The timer compares the data set in this register with the corresponding counter data, and outputs the compare match signals when they are the same. The compare match signal controls the interrupt and the TOUT output waveform. This register can also be read. At initial reset, this register is set to "H". PTMPTM7: FF36H PTMPTM7: FF37H PTM2PTM27: FF3EH PTM3PTM37: FF3FH PTM4PTM47: FFB6H PTM5PTM57: FFB7H PTM6PTM67: FFBEH PTM7PTM77: FFBFH The counter data of each timer can be read. Data can be read at any given time. However, in the 6-bit mode, reading PTM(L) does not latch the Timer(H) counter data in PTM(H). To avoid generating a borrow from Timer(L) to Timer(H), read the counter data after stopping the timer by writing "" to PTRUN(L). PTMx can only be read, so writing operation is invalid. At initial reset, PTMx is set to "FFH". PSET: FF3H D PSET: FF3H D PSET2: FF38H D PSET3: FF39H D PSET4: FFBH D PSET5: FFBH D PSET6: FFB8H D PSET7: FFB9H D Presets the reload data to the counter. When "" is written: Preset When "" is written: Invalid Reading: Always "" Writing "" to PSETx presets the reload data in the RDRx register to the counter of Timer x. When the counter of Timer x is in RUN status, the counter restarts immediately after presetting. In the case of STOP status, the counter maintains the preset data. No operation results when "" is written. In the 6-bit mode, writing "" to PSET(H) is invalid because 6-bit data is preset by PSET(L) only. PSETx is only for writing, and it is always "" during reading. 4 EPSON SC8865 TECHNICAL MANUAL

113 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) PTRUN: FF3H PTRUN: FF3H PTRUN2: FF38H PTRUN3: FF39H PTRUN4: FFBH PTRUN5: FFBH PTRUN6: FFB8H PTRUN7: FFB9H Controls the RUN/STOP of the counter. When "" is written: RUN When "" is written: STOP Reading: Valid The counter of Timer x starts down-counting by writing "" to the PTRUNx register and stops by writing "". In STOP status, the counter data is maintained until it is preset or the counter restarts. When STOP status changes to RUN status, the counter resumes counting from the data maintained. In the 6-bit mode, the timers are controlled with the PTRUN(L) register, and the PTRUN(H) register is fixed at "". At initial reset, this register is set to "" (STOP). PTOUT: FF3H D3 PTOUT: FF3H D3 PTOUT2: FF38H D3 PTOUT3: FF39H D3 Controls the output of the TOUT signal. When "" is written: TOUT signal output When "" is written: DC output Reading: Valid The PTOUTx is the output control register for the TOUTx signal (Timer x output clock). When PTOUT or PTOUT is set to "", the TOUT or TOUT signal is output from the P4 port terminal. When PTOUT2 or PTOUT3 is set to "", the TOUT2 or TOUT3 signal is output from the P5 port terminal. When "" is set, P4/P5 is set for DC output. At this time, settings of the I/O control register IOC4/IOC5 and data register P4D/P5D become invalid. In the 6-bit mode, the timers are controlled with the PTOUT(H) register, and the PTOUT(L) register is fixed at "". At initial reset, this register is set to "" (DC output). Note: If PTOUT and PTOUT are set to "" at the same time, PTOUT is effective. Similarly, if PTOUT2 and PTOUT3 are set to "", PTOUT3 is effective. Furthermore, if the programmable timer is set in 6-bit mode, the TOUT and TOUT2 signals cannot be output. RPTOUT2: FF38H D4 RPTOUT3: FF39H D4 Controls the output of the TOUT signal. When "" is written: TOUT signal output When "" is written: DC output Reading: Valid The RPTOUTx is the output control register for the TOUTx signal (Timer x inverted output clock). When RPTOUT2 or RPTOUT3 is set to "", the TOUT2 or TOUT3 signal is output from the P7 port terminal. When "" is set, P7 is set for DC output. At this time, settings of the I/O control register IOC7 and data register P7D become invalid. In the 6-bit mode, the timers are controlled with the RPTOUT3 register, and the RPTOUT2 register is fixed at "". At initial reset, this register is set to "" (DC output). Note: If RPTOUT2 and RPTOUT3 are set to "" at the same time, RPTOUT3 is effective. PPT, PPT: FF2H, D3 PPT2, PPT3: FF2H D4, PPT4, PPT5: FF2AH, D PPT6, PPT7: FF2AH, D3 Sets the priority level of the programmable timer interrupt. PPTPPT, PPT2PPT3, PPT4PPT5, and PPT6 PPT7 are the interrupt priority register corresponding to Timers, Timers 23, Timers 4 5, and Timers 67, respectively. Table shows the interrupt priority level which can be set by this register. Table Interrupt priority level settings PPT7 PPT5 PPT3 PPT PPT6 PPT4 PPT2 PPT Interrupt priority level Level 3 (IRQ3) Level 2 (IRQ2) Level (IRQ) Level (None) At initial reset, this register is set to "" (level ). SC8865 TECHNICAL MANUAL EPSON 5

114 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) ETU: FF25H ETU: FF25H ETU2: FF25H D4 ETU3: FF25H ETU4: FF2CH ETU5: FF2CH ETU6: FF2CH D4 ETU7: FF2CH Enables or disables the underflow interrupt generation to the CPU. When "" is written: Interrupt is enabled When "" is written: Interrupt is disabled Reading: Valid The ETUx register is the interrupt enable register corresponding to the underflow interrupt factor of Timer x. Interrupt in which the ETUx register is set to "" is enabled, and the others in which the ETUx register is set to "" are disabled. In the 6-bit mode, the setting of the ETU(L) is invalid. At initial reset, this register is set to "" (interrupt is disabled). ETC: FF25H D ETC: FF25H D3 ETC2: FF25H ETC3: FF25H D7 ETC4: FF2CH D ETC5: FF2CH D3 ETC6: FF2CH ETC7: FF2CH D7 Enables or disables the compare match interrupt generation to the CPU. When "" is written: Interrupt is enabled When "" is written: Interrupt is disabled Reading: Valid The ETCx register is the interrupt enable register corresponding to the compare match interrupt factor of Timer x. Interrupt in which the ETCx register is set to "" is enabled, and the others in which the ETCx register is set to "" are disabled. In the 6-bit mode, the setting of the ETC(L) is invalid. At initial reset, this register is set to "" (interrupt is disabled). FTU: FF29H FTU: FF29H FTU2: FF29H D4 FTU3: FF29H FTU4: FF2EH FTU5: FF2EH FTU6: FF2EH D4 FTU7: FF2EH Indicates the generation of underflow interrupt factor. When "" is read: Int. factor has generated When "" is read: Int. factor has not generated When "" is written: Factor flag is reset When "" is written: Invalid FTUx is the interrupt factor flag corresponding to interrupt of Timer x, and is set to "" due to the counter underflow. At this point, if the corresponding interrupt enable register is set to "" and the corresponding interrupt priority register is set to a higher level than the setting of the interrupt flags (I and I), an interrupt is generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag is set to "" when the interrupt generation condition is met. To accept the subsequent interrupt after an interrupt generation, it is necessary to re-set the interrupt flags (set the interrupt flag to a lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and to reset the interrupt factor flag. The interrupt factor flag is reset to "" by writing "". In the 6-bit mode, the interrupt factor flag FTU(L) is not set to "" and Timer(L) interrupt is not generated. In this mode, the interrupt factor flag FTU(H) is set to "" by the underflow of the 6-bit counter. At initial reset, this flag is reset to "". FTC: FF29H D FTC: FF29H D3 FTC2: FF29H FTC3: FF29H D7 FTC4: FF2EH D FTC5: FF2EH D3 FTC6: FF2EH FTC7: FF2EH D7 Indicates the generation of compare match interrupt factor. When "" is read: Int. factor has generated When "" is read: Int. factor has not generated When "" is written: Factor flag is reset When "" is written: Invalid 6 EPSON SC8865 TECHNICAL MANUAL

115 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) FTCx is the interrupt factor flag corresponding to interrupt of Timer x, and is set to "" with the compare match signal. At this point, if the corresponding interrupt enable register is set to "" and the corresponding interrupt priority register is set to a higher level than the setting of the interrupt flags (I and I), an interrupt is generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag is set to "" when the interrupt generation condition is met. To accept the subsequent interrupt after an interrupt generation, it is necessary to re-set the interrupt flags (set the interrupt flag to a lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and to reset the interrupt factor flag. The interrupt factor flag is reset to "" by writing "". In the 6-bit mode, the interrupt factor flag FTC(L) is not set to "" and Timer(L) interrupt is not generated. In this mode, the interrupt factor flag FTC(H) is set to "" by the compare match of the 6-bit counter. At initial reset, this flag is reset to "". 5.. Programming notes () The programmable timer actually enters into RUN or STOP status at the falling edge of the input clock after writing to the PTRUNx register. Consequently, when "" is written to PTRUNx, the timer stops after counting once more (+). PTRUNx is read as "" until the timer actually stops. Figure 5... shows the timing chart at the RUN/STOP control. (3) In the 6-bit mode, reading PTM(L) does not latch the Timer(H) counter data in PTM(H). To avoid generating a borrow from Timer(L) to Timer(H), read the counter data after stopping the timer by writing "" to PTRUN(L). (4) For the reason below, pay attention to the reload data write timing when changing the interval of the programmable timer interrupts while the programmable timer is running. The programmable timer counts down at the falling edge of the input clock and at the same time it generates an interrupt if the counter underflows. Then it starts loading the reload data to the counter and the counter data is determined at the next rising edge of the input clock (period shown in as ➀ in the figure). (Reload data = 25H) Input clock Counter data 3H 2H H H 25H 24H (continuous mode) Underflow (interrupt is generated) Counter data is determined by reloading Fig Reload timing for programmable timer To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter data is determined including the reloading period ➀. Be especially careful when using the OSC (low-speed clock) as the clock source of the programmable timer and the CPU is operating with the OSC3 (high-speed clock). ➀ Input clock PTRUNx(RD) PTRUNx(WR) PTMx 42H 4H 4H 3FH 3EH 3DH Fig Timing chart at RUN/STOP control (2) When the SLP instruction is executed while the programmable timer is running (PTRUNx = ""), the timer stops counting during SLEEP status. When SLEEP status is canceled, the timer starts counting. However, the operation becomes unstable immediately after SLEEP status is canceled. Therefore, when shifting to SLEEP status, stop the 6-bit programmable timer (PTRUNx = "") prior to executing the SLP instruction. Same as above, the TOUT signal output should be disabled (PTOUTx = "") so that an unstable clock is not output to the clock output port terminal. SC8865 TECHNICAL MANUAL EPSON 7

116 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver) 5. LCD Driver 5.. Configuration of LCD driver The SC8865 has a built-in dot matrix LCD driver that can drive an LCD panel with a maximum of 4,32 dots (26 segments 32 commons). Figure 5... shows the configuration of the LCD driver and the drive power supply LCD power supply The SC8865 generates the LCD drive voltages VC to VC5 using the internal power supply circuit. It is not necessary to apply an external voltage. Note that the internally generated voltage cannot be used for driving external loads. The LCD system voltage regulator can be driven with VDD or V depending on the power supply voltage level. Use the LCD system voltage regulator power select register VDSEL for this switching. When VDSEL is set to "", VDD is selected and when VDSEL is set to "", V is selected. The V voltage is generated by approximately doubling the VDD voltage in the power voltage booster circuit. When using V, write "" to the power voltage booster circuit ON/OFF control register DBON to turn the power voltage booster circuit on. This must be done before the power source of the LCD system voltage regulator can be switched to V. Programmable timer 5 underflow signal OSC oscillation fosc Divider circuit Clock control circuit FRMCS V CF CG Power voltage booster DBON VDSEL V VDD LCD contrast adjustment circuit LC3 LC2 LC LC VC VC2 VC3 VC4 VC5 CA CB CC CD CE LCD system voltage regulator VCVC5 LCD driver LCDC LCDC DTFNT LDUTY LDUTY SEGREV COMCOM3 SEGSEG25 VSS Display memory DSPAR Fig Configuration of LCD driver and drive power supply 8 EPSON SC8865 TECHNICAL MANUAL

117 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver) 5..3 Frame frequency This LCD driver allows selection of the source clock for generating the frame signal from the OSC oscillation clock (fosc) and the programmable timer 5 underflow signal. By using programmable timer 5, flexible frame frequencies can be programmed. Refer to Section 5..8, "Setting frame frequency for LCD driver". Use the LCD frame frequency source clock select register FRMCS to select the source clock. When FRMCS is set to "", fosc is selected, and when it is set to "", programmable timer 5 is selected. The following shows the frame frequencies when fosc is selected (fosc = khz). /8 duty: 64 Hz /6 duty: 32 Hz /32 duty: 32 Hz 5..4 Switching drive duty The SC8865 supports three types of LCD drive duty settings, /8, /6 and /32, and it can be switched using the LDUTY and LDUTY registers. Table shows the relationship of the LDUTY setting, drive duty and the maximum number of displaying dots. When /32 duty is selected, an LCD panel with 26 segments 32 commons (maximum 4,32 dots) can be driven. When /6 duty is selected, an LCD panel with 26 segments 6 commons (maximum 2,6 dots) can be driven. The COM6COM3 terminals become invalid, in that they always output an OFF signal. When /8 duty is selected, an LCD panel with 26 segments 8 commons (maximum,8 dots) can be driven. The COM8COM3 terminals become invalid, in that they always output an OFF signal. The drive bias is /5 (five potentials, VC, VC2, VC3, VC4 and VC5) regardless of the drive duty selected. The respective drive waveforms are shown in Figures to Table Correspondence between drive duty and maximum number of displaying dots LDUTY LDUTY Duty Not allowed /6 /32 /8 Common terminal COMCOM5 COMCOM3 COMCOM7 Segment terminal SEGSEG25 SEGSEG25 SEGSEG25 Maximum number of display dots 2,6 dots 4,32 dots,8 dots OSC oscillation circuit fosc /6 /64 (/32, /6 duty) Frame Divider Selector /28 (/8 duty) frequency Programmable timer 5 /2 underflow signal Fig Dividing the source clock to generate frame frequency SC8865 TECHNICAL MANUAL EPSON 9

118 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver) 32 Hz* COM SEG FR COM COM COM2 SEG SEG COMSEG VDD VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC V SS (GND) -VC -VC2 -VC3 -VC4 -VC5 COMSEG VC5 VC4 VC3 VC2 VC V SS (GND) -VC -VC2 -VC3 -VC4 -VC5 when fosc ( khz) is selected as the source clock (FRMCS = "") Fig Drive waveform for /32 duty EPSON SC8865 TECHNICAL MANUAL

119 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver) 32 Hz* COM SEG FR COM COM COM2 SEG VDD VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC VSS SEG VC5 VC4 VC3 VC2 VC VSS COMSEG VC5 VC4 VC3 VC2 VC V SS (GND) -VC -VC2 -VC3 -VC4 -VC5 COMSEG VC5 VC4 VC3 VC2 VC V SS (GND) -VC -VC2 -VC3 -VC4 -VC5 when fosc ( khz) is selected as the source clock (FRMCS = "") Fig Drive waveform for /6 duty SC8865 TECHNICAL MANUAL EPSON

120 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver) 64 Hz* COM SEG FR COM COM VDD VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC VSS COM2 VC5 VC4 VC3 VC2 VC VSS SEG VC5 VC4 VC3 VC2 VC VSS SEG VC5 VC4 VC3 VC2 VC VSS COMSEG VC5 VC4 VC3 VC2 VC V SS (GND) -VC -VC2 -VC3 -VC4 -VC5 COMSEG VC5 VC4 VC3 VC2 VC V SS (GND) -VC -VC2 -VC3 -VC4 -VC5 when fosc ( khz) is selected as the source clock (FRMCS = "") Fig Drive waveform for /8 duty 2 EPSON SC8865 TECHNICAL MANUAL

121 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver) 5..5 Display memory The SC8865 has a built-in 768-byte display memory. The display memory is allocated to address FxHFx7FH (x = 8DH) and the correspondence between the memory bits and common/segment terminal is changed according to the selection status of the following items. () Drive duty (/32, /6 or /8 duty) (2) Dot font (6 6/5 8 or 2 2 dots) (3) SEG terminal assignment (normal or reverse) When /6 or /8 duty is selected for the drive duty, two screen areas are reserved in the display memory and the area to be displayed can be selected by the display memory area select register DSPAR. When "" is written to DSPAR, display area is selected and when "" is written, display area is selected. Furthermore, memory allocation for 6 6/5 8 dots and 2 2 dots can be selected in order to easily display 2 2-dot font characters on the LCD panel. This selection can be done by the dot font selection register DTFNT: when "" is written to DTFNT, 6 6/5 8 dots is selected and when "" is written, 2 2 dots is selected. The memory allocation for the SEG terminals can be reversed using the SEG assignment reverse register SEGREV. Table Selecting SEG assignment SEGREV Assignment Reverse Normal FxH SEG25 SEG Fx7H SEG SEG25 The correspondence between the display memory bits set according to the drive duty and font size, and the common/segment terminals are shown in Figures When "" is written to the display memory bit corresponding to the dot on the LCD panel, the dot goes ON and when "" is written, it goes OFF. Since display memory is designed to permit reading/writing, it can be controlled in bit units by logical operation instructions and other means (read, modify and write instructions). The display area bits which have not been assigned within the 768-byte display memory can be used as general purpose RAM with read/write capabilities. Even when external memory has expanded into the display memory area, this area is not released to external memory. Access to this area is always via display memory. SC8865 TECHNICAL MANUAL EPSON 3

122 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver) Address / Data bit F F D F8H D3 D4 F87DH D7 D F9H D3 D4 F97DH D7 D FAH D3 D4 FA7DH D7 D FBH D3 D4 FB7DH D7 D FCH D3 D4 FC7DH D7 D FH D3 D4 FD7DH D7 SEG (normal) * 5 63 SEG (reverse) * F F Display area Display area Display area Display area F F F : SEGREV = "" 2: SEGREV = "" Fig Display memory map for /32 duty and 6 6/5 8-dot font 7 D COM EPSON SC8865 TECHNICAL MANUAL

123 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver) Address / Data bit D F8H D3 D4 F87DH D7 D F9H D3 D4 F97DH D7 D FAH D3 D4 FA7DH D7 D FBH D3 D4 FB7DH D7 D FCH D3 D4 FC7DH D7 D FH D3 D4 FD7DH D7 F SEG (normal) * 5 SEG (reverse) *2 252 F F F Display area Display area F Display area Display area F F : SEGREV = "" 2: SEGREV = "" Fig Display memory map for /32 duty and 2 2-dot font 7 D COM SC8865 TECHNICAL MANUAL EPSON 5

124 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver) Address / Data bit D F8H D3 D4 F87DH D7 D F9H D3 D4 F97DH D7 D FAH D3 D4 FA7DH D7 D FBH D3 D4 FB7DH D7 D FCH D3 D4 FC7DH D7 D FH D3 D4 FD7DH D7 F SEG (normal) * 5 SEG (reverse) *2 252 F F Display area (when DSPAR is set to "") Display area (when DSPAR is set to "") Display area (when DSPAR is set to "") Display area (when DSPAR is set to "") F F F F : SEGREV = "" 2: SEGREV = "" Fig Display memory map for /6 duty and 6 6/5 8-dot font 7 D COM EPSON SC8865 TECHNICAL MANUAL

125 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver) Address / Data bit D F8H D3 D4 F87DH D7 D F9H D3 D4 F97DH D7 D FAH D3 D4 FA7DH D7 D FBH D3 D4 FB7DH D7 D FCH D3 D4 FC7DH D7 D FH D3 D4 FD7DH D7 F SEG (normal) * 5 SEG (reverse) *2 252 F F Display area (when DSPAR is set to "") Display area (when DSPAR is set to "") F F F Display area (when DSPAR is set to "") Display area (when DSPAR is set to "") F : SEGREV = "" 2: SEGREV = "" Fig Display memory map for /6 duty and 2 2-dot font 7 D COM SC8865 TECHNICAL MANUAL EPSON 7

126 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver) Address / Data bit D F8H D3 D4 F87DH D7 D F9H D3 D4 F97DH D7 D FAH D3 D4 FA7DH D7 D FBH D3 D4 FB7DH D7 D FCH D3 D4 FC7DH D7 D FH D3 D4 FD7DH D7 F SEG (normal) * 5 SEG (reverse) *2 252 F F Display area (when DSPAR is set to "") Display area (when DSPAR is set to "") F F F F : SEGREV = "" 2: SEGREV = "" Fig Display memory map for /8 duty and 5 8-dot font 7 D COM EPSON SC8865 TECHNICAL MANUAL

127 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver) Address / Data bit D F8H D3 D4 F87DH D7 D F9H D3 D4 F97DH D7 D FAH D3 D4 FA7DH D7 D FBH D3 D4 FB7DH D7 D FCH D3 D4 FC7DH D7 D FH D3 D4 FD7DH D7 F SEG (normal) * 5 SEG (reverse) *2 252 F F Display area (when DSPAR is set to "") Display area (when DSPAR is set to "") F F F F : SEGREV = "" 2: SEGREV = "" Fig Display memory map for /8 duty and 2 2-dot font 7 D COM SC8865 TECHNICAL MANUAL EPSON 9

128 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver) 5..6 Display control The display status of the built-in LCD driver and the contrast adjustment can be controlled with the built-in LCD driver. The LCD display status can be selected by display control registers LCDC and LCDC. Setting the value and display status are shown in Table Table LCD display control LCDC LCDC LCD display All LCDs lit (Static) All LCDs out (Dynamic) Normal display Drive OFF All the dots in the LCD display can be turned on or off directly by the drive waveform output from the LCD driver, and data in the display memory is not changed. Also, since the common terminal at this time is set to static drive when all the dots are on and is set to dynamic drive when they are off, this function can be used as follows: () Since all dots on is binary output (VC5 and VSS) with static drive, the common/segment terminal can be used as a monitor terminal for the OSC oscillation frequency adjustment. (2) Since all dots off is dynamic drive, you can brink the entire LCD display without changing display memory data. Selecting LCD drive OFF turns the LCD drive power circuit OFF and all the VC to VC5 terminals go to VSS level. Furthermore, when the SLP instruction is executed, registers LCDC and LCDC are automatically reset to "" (set to drive off) by hardware. The LCD contrast can be adjusted in 6 stages. This adjustment is done by the contrast adjustment register LCLC3, and the setting values correspond to the contrast as shown in Table Table LCD contrast adjustment LC3 LC2 LC LC Contrast : : : : Dark Light 2 EPSON SC8865 TECHNICAL MANUAL

129 5..7 Control of LCD driver /8 FF D7 FRMCS DSPAR LCDC LCD frame signal source clock selection LCD display memory area selection LCD display control LCDC LCDC LCD display All LCDs lit D4 LCDC All LCDs out Normal display Drive off D3 LC3 LC2 D LC LC LCD contrast adjustment 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver) Table shows the LCD driver control bits. Table LCD driver control bits Address Bit Name Function SR Comment FF3 D7 D4 D3 Constantly "" when being read D VDSEL DBON Power source select for LCD voltage regulator Power voltage booster On/Off control V On VDD Off FF D7 HLMOD Heavy load protection mode On Off SEGREV Reverse SEG assignment Reverse Normal D4 D3 DTFNT register register register LCD dot font selection /5 8 Reserved register D LDUTY LCD drive duty selection LDUTY LDUTY Duty Not allowed LDUTY /6 /32 LC3 : LC2 : LC : LC : Contrast Dark : : Light PTM fosc Display area Display area These bits are reset to (, ) when SLP instruction is executed. LDUTY, LDUTY: FFH, D Selects the drive duty. Table Setting drive duty LDUTY LDUTY Duty Not allowed /6 /32 /8 Common terminal COMCOM5 COMCOM3 COMCOM7 Segment terminal SEGSEG25 SEGSEG25 SEGSEG25 Maximum number of display dots 2,6 dots 4,32 dots,8 dots At initial reset, LDUTY is set to "" (/6 duty). SC8865 TECHNICAL MANUAL EPSON 2

130 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver) DTFNT: FFH Selects the dot font. When "" is written: 2 2 dots When "" is written: 6 6/5 8 dots Reading: Valid Select 6 6/5 8 dots or 2 2 dots type for the display memory area. When "" is written to DTFNT, 6 6/5 8 dots is selected and when "" is written, 2 2 dots is selected. The correspondence between the display memory bits set according to the dot font, and the common/ segment terminals are shown in Figures At initial reset, DTFNT is set to "" (6 6/5 8 dots). SEGREV: FFH Reverses the memory allocation for the SEG terminals. Table Selecting SEG assignment SEGREV Assignment Reverse Normal FxH SEG25 SEG Fx7H SEG SEG25 At initial reset, SEGREV is set to "" (normal). DSPAR: FFH Selects the display area. When "" is written: Display area When "" is written: Display area Reading: Valid An area to be displayed is selected from two areas in the display memory. When "" is written to DSPAR, display area is selected and when "" is written, display area is selected. The correspondence between the display memory bits set according to the display area, and the common/segment terminals are shown in Figures At initial reset, DSPAR is set to "" (display area ). LCDC, LCDC: FFH D4, Controls the LCD display. Table LCD display control LCDC LCDC LCD display All LCDs lit (Static) All LCDs out (Dynamic) Normal display Drive OFF The four settings mentioned above can be made without changing the display memory data. At initial reset and in the SLEEP status, this register is set to "" (drive off). LCLC3: FFH D3 Adjusts the LCD contrast. Table LCD contract adjustment LC3 LC2 LC LC Contrast Dark Light The contrast can be adjusted in 6 stages as mentioned above. This adjustment changes the drive voltage on terminals VC to VC5. At initial reset, this register is set to "". FRMCS: FFH D7 Selects the source clock for generating the frame signal. When "" is written: Programmable timer 5 When "" is written: fosc Reading: Valid When "" is written to FRMCS, fosc is selected, and when "" is written, programmable timer 5 is selected. At initial reset, FRMCS is set to "" (fosc). 22 EPSON SC8865 TECHNICAL MANUAL

131 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver) DBON: FF3H Control the power voltage booster circuit. When "" is written: ON When "" is written: OFF Reading: Valid When "" is written to DBON, the power voltage booster activates and almost doubles the VDD voltage to generate the V voltage. Turn the power voltage booster on when driving the LCD system voltage regulator with V. When "" is written to DBON, the power voltage booster goes off. When driving the LCD system voltage regulator with VDD, turn the power voltage booster off to reduce current consumption. At initial reset, DBON is set to "" (OFF). VDSEL: FF3H D Selects the power voltage for the LCD system voltage regulator Programming notes () When the SLP instruction is executed, display control registers LCDC and LCDC are automatically reset to "" by hardware. (2) When driving the LCD system voltage regulator with V, wait at least msec for stabilization of the voltage before switching the power voltage for the LCD system voltage regulator to V using VDSEL after the power voltage booster is turned on. When "" is written: V When "" is written: VDD Reading: Valid When "" is written to VDSEL, the LCD system voltage regulator is driven with V generated by the power voltage booster. Before this setting is made, it is necessary to write "" to DBON to turn on the power voltage booster. Furthermore, do not switch the power voltage to V for at least msec after the power voltage booster is turned on to allow V stabilize. When "" is written to VDSEL, the LCD system voltage regulator is driven with VDD. At initial reset, VDSEL is set to "" (VDD). SC8865 TECHNICAL MANUAL EPSON 23

132 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (SVD Circuit) 5.2 Supply Voltage Detection (SVD) Circuit 5.2. Configuration of SVD circuit The SC8865 has a built-in SVD (supply voltage detection) circuit, so that the software can find when the source voltage lowers. Turning the SVD circuit ON/OFF and the SVD criteria voltage setting can be done with software. Figure shows the configuration of the SVD circuit SVD operation The SVD circuit compares the criteria voltage set by software and the supply voltage (VDDVSS) and sets its results into the SVDDT latch. By reading the data of this SVDDT latch, it can be determined by means of software whether the supply voltage is normal or has dropped. The criteria voltage can be set for the 3 types shown in Table by the SVDS3SVDS registers. Table Criteria voltage setting SVDS3 SVDS2 SVDS SVDS Criteria voltage (V) When the SVDON register is set to "", source voltage detection by the SVD circuit is executed. As soon as the SVDON register is reset to "", the result is loaded to the SVDDT latch and the SVD circuit goes OFF. To obtain a stable detection result, the SVD circuit must be ON for at least 5 µsec. So, to obtain the SVD detection result, follow the programming sequence below.. Set SVDON to "" 2. Maintain for 5 µsec minimum 3. Set SVDON to "" 4. Read SVDDT When the SVD circuit is ON, the IC draws a large current, so keep the SVD circuit off unless it is. V DD SVD circuit Detection output SVDDT VSS Criteria voltage setting circuit SVDON SVDS3 SVDS Data bus Fig Configuration of SVD circuit 24 EPSON SC8865 TECHNICAL MANUAL

133 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (SVD Circuit) Control of SVD circuit Table shows the SVD circuit control bits. Table SVD circuit control bits Address Bit Name Function SR FF2 D7 SVDDT SVD detection data Low Normal R D4 SVDON SVD circuit On/Off On Off D3 SVDS3 SVD criteria voltage setting SVDS2 SVDS3 SVDS2 SVDS SVDS (V) Voltage 2.7 D SVDS SVDS : : : : :.8 Comment Constantly "" when being read SVDS3SVDS: FF2H D3 Criteria voltage for SVD is set as shown in Table At initial reset, this register is set to "". SVDON: FF2H D4 Controls the SVD circuit ON and OFF. When "" is written: SVD circuit ON When "" is written: SVD circuit OFF Reading: Valid When the SVDON register is set to "", a supply voltage detection is executed by the SVD circuit. As soon as SVDON is reset to "", the result is loaded to the SVDDT latch. To obtain a stable detection result, the SVD circuit must be ON for at least 5 µsec. At initial reset, this register is set to "". SVDDT: FF2H This is the result of supply voltage detection. When "" is read: Supply voltage (VDDVSS) Criteria voltage When "" is read: Supply voltage (VDDVSS) < Criteria voltage Writing: Invalid The result of supply voltage detection at time of SVDON is set to "" can be read from this latch. At initial reset, SVDDT is set to "" Programming notes () To obtain a stable detection result, the SVD circuit must be ON for at least 5 µsec. So, to obtain the SVD detection result, follow the programming sequence below.. Set SVDON to "" 2. Maintain for 5 µsec minimum 3. Set SVDON to "" 4. Read SVDDT (2) The SVD circuit should normally be turned OFF because SVD operation increase current consumption. SC8865 TECHNICAL MANUAL EPSON 25

134 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Heavy Load Protection Function) 5.3 Heavy Load Protection Function 5.3. Outline of heavy load protection function The SC8865 has a heavy load protection function to prevent malfunction due to a power voltage fluctuation caused by a heavy battery load such as when an external lamp is driven and while the IC is running in high-speed with the OSC3 clock. This function works when the IC enters the heavy load protection mode. Set the IC into the heavy load protection mode when there are inconsistencies in density on the LCD panel as well as when the IC is under one of the condition above. The normal mode (heavy load protection function is off) changes to the heavy load protection mode (heavy load protection function is on) when the software changes the mode to the heavy load protection mode (HLMOD = ""). Note: Control of heavy load protection function In the heavy load protection mode, more current is consumed than in the normal mode. Unless necessary, do not select the heavy load protection mode with the software. Table shows the control bit for the heavy load protection function. Table Control bit for heavy load protection function Address Bit Name Function SR Comment FF D7 HLMOD Heavy load protection mode On Off SEGREV Reverse SEG assignment Reverse Normal D4 D3 DTFNT register register register LCD dot font selection /5 8 Reserved register D LDUTY LCD drive duty selection LDUTY LDUTY LDUTY Duty Not allowed /6 /32 /8 HLMOD: FFH D7 Controls the heavy load protection mode. When "" is written: Heavy load protection ON When "" is written: Heavy load protection OFF Reading: Valid The device enters the heavy load protection mode by writing "" to HLMOD, and returns to the normal mode by writing "". In the heavy load protection mode, the consumed current becomes larger. Unless necessary, do not select the heavy load protection mode with the software. At initial reset, this register is set to "" Programming note In the heavy load protection mode, more current is consumed than in the normal mode. Unless necessary, do not select the heavy load protection mode with the software. 26 EPSON SC8865 TECHNICAL MANUAL

135 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status) 5.4 Interrupt and Standby Status Types of interrupts 4 systems and 3 types of interrupts have been provided for the SC8865. External interrupt KK7 input interrupt (8 types) Internal interrupt Clock timer interrupt (4 types) Programmable timer interrupt (6 types) Serial interface interrupt (3 types) An interrupt factor flag that indicates the generation of an interrupt factor and an interrupt enable register that sets enable/disable for interrupt requests have been provided for each interrupt and interrupt generation can be optionally set for each factor. In addition, an interrupt priority register has been provided for each system of interrupts and the priority of interrupt processing can be set to 3 levels in each system. Figure 5.4. shows the configuration of the interrupt circuit. Refer to the explanations of the respective peripheral circuits for details on each interrupt. HALT status By executing the program's HALT instruction, the SC8865 enters the HALT status. Since CPU operation stops in the HALT status, power consumption can be reduced with only peripheral circuit operation. Cancellation of the HALT status is done by initial reset or an optional interrupt request, and the CPU restarts program execution from an exception processing routine. See the "SC88 Core CPU Manual" for the HALT status and reactivation sequence Interrupt generation conditions The interrupt factor flags that indicate the generation of their respective interrupt factors are provided for the previously indicated 4 systems and 3 types of interrupts and they will be set to "" by the generation of a factor. In addition, interrupt enable registers with a to correspondence to each of the interrupt factor flags are provided. An interrupt is enabled when "" is written and interrupt is disabled when "" is written. The CPU manages the enable/disable of interrupt requests at the interrupt priority level. An interrupt priority register that sets the priority level is provided for each of the interrupts of the 4 systems and the CPU accepts only interrupts above the level that has been indicated with the interrupt flags (I and I). Consequently, the following three conditions are necessary for the CPU to accept the interrupt. () The interrupt factor flag has been set to "" by generation of an interrupt factor. (2) The interrupt enable register corresponding to the above has been set to "". (3) The interrupt priority register corresponding to the above has been set to a priority level higher than the interrupt flag (I and I) setting. The CPU initially samples the interrupt for the first op-code fetch cycle of each instruction. Thereupon, the CPU shifts to the exception processing when the above mentioned conditions have been established. See the "SC88 Core CPU Manual" for the exception processing sequence. SLEEP status By executing the program's SLP instruction, the SC8865 enters the SLEEP status. Since the operation of the CPU and peripheral circuits stop completely in the SLEEP status, power consumption can be reduced even more than in the HALT status. Cancellation of the SLEEP status is done by initial reset or an input interrupt from the input port. The CPU reactivates after waiting 28/fOSC or 52/ fosc3 seconds of oscillation stabilization time (the oscillation stabilization time varies depending on the operating clock being used when the SLP instruction is executed). At this time, the CPU restarts program execution from an exception processing routine (input interrupt routine). Note: The oscillation becomes unstable for a while after SLEEP status is cancelled, the wait time for restarting the CPU may be longer than 28/fOSC or 52/fOSC3 seconds. SC8865 TECHNICAL MANUAL EPSON 27

136 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status) Interrupt factor flag Interrupt enable register Interrupt priority register Vector Interrupt vector address address generation circuit Data bus K7 FK7 EK7 K6 FK6 EK6 K5 FK5 EK5 Input port K4 K3 K2 K K FK4 EK4 FK3 EK3 FK2 EK2 FK EK FK EK PK PK Programmable timer Programmable timer Programmable timer 2 Programmable timer 3 Programmable timer 4 Programmable timer 5 Programmable timer 6 Programmable timer 7 Underflow Compare match Underflow Compare match Underflow Compare match Underflow Compare match Underflow Compare match Underflow Compare match Underflow Compare match Underflow Compare match FTU ETU FTC ETC FTU ETU FTC ETC FTU2 ETU2 FTC2 ETC2 FTU3 ETU3 FTC3 ETC3 FTU4 ETU4 FTC4 ETC4 FTU5 ETU5 FTC5 ETC5 FTU6 ETU6 FTC6 ETC6 FTU7 ETU7 FTC7 ETC7 PPT PPT PPT2 PPT3 PPT4 PPT5 PPT6 PPT7 Interrupt priority level judgement circuit NMI IRQ3 IRQ2 IRQ Error FSERR ESERR Serial interface Receive Transmit FSREC ESREC FSTRA ESTRA PSIF PSIF 32 Hz FTM32 ETM32 Clock timer 8 Hz 2 Hz Hz FTM8 ETM8 FTM2 ETM2 FTM ETM PTM PTM Fig Configuration of interrupt circuit 28 EPSON SC8865 TECHNICAL MANUAL

137 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status) Interrupt factor flag Table shows the correspondence between the factors generating an interrupt and the interrupt factor flags. The corresponding interrupt factor flags are set to "" by generation of the respective interrupt factors. The corresponding interrupt factor can be confirmed by reading the flags through software. Interrupt factor flag that has been set to "" is reset to "" by writing "". At initial reset, the interrupt factor flags are reset to "". Note: When executing the RETE instruction without resetting the interrupt factor flag after an interrupt has been generated, the same interrupt will be generated. Consequently, the interrupt factor flag corresponding to that routine must be reset (writing "") in the interrupt processing routine. Table Interrupt factors Interrupt factor K7 input of falling edge or rising edge (instruction at KCP7) K6 input of falling edge or rising edge (instruction at KCP6) K5 input of falling edge or rising edge (instruction at KCP5) K4 input of falling edge or rising edge (instruction at KCP4) K3 input of falling edge or rising edge (instruction at KCP3) K2 input of falling edge or rising edge (instruction at KCP2) K input of falling edge or rising edge (instruction at KCP) K input of falling edge or rising edge (instruction at KCP) Programmable timer underflow Programmable timer compare match Programmable timer underflow Programmable timer compare match Programmable timer 2 underflow Programmable timer 2 compare match Programmable timer 3 underflow Programmable timer 3 compare match Programmable timer 4 underflow Programmable timer 4 compare match Programmable timer 5 underflow Programmable timer 5 compare match Programmable timer 6 underflow Programmable timer 6 compare match Programmable timer 7 underflow Programmable timer 7 compare match Serial interface receiving error (in asynchronous mode) Serial interface receiving completion Serial interface transmitting completion Falling edge of the clock timer 32 Hz signal Falling edge of the clock timer 8 Hz signal Falling edge of the clock timer 2 Hz signal Falling edge of the clock timer Hz signal Interrupt factor flag FK7 FK6 FK5 FK4 FK3 FK2 FK FK FTU FTC FTU FTC FTU2 FTC2 FTU3 FTC3 FTU4 FTC4 FTU5 FTC5 FTU6 FTC6 FTU7 FTC7 FSERR FSREC FSTRA FTM32 FTM8 FTM2 FTM FF28H D7 FF28H FF28H FF28H D4 FF28H D3 FF28H FF28H D FF28H FF29H FF29H D FF29H FF29H D3 FF29H D4 FF29H FF29H FF29H D7 FF2EH FF2EH D FF2EH FF2EH D3 FF2EH D4 FF2EH FF2EH FF2EH D7 FF27H FF27H D FF27H FF26H D3 FF26H FF26H D FF26H SC8865 TECHNICAL MANUAL EPSON 29

138 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status) Interrupt enable register The interrupt enable register has a to correspondence with each interrupt factor flag and enable/disable of interrupt requests can be set. When "" is written to the interrupt enable register, an interrupt request is enabled, and is disabled when "" is written. This register also permits reading, thus making it possible to confirm that a status has been set. At initial reset, the interrupt enable registers are set to "" and shifts to the interrupt disable status. Table shows the correspondence between the interrupt enable registers and the interrupt factor flags. Table Interrupt enable registers and interrupt factor flags Interrupt Interrupt factor flag Interrupt enable register K7 input K6 input K5 input K4 input K3 input K2 input K input K input Timer underflow Timer compare match Timer underflow Timer compare match Timer 2 underflow Timer 2 compare match Timer 3 underflow Timer 3 compare match Timer 4 underflow Timer 4 compare match Timer 5 underflow Timer 5 compare match Timer 6 underflow Timer 6 compare match Timer 7 underflow Timer 7 compare match Serial interface receiving error Serial interface receiving completion Serial interface transmitting completion Clock timer 32 Hz Clock timer 8 Hz Clock timer 2 Hz Clock timer Hz FK7 FK6 FK5 FK4 FK3 FK2 FK FK FTU FTC FTU FTC FTU2 FTC2 FTU3 FTC3 FTU4 FTC4 FTU5 FTC5 FTU6 FTC6 FTU7 FTC7 FSERR FSREC FSTRA FTM32 FTM8 FTM2 FTM FF28H D7 FF28H FF28H FF28H D4 FF28H D3 FF28H FF28H D FF28H FF29H FF29H D FF29H FF29H D3 FF29H D4 FF29H FF29H FF29H D7 FF2EH FF2EH D FF2EH FF2EH D3 FF2EH D4 FF2EH FF2EH FF2EH D7 FF27H FF27H D FF27H FF26H D3 FF26H FF26H D FF26H EK7 EK6 EK5 EK4 EK3 EK2 EK EK ETU ETC ETU ETC ETU2 ETC2 ETU3 ETC3 ETU4 ETC4 ETU5 ETC5 ETU6 ETC6 ETU7 ETC7 ESERR ESREC ESTRA ETM32 ETM8 ETM2 ETM FF24H D7 FF24H FF24H FF24H D4 FF24H D3 FF24H FF24H D FF24H FF25H FF25H D FF25H FF25H D3 FF25H D4 FF25H FF25H FF25H D7 FF2CH FF2CH D FF2CH FF2CH D3 FF2CH D4 FF2CH FF2CH FF2CH D7 FF23H FF23H D FF23H FF22H D3 FF22H FF22H D FF22H 3 EPSON SC8865 TECHNICAL MANUAL

139 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status) Interrupt priority register and interrupt priority level Interrupt KK7 input interrupt Programmable timer interrupt Programmable timer interrupt 32 Programmable timer interrupt 54 Programmable timer interrupt 76 Serial interface interrupt Clock timer interrupt Table Interrupt priority register Interrupt priority register PK, PK PPT, PPT PPT2, PPT3 PPT4, PPT5 PPT6, PPT7 PSIF, PSIF PTM, PTM FF2, D7 FF2, D3 FF2 D4, FF2A, D FF2A, D3 FF2 D4, FF2, D The interrupt priority registers shown in Table are set to each system of interrupts and the interrupt priority levels for the CPU can be set to the optional priority level (3). As a result, it is possible to have multiple interrupts that match the system's interrupt processing priority levels. The interrupt priority level between each system can optionally be set to three levels by the interrupt priority register. However, when more than one system is set to the same priority level, they are processed according to the default priority level. Table Setting of interrupt priority level P* P* Interrupt priority level Level 3 (IRQ3) Level 2 (IRQ2) Level (IRQ) Level (None) At initial reset, the interrupt priority registers are all set to "" and each interrupt is set to level. Furthermore, the priority levels in each system have been previously decided and they cannot be changed. The CPU can mask each interrupt by setting the interrupt flags (I and I). The relation between the interrupt priority level of each system and interrupt flags is shown in Table , and the CPU accepts only interrupts above the level indicated by the interrupt flags. The NMI (watchdog timer) that has level 4 priority, is always accepted regardless of the setting of the interrupt flags. Table Interrupt mask setting of CPU I I Acceptable interrupt Level 4 (NMI) Level 4, Level 3 (IRQ3) Level 4, Level 3, Level 2 (IRQ2) Level 4, Level 3, Level 2, Level (IRQ) After an interrupt has been accepted, the interrupt flags are written to the level of that interrupt. However, interrupt flags after an NMI has been accepted are written to level 3 (I = I = ""). Table Interrupt flags after acceptance of interrupt Accepted interrupt priority level I I Level 4 (NMI) Level 3 (IRQ3) Level 2 (IRQ2) Level (IRQ) The set interrupt flags are reset to their original value on return from the interrupt processing routine. Consequently, multiple interrupts up to 3 levels can be controlled by the initial settings of the interrupt priority registers alone. Additional multiplexing can be realized by rewriting the interrupt flags and interrupt enable register in the interrupt processing routine. Note: Beware. If the interrupt flags have been rewritten (set to lower priority) prior to resetting an interrupt factor flag after an interrupt has been generated, the same interrupt will be generated again. SC8865 TECHNICAL MANUAL EPSON 3

140 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status) Exception processing vectors When the CPU accepts an interrupt request, it starts exception processing following completion of the instruction being executed. In exception processing, the following operations branch the program. () In the minimum mode, the program counter (PC) and system condition flag (SC) are moved to stack and in the maximum mode, the code bank register (CB), PC and SC are moved. (2) The branch destination address is read from the exception processing vector corresponding to each exception processing (interrupt) factor and is placed in the PC. An exception vector is 2 bytes of data in which the top address of each exception (interrupt) processing routine has been stored and the vector addresses correspond to the exception processing factors as shown in Table Note: An exception processing vector is fixed at 2 bytes, so it cannot specify a branch destination bank address. Consequently, to branch from multiple banks to a common exception processing routine, the top portion of an exception processing routine must be described within the common area (H7FFFH). Table Vector address and exception processing correspondence Vector Exception processing factor Priority address H 2H 4H 6H 8H AH CH EH H 2H 4H 6H 8H AH CH EH 2H 22H 24H 26H 28H 2AH 2CH 2EH 3H 32H 34H 36H 38H 3AH 3CH 3EH 4H 42H 44H 46H 48H 4AH 4CH 4EH : FEH Reset Zero division Watchdog timer (NMI) K7 input interrupt K6 input interrupt K5 input interrupt K4 input interrupt K3 input interrupt K2 input interrupt K input interrupt K input interrupt PTM underflow interrupt PTM compare match interrupt PTM underflow interrupt PTM compare match interrupt PTM 2 underflow interrupt PTM 2 compare match interrupt PTM 3 underflow interrupt PTM 3 compare match interrupt System reserved (cannot be used) Serial I/F error interrupt Serial I/F receiving complete interrupt Serial I/F transmitting complete interrupt System reserved (cannot be used) System reserved (cannot be used) System reserved (cannot be used) Clock timer 32 Hz interrupt Clock timer 8 Hz interrupt Clock timer 2 Hz interrupt Clock timer Hz interrupt PTM 4 underflow interrupt PTM 4 compare match interrupt PTM 5 underflow interrupt PTM 5 compare match interrupt PTM 6 underflow interrupt PTM 6 compare match interrupt PTM 7 underflow interrupt PTM 7 compare match interrupt System reserved (cannot be used) Software interrupt High Low No priority rating 32 EPSON SC8865 TECHNICAL MANUAL

141 5.4.6 Control of interrupt FF2 D7 D4 D3 D PPT3 PPT2 PPT PPT FF2A D7 D4 D3 PPT7 PPT6 D PPT5 PPT4 FF22 D7 D4 D3 ETM32 ETM8 D ETM2 ETM FF23 D7 D4 D3 ESERR D ESREC ESTRA 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status) Table shows the interrupt control bits. Table (a) Interrupt control bits Address Bit Name Function SR Comment FF2 D7 PK KK7 interrupt priority register PK PK Priority PSIF PSIF level PK Level 3 PSIF Serial interface interrupt priority register Level 2 Level D4 PSIF Level D3 Constantly "" when being read D PTM Clock timer interrupt priority register PTM PTM Priority level Level 3 PTM Level 2 Level Level Programmable timer 32 interrupt priority register Programmable timer interrupt priority register Programmable timer 76 interrupt priority register Programmable timer 54 interrupt priority register Clock timer 32 Hz interrupt enable register Clock timer 8 Hz interrupt enable register Clock timer 2 Hz interrupt enable register Clock timer Hz interrupt enable register Serial I/F (error) interrupt enable register Serial I/F (receiving) interrupt enable register Serial I/F (transmitting) interrupt enable register PPT3 PPT PPT7 PPT5 Interrupt enable Interrupt enable PPT2 PPT PPT6 PPT4 Priority level Level 3 Level 2 Level Level Priority level Level 3 Level 2 Level Level Interrupt disable Interrupt disable Constantly "" when being read Constantly "" when being read Constantly "" when being read Constantly "" when being read Constantly "" when being read SC8865 TECHNICAL MANUAL EPSON 33

142 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status) Table (b) Interrupt control bits Address Bit Name Function SR FF24 D7 EK7 K7 interrupt enable EK6 K6 interrupt enable EK5 K5 interrupt enable D4 EK4 K4 interrupt enable Interrupt Interrupt D3 EK3 K3 interrupt enable enable disable EK2 K2 interrupt enable D EK K interrupt enable EK K interrupt enable FF25 D7 D4 D3 D ETC3 ETU3 ETC2 ETU2 ETC ETU ETC ETU FF2C D7 ETC7 ETU7 ETC6 D4 ETU6 D3 ETC5 ETU5 D ETC4 ETU4 FF26 D7 D4 D3 FTM32 FTM8 D FTM2 FTM FF27 D7 D4 D3 FSERR D FSREC FSTRA FF28 D7 FK7 FK6 FK5 D4 FK4 D3 FK3 FK2 D FK FK PTM3 compare match interrupt enable PTM3 underflow interrupt enable PTM2 compare match interrupt enable PTM2 underflow interrupt enable PTM compare match interrupt enable PTM underflow interrupt enable PTM compare match interrupt enable PTM underflow interrupt enable PTM7 compare match interrupt enable PTM7 underflow interrupt enable PTM6 compare match interrupt enable PTM6 underflow interrupt enable PTM5 compare match interrupt enable PTM5 underflow interrupt enable PTM4 compare match interrupt enable PTM4 underflow interrupt enable Clock timer 32 Hz interrupt factor flag Clock timer 8 Hz interrupt factor flag Clock timer 2 Hz interrupt factor flag Clock timer Hz interrupt factor flag Serial I/F (error) interrupt factor flag Serial I/F (receiving) interrupt factor flag Serial I/F (transmitting) interrupt factor flag K7 interrupt factor flag K6 interrupt factor flag K5 interrupt factor flag K4 interrupt factor flag K3 interrupt factor flag K2 interrupt factor flag K interrupt factor flag K interrupt factor flag Interrupt enable Interrupt enable (R) Generated (W) Reset (R) Generated (W) Reset (R) Interrupt factor is generated (W) Reset Interrupt disable Interrupt disable (R) Not generated (W) No operation (R) Not generated (W) No operation (R) No interrupt factor is generated (W) No operation Comment Constantly "" when being read Constantly "" when being read 34 EPSON SC8865 TECHNICAL MANUAL

143 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status) Table (c) Interrupt control bits Address Bit Name Function SR Comment FF29 D7 FTC3 PTM3 compare match interrupt factor flag (R) (R) FTU3 PTM3 underflow interrupt factor flag Interrupt No interrupt FTC2 PTM2 compare match interrupt factor flag factor is factor is D4 FTU2 PTM2 underflow interrupt factor flag generated generated D3 FTC PTM compare match interrupt factor flag FTU PTM underflow interrupt factor flag (W) (W) D FTC PTM compare match interrupt factor flag Reset No operation FTU PTM underflow interrupt factor flag FF2E D7 FTC7 PTM7 compare match interrupt factor flag (R) (R) FTU7 PTM7 underflow interrupt factor flag Interrupt No interrupt FTC6 PTM6 compare match interrupt factor flag factor is factor is D4 FTU6 PTM6 underflow interrupt factor flag generated generated D3 FTC5 PTM5 compare match interrupt factor flag FTU5 PTM5 underflow interrupt factor flag (W) (W) D FTC4 PTM4 compare match interrupt factor flag Reset No operation FTU4 PTM4 underflow interrupt factor flag Refer to the explanations on the respective peripheral circuits for the setting content and control method for each bit Programming notes () When executing the RETE instruction without resetting the interrupt factor flag after an interrupt has been generated, the same interrupt will be generated. Consequently, the interrupt factor flag corresponding to that routine must be reset (writing "") in the interrupt processing routine. (2) Beware. If the interrupt flags (I and I) have been rewritten (set to lower priority) prior to resetting an interrupt factor flag after an interrupt has been generated, the same interrupt will be generated again. (3) An exception processing vector is fixed at 2 bytes, so it cannot specify a branch destination bank address. Consequently, to branch from multiple banks to a common exception processing routine, the front portion of an exception processing routine must be described within the common area (H7FFFH). (4) Do not execute the SLP instruction for 2 msec after a NMI interrupt has occurred (when fosc is khz). SC8865 TECHNICAL MANUAL EPSON 35

144 6 SUMMARY OF NOTES 6 SUMMARY OF NOTES 6. Notes for Low Current Consumption The SC8865 can turn circuits, which consume a large amount of power, ON or OFF by control registers. You can reduce power consumption by creating a program that operates the minimum necessary circuits using these control registers. Next, which circuit systems' operation can be controlled and their control registers (instructions) are explained. You should refer to these when programming. See Chapter 8, "ELECTRICAL CHARACTERIS- TICS" for the current consumption. Refer to "Programming notes" in each peripheral section for precautions of each peripheral circuit. Circuit type CPU Oscillation circuit Power voltage booster LCD controller SVD circuit Heavy lord protection Table 6.. Circuit systems and control registers Control register (Instruction) Status at time of initial resetting HALT and SLP instructions CLKCHG, SOSC3 DBON LCDC, LCDC SVDON HLMOD Operation status OSC3 clock (CLKCHG = "") OSC3 oscillation ON (SOSC3 = "") OFF status (DBON = "") Drive OFF (LCDC = LCDC = "") OFF status (SVDON = "") OFF status (HLMOD = "") 36 EPSON SC8865 TECHNICAL MANUAL

145 6 SUMMARY OF NOTES 6.2 Precautions on Mounting <Oscillation Circuit> Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when a ceramic or crystal oscillator is used, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following points to prevent this: () Components which are connected to the OSC, OSC2, OSC3 and OSC4 terminals, such as oscillators, resistors and capacitors, should be connected in the shortest line. (2) As shown in the right hand figure, make a VSS pattern as large as possible at circumscription of the OSC, OSC2, OSC3 and OSC4 terminals and the components connected to these terminals. Furthermore, do not use this VSS pattern for any purpose other than the oscillation system. Sample VSS pattern (OSC3) OSC4 OSC3 VSS In order to prevent unstable operation of the oscillation circuit due to current leak between OSC/OSC3 and VDD, please keep enough distance between OSC/OSC3 and VDD or other signals on the board pattern. <Power Supply Circuit> Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: () The power supply should be connected to the VDD and VSS terminal with patterns as short and large as possible. (2) When connecting between the VDD and VSS terminals with a bypass capacitor, the terminals should be connected as short as possible. Bypass capacitor connection example VDD VSS VDD VSS (3) Components which are connected to the VD, VC, VC2, VC3, VC4 and VC5 terminals, such as capacitors and resistors, should be connected in the shortest line. In particular, the VC, VC2, VC3, VC4 and VC5 voltages affect the display quality. <Arrangement of Signal Lines> In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit. When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction. Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit. Prohibited pattern <Reset Circuit> The power-on reset signal which is input to the RESET terminal changes depending on conditions (power rise time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. When the built-in pull-up resistor of the RESET terminal is used, take into consideration dispersion of the resistance for setting the constant. In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the RESET terminal in the shortest line. Large current signal line High-speed signal line SC8865 TECHNICAL MANUAL EPSON 37 OSC4 OSC3 VSS

146 6 SUMMARY OF NOTES <Precautions for Visible Radiation (when bare chip is mounted)> Visible radiation causes semiconductor devices to change the electrical characteristics. It may cause this IC to malfunction. When developing products which use this IC, consider the following precautions to prevent malfunctions caused by visible radiations. () Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use. (2) The inspection process of the product needs an environment that shields the IC from visible radiation. (3) As well as the face of the IC, shield the back and side too. 38 EPSON SC8865 TECHNICAL MANUAL

147 7 BASIC EXTERNAL WIRING DIAGRAM 7 BASIC EXTERNAL WIRING DIAGRAM LCD panel 26 x 32 RCR3 RCR 2 4 CG X'tal CG2 X'tal2 or Ceramic C C C2 C3 C4 C5 C6 C7 C8 C9 VSS OSC OSC2 OSC3 Recommended values for external parts Rf C C Cres 3 V - + CP 3 OSC4 VD VC VC2 VC3 VC4 VC5 CA CB CC CD CE V CF CG RESET VDD TEST SEG SEG25 COM COM3 SC8865 [The potential of the substrate (back of the chip) is VSS.] KK2 K3 (BREQ) K4K7 RR7 (AA7) RR7 (A8A5) R2R23 (A6A9) R24 (RD) R25 (WR) R3R32 (CECE2) R33 (BACK) PP7 (D7) P (SIN) P (SOUT) P2 (SCLK) P3 (SRDY) P4 (TOUT/TOUT) P5 (TOUT2/TOUT3) P6 (FOUT) P7 (TOUT2/TOUT3) : OSC = Crystal oscillation 2: OSC = CR oscillation 3: OSC3 = Crystal or Ceramic oscillation 4: OSC3 = CR oscillation Symbol X'tal CG RCR X'tal2 Ceramic Rf CG2 C RCR3 Name Crystal oscillator Trimmer capacitor Resistor for CR oscillation Crystal oscillator Ceramic oscillator Feedback resistor Gate capacitor Drain capacitor Resistor for CR oscillation Recommended value khz, CI(Max.) = 35 kω 25 pf.5 MΩ 4 MHz 4 MHz MΩ 5 pf (Crystal oscillation) 3 pf (Ceramic oscillation) 5 pf (Crystal oscillation) 3 pf (Ceramic oscillation) 4 kω Symbol C C2 C3 C4 C5 C6 C7C9 C C CP Cres Name Capacitor between VSS and VD Capacitor between VSS and VC Capacitor between VSS and VC2 Capacitor between VSS and VC3 Capacitor between VSS and VC4 Capacitor between VSS and VC5 Booster capacitors Capacitor between VSS and V Booster capacitor Capacitor for power supply Capacitor for RESET terminal Recommended value. µf. µf. µf. µf. µf. µf. µf. µf. µf 3.3 µf.47 µf Note: The above table is simply an example, and is not guaranteed to work. SC8865 TECHNICAL MANUAL EPSON 39

148 8 ELECTRICAL CHARACTERISTICS 8 ELECTRICAL CHARACTERISTICS 8. Absolute Maximum Rating (VSS = V) Item Symbol Condition Rated value Unit Note Power voltage Liquid crystal power voltage Input voltage Output voltage High level output current Low level output current VDD VC5 VI VO IOH IOL terminal Total of all terminals terminal Total of all terminals -.3 to to to VDD to VDD V V V V ma ma ma ma Permitted loss Operating temperature Storage temperature Soldering temperature / time PD Topr Tstg Tsol 2-2 to to C, sec (lead section) mw C C Note) In case of plastic package. 8.2 Recommended Operating Conditions Operating power voltage Operating frequency Capacitor between VD and VSS Capacitor between VC and VSS Capacitor between VC2 and VSS Capacitor between VC3 and VSS Capacitor between VC4 and VSS Capacitor between VC5 and VSS Item Symbol Condition Min. Typ. Max. Unit VDD fosc fosc3 Capacitor between CA and CB C7 Capacitor between CA and CC C8 Capacitor between CD and CE C9 Capacitor between V and VSS C Capacitor between CF and CG C Note) When LCD drive power is not used, the capacitor is not necessary. In this case, leave the VC to VC5 and CA to CG terminals open. C C2 C3 C4 C5 C6 CR oscillation Crystal/ceramic oscillation V khz MHz MHz µf µf µf µf µf µf µf µf µf µf µf Note 4 EPSON SC8865 TECHNICAL MANUAL

149 8 ELECTRICAL CHARACTERISTICS 8.3 DC Characteristics Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = -2 to 7 C Item Symbol Condition Min. Typ. Max. Unit High level input voltage Low level input voltage High level schmitt input voltage () Low level schmitt input voltage () High level schmitt input voltage (2) Low level schmitt input voltage (2) High level output current Low level output current Input leak current Output leak current Input pull-up resistance Input terminal capacitance Segment/Common output current VIH VIL VT+ VT- VT2+ VT2- IOH IOL ILI ILO RIN CIN ISEGH ISEGL Kxx, Pxx Kxx, Pxx RESET, MCU/MPU RESET, MCU/MPU Kxx Kxx Pxx, Rxx, VOH =.9 VDD Pxx, Rxx, VOL =. VDD Kxx, Pxx, RESET, MCU/MPU Pxx, Rxx Kxx, Pxx, RESET, MCU/MPU Kxx, Pxx VIN = V, f = MHz, Ta = 25 C SEGxx, COMxx, VSEGH = VC5-. V SEGxx, COMxx, VSEGL =. V.8VDD.5VDD.VDD.5VDD.VDD VDD.2VDD.9VDD.5VDD.9VDD.5VDD V V V V V V ma ma µa µa kω pf µa µa Note) When CMOS Schmitt level is selected by mask option. 2 When addition of pull-up resistor is selected by mask option. Note 2 VDD VOUT (V) VT- VT+ VDD VIN (V) SC8865 TECHNICAL MANUAL EPSON 4

150 8 ELECTRICAL CHARACTERISTICS 8.4 Analog Circuit Characteristics LCD drive circuit The typical values in the following LCD driver characteristics varies depending on the panel load (panel size, number of display pixels and display contents), so evaluate them by connecting to the actually used LCD panel. Refer to Section 8.8, "Characteristics Curves" for the load characteristic. Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, CC =. µf, When a checker pattern is displayed, No panel load Item Symbol Condition Min. Typ. Max. Unit Note LCD drive voltage VC VC2 VC3 VC4 * *2 *3 *4.8 VC5.39 VC5.59 VC5.79 VC5.22 VC5.43 VC5.63 VC5.83 VC5 V V V V VC5 *5 LCX = H LCX = H LCX = 2H LCX = 3H LCX = 4H LCX = 5H LCX = 6H V V V V V V V LCX = 7H LCX = 8H LCX = 9H LCX = AH LCX = BH LCX = CH LCX = DH LCX = EH LCX = FH Typ Typ.6 V V V V V V V V V * *2 *3 *4 *5 Connects MΩ load resistor between VSS and VC. Connects MΩ load resistor between VSS and VC2. Connects MΩ load resistor between VSS and VC3. Connects MΩ load resistor between VSS and VC4. Connects MΩ load resistor between VSS and VC5. SVD circuit Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C Item Symbol Condition Min. Typ. Max. Unit SVD voltage VSVD SVDS3 = "" SVDS3 = "" SVDS3 = "2" SVDS3 = "3" SVDS3 = "4" SVDS3 = "5" SVDS3 = "6" SVDS3 = "7" SVDS3 = "8" V V V V V V V V V SVDS3 = "9" SVDS3 = "" SVDS3 = "" SVDS3 = "2" SVDS3 = "3" SVDS3 = "4" SVDS3 = "5" Typ Typ.9 V V V V V V V SVD circuit response time tsvd 5 µs Note 42 EPSON SC8865 TECHNICAL MANUAL

151 8 ELECTRICAL CHARACTERISTICS 8.5 Power Current Consumption Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, CC =. µf, No panel load Item Symbol Condition Min. Typ. Max. Unit Note Current consumption in SLEEP mode Current consumption in HALT mode Current consumption during execution ISLP IHALT IHALT2 IHALT3 IHALT4 IEXE IEXE2 OSC = OFF, OSC3 = OFF OSC = 32kHz Crystal, OSC3 = OFF OSC = 32kHz CR, OSC3 = OFF OSC = 32kHz Crystal, OSC3 = 8MHz Ceramic OSC = 32kHz CR, OSC3 = 2MHz CR OSC = 32kHz Crystal, OSC3 = OFF OSC = 32kHz CR, OSC3 = OFF µa µa µa µa µa µa µa IEXE3 OSC = 32kHz Crystal, OSC3 = 8MHz Ceramic 7 3 µa Current consumption during execution in heavy load protection mode LCD circuit current LCD circuit current in heavy load protection mode LCD circuit current when the power voltage booster is active LCD circuit current in heavy load protection mode when the power voltage booster is active SVD circuit current IEXE4 IHVL IHVL2 ILCD ILCDH ILC ILCH ISVD OSC = 32kHz CR, OSC3 = 2MHz CR OSC = 32kHz Crystal, OSC3 = OFF, HLMOD = H OSC = 32kHz CR, OSC3 = OFF, HLMOD = H LCDCx = All on, LCx = FH, fosc = kHz, VDD = 2.5 to 3.6V LCDCx = All on, LCx = FH, fosc = kHz, HLMOD = H LCDCx = All on, LCx = FH, fosc = kHz, DBON = H, VDD =.8 to 2.5V LCDCx = All on, LCx = FH, fosc = kHz, DBON = H, VDD =.8 to 2.5V, HLMOD = H SVDON = ON µa µa µa µa µa µa µa µa Note) This value is added to the current consumption during execution when the LCD circuit is active. Current consumption increases according to the display contents and panel load. This value is added to the current consumption during execution in heavy load protection mode when the LCD circuit is active. Current consumption increases according to the display contents and panel load. This value is added to the current consumption during execution when the power voltage booster and the LCD circuit are active. Current consumption increases according to the display contents and panel load. This value is added to the current consumption during execution in heavy load protection mode when the power voltage booster and the LCD circuit are active. Current consumption increases according to the display contents and panel load. This value is added to the current consumption during execution or current consumption during execution in heavy load protection mode when the SVD circuit is active. SC8865 TECHNICAL MANUAL EPSON 43

152 8 ELECTRICAL CHARACTERISTICS 8.6 AC Characteristics Operating range Condition: VDD =.8 to 3.6 V, VSS = V, Ta = -2 to 7 C Item Symbol Condition Min. Typ. Max. Unit Operating frequency Instruction execution time (during operation with OSC clock) Instruction execution time (during operation with OSC3 clock) fosc fosc3 tcy tcy VDD =.8 to 3.6 V -cycle instruction 2-cycle instruction 3-cycle instruction 4-cycle instruction 5-cycle instruction 6-cycle instruction -cycle instruction 2-cycle instruction 3-cycle instruction 4-cycle instruction 5-cycle instruction 6-cycle instruction khz MHz µs µs µs µs µs µs µs µs µs µs µs µs Note 44 EPSON SC8865 TECHNICAL MANUAL

153 8 ELECTRICAL CHARACTERISTICS External memory access Read cycle Condition: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VIH2 =.6 V, VIL2 =.6 V, VOH =.8VDD, VOL =.2VDD, CL = pf (load capacitance) Item Symbol Min. Typ. Max. Unit Address set-up time in read cycle Address hold time in read cycle Read signal pulse width Data input set-up time in read cycle Data input hold time in read cycle tras trah trp trds trdh tc+tl-5+n tc/2 th-4 tc-+n tc/2 5 ns ns ns ns ns Note) Substitute the number of states for wait insertion in n. Write cycle Condition: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VIH2 =.6 V, VIL2 =.6 V, VOH =.8VDD, VOL =.2VDD, CL = pf (load capacitance) Item Symbol Min. Typ. Max. Unit Address set-up time in write cycle Address hold time in write cycle Write signal pulse width Data output set-up time in write cycle Data output hold time in write cycle twas twah twp twds twdh tc-9 th-4 tl-2+n tc/2 tc-9+n tc/2 th-4 th+4 ns ns ns ns ns Note) Substitute the number of states for wait insertion in n. Note Note tc* ICLK VIH2 VIL2 th* tl* AA9 CE VOH VOL RD VOH VOL tras trah DIN trp VIH VIL trds trdh AA9 CE VOH VOL WR DOUT twas VIH VIL VOH VOL twp twds twah twdh * In the case of crystal oscillation and ceramic oscillation: th =.5tc ±.5tc, tl = tc - th (/tc: oscillation frequency) * In the case of CR oscillation: th =.5tc ±.tc, tl = tc - th (/tc: oscillation frequency) SC8865 TECHNICAL MANUAL EPSON 45

154 8 ELECTRICAL CHARACTERISTICS Serial interface Clock synchronous master mode Condition: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VOH =.8VDD, VOL =.2VDD Item Symbol Min. Typ. Max. Unit Transmitting data output delay time Receiving data input set-up time Receiving data input hold time tsmd tsms tsmh 25 ns ns ns Note Clock synchronous slave mode Condition: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VOH =.8VDD, VOL =.2VDD Item Symbol Min. Typ. Max. Unit Transmitting data output delay time Receiving data input set-up time Receiving data input hold time tssd tsss tssh 25 ns ns ns Note Asynchronous system Condition: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C Item Symbol Min. Typ. Max. Unit Note Start bit detection error time Erroneous start bit detection range time tsa tsa2 9t/6 t/6 t/6 s s 2 Note) 2 Start bit detection error time is a logical delay time from inputting the start bit until internal sampling begins operating. (Time as far as AC is excluded.) Erroneous start bit detection range time is a logical range to detect whether a LOW level (start bit) has been input again after a start bit has been detected and the internal sampling clock has started. When a HIGH level is detected, the start bit detection circuit is reset and goes into a wait status until the next start bit. (Time as far as AC is excluded.) SCLK OUT VOL VOH SOUT tsmd VOH VOL SIN VIH VIL tsms tsmh SCLK IN VIL VIH SOUT tssd VOH VOL SIN VIH VIL tsss tssh Start bit Stop bit SIN Sampling clock tsa Erroneous start bit detection signal tsa2 t 46 EPSON SC8865 TECHNICAL MANUAL

155 8 ELECTRICAL CHARACTERISTICS Input clock SCLK, EXCL input clock Condition: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD Item Symbol Min. Typ. Max. Unit SCLK input clock time EXCL input clock time (with noise rejecter) EXCL input clock time (without noise rejecter) Cycle time "H" pulse width "L" pulse width Cycle time "H" pulse width "L" pulse width Cycle time "H" pulse width "L" pulse width tsccy tsch tscl tevcy tevh tevl tevcy tevh tevl 2 64/fOSC 32/fOSC 32/fOSC 2 µs µs µs s s s µs µs µs Input clock rising time Input clock falling time tckr tckf ns ns Note SCLK EXCL tsccy tckf tckr VIH VIL tscl tsch tevcy tckf tckr VIH VIL tevl tevh RESET input clock Condition: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, VIH =.5VDD, VIL =.VDD Item Symbol Min. Typ. Max. Unit RESET input time tsr µs Note tsr RESET VIL VIH SC8865 TECHNICAL MANUAL EPSON 47

156 8 ELECTRICAL CHARACTERISTICS Power ON reset using an external capacitor Condition: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C Item Symbol Min. Typ. Max. Unit Operating power voltage RESET input time Vsr tpsr.8 V ms Note VDD Vsr tpsr RESET Power ON.VDD.5VDD * VDD RESET VSS * Because the potential of the RESET terminal not reached VDD level or higher. 48 EPSON SC8865 TECHNICAL MANUAL

157 8.7 Oscillation Characteristics 8 ELECTRICAL CHARACTERISTICS Oscillation characteristics change depending on conditions (board pattern, components used, etc.). Use the following characteristics as reference values. In particular, when a ceramic oscillator or crystal oscillator is used for OSC3, use the oscillator manufacturer s recommended values for constants such as capacitance and resistance. The oscillation start time is important because it becomes the wait time when OSC3 clock is used. (If OSC3 is used as CPU clock before oscillation stabilizes, the CPU may malfunction.) OSC (Crystal) Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, Crystal oscillator = Q2C2 (Ri = 3 kω Typ.)*, CG = 25 pf, CD = Built-in Item Symbol Condition Min. Typ. Max. Unit Oscillation start time External gate capacitance Built-in drain capacitance Frequency/IC deviation Frequency/power voltage deviation Frequency adjustment range tsta CG CD f/ IC f/ V f/ CG Including board capacitance In case of the chip VDD = constant VDD = constant, CG = 5 to 25 pf s pf pf ppm ppm/v ppm * Q2C2 Made by Seiko Epson corporation Note OSC (CR) Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C Item Symbol Condition Min. Typ. Max. Unit Oscillation start time Frequency/IC deviation tsta f/ IC RCR = constant µs % Note OSC3 (Crystal) Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, Crystal oscillator = Q2CA3*, RF = MΩ, CG2 = C = 5 pf Item Symbol Condition Min. Typ. Max. Unit Note Oscillation start time tsta ms Note) * Q2CA3 Made by Seiko Epson corporation The crystal oscillation start time changes by the crystal oscillator to be used, CG2 and C. OSC3 (Ceramic) Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, Ceramic oscillator = KBR-4.MSB/KBR-8.MSB*, RF = MΩ, CG2 = C = 3 pf Item Symbol Condition Min. Typ. Max. Unit Note Oscillation start time tsta ms Note) * KBR-4.MSB/KBR-8.MSB Made by Kyocera The ceramic oscillation start time changes by the ceramic oscillator to be used, CG2 and C. OSC3 (CR) Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C Item Symbol Condition Min. Typ. Max. Unit Oscillation start time Frequency/IC deviation tsta f/ IC RCR = constant µs % Note SC8865 TECHNICAL MANUAL EPSON 49

158 8 ELECTRICAL CHARACTERISTICS 8.8 Characteristics Curves (reference value) High level output current-voltage characteristic. Ta = 7 C, Max. value VDDVOH [V] IOH [ma] -6-9 VDD =.8 V -2-5 VDD = 3.6 V VDD = 2.4 V Low level output current-voltage characteristic 5 VDD = 3.6 V VDD = 2.4 V Ta = 7 C, Min. value VDD =.8 V 2 IOL [ma] VOL [V] 5 EPSON SC8865 TECHNICAL MANUAL

159 8 ELECTRICAL CHARACTERISTICS LCD drive voltage-supply voltage characteristic (when the power voltage booster is not used) Connects MΩ load resistor between VSS and VC5. (no panel load) 7. Ta = 25 C, Typ. value 6. LCx = FH VC5 [V] LCx = H VDD [V] LCD drive voltage-supply voltage characteristic (when the power voltage booster is used) Connects MΩ load resistor between VSS and VC5. (no panel load) 7. Ta = 25 C, Typ. value 6. LCx = FH VC5 [V] LCx = H VDD [V] SC8865 TECHNICAL MANUAL EPSON 5

160 8 ELECTRICAL CHARACTERISTICS LCD drive voltage-ambient temperature characteristic.5vc5 Typ. value VC5 [V].4VC5.3VC5.2VC5.VC5.VC5.99VC5.98VC5.97VC5.96VC5.95VC Ta [ C] LCD drive voltage-load characteristic 5.3 Ta = 25 C, Typ. value, LCx = 8H VC5 [V] IVC5 [µa] 52 EPSON SC8865 TECHNICAL MANUAL

161 8 ELECTRICAL CHARACTERISTICS SVD voltage-ambient temperature characteristic.5vsvd Typ. value, SVDSx = FH VSVD [V].4VSVD.3VSVD.2VSVD.VSVD.VSVD.99VSVD.98VSVD.97VSVD.96VSVD.95VSVD Ta [ C] SC8865 TECHNICAL MANUAL EPSON 53

162 8 ELECTRICAL CHARACTERISTICS In HALT status current consumption temperature characteristic (During operation with OSC) <Crystal oscillation, fosc = khz> Typ. value 8 6 IHALT [µa] Ta [ C] In HALT status current consumption resistor characteristic (During operation with OSC) <CR oscillation> 6 Ta = 25 C 5 IHALT2 [µa] Max. Typ. RCR [kω] 54 EPSON SC8865 TECHNICAL MANUAL

163 8 ELECTRICAL CHARACTERISTICS In executed status current consumption temperature characteristic (During operation with OSC) <Crystal oscillation, fosc = khz> Typ. value 6 2 IEXE [µa] Ta [ C] In executed status current consumption resistor characteristic (During operation with OSC) <CR oscillation> 6 Ta = 25 C IEXE2 [µa] Max. Typ. RCR [kω] SC8865 TECHNICAL MANUAL EPSON 55

164 8 ELECTRICAL CHARACTERISTICS In executed status current consumption frequency characteristic (During operation with OSC3) <Crystal oscillation/ceramic oscillation> Ta = 25 C Max. IEXE3 [µa] Typ fosc3 [MHz] In executed status current consumption resistor characteristic (During operation with OSC3) <CR oscillation> 8 Ta = 25 C IEXE4 [µa] Max. Typ. RCR3 [kω] 56 EPSON SC8865 TECHNICAL MANUAL

165 8 ELECTRICAL CHARACTERISTICS Oscillation frequency resistor characteristic (OSC) <CR oscillation> Ta = 25 C, Typ. value fosc [khz] RCR [kω] Oscillation frequency temperature characteristic (OSC) <CR oscillation> Typ. value, RCR = 5 kω fosc [khz] Ta [ C] SC8865 TECHNICAL MANUAL EPSON 57

166 8 ELECTRICAL CHARACTERISTICS Oscillation frequency resistor characteristic (OSC3) <CR oscillation> Ta = 25 C, Typ. value fosc3 [khz] RCR3 [kω] Oscillation frequency temperature characteristic (OSC3) <CR oscillation> Typ. value, RCR3 = 4 kω fosc3 [khz] Ta [ C] 58 EPSON SC8865 TECHNICAL MANUAL

167 9 PACKAGE 9 PACKAGE 9. Plastic Package QFP22-256pin (Unit: mm) 3 ±.4 28 ± ±. 3 ±.4 INDEX max.4 ± ± SC8865 TECHNICAL MANUAL EPSON 59

168 6 EPSON SC8865 TECHNICAL MANUAL 9 PACKAGE 9.2 Ceramic Package for Test Samples PGA-256pin (Unit: mm) Pin name Pin No. Pin No. Pin name R2/A6 R2/A7 R22/A8 R23/A9 R24/RD R25/WR R3/CE R3/CE VDD N.C. N.C. N.C. N.C. N.C. VSS R32/CE2 R33/BACK COM COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM COM COM2 COM3 COM4 COM5 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 N.C. N.C. VDD OSC3 OSC4 VSS VD OSC OSC2 TEST RESET MPU/MPU K7/EXCL3 K6/EXCL2 K5/EXCL K4/EXCL K3/BREQ K2 K K P7/TOUT2/TOUT3 P6/FOUT P5/TOUT2/TOUT3 P4/TOUT/TOUT P3/SRDY P2/SCLK P/SOUT P/SIN P7/D7 P6/ P5/ P4/D4 P3/D3 P2/ P/D P/ R/A R/A R2/A2 R3/A3 R4/A4 R5/A5 R6/A6 R7/A7 R/A8 R/A9 R2/A R3/A R4/A2 R5/A3 R6/A4 R7/A5 Pin No. Pin name SEG9 SEG2 SEG2 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG3 SEG3 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 VSS N.C. N.C. N.C. N.C. N.C. TEST SEG39 SEG4 SEG4 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG5 SEG5 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG6 SEG6 SEG62 SEG63 Pin No. Pin name SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG7 SEG7 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG8 SEG8 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG9 SEG9 SEG92 SEG93 SEG94 SEG95 SEG96 N.C. N.C. N.C. N.C. N.C. VSS SEG97 SEG98 SEG99 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 Pin No. Pin name SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG2 SEG2 SEG22 SEG23 SEG24 SEG25 COM3 COM3 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM2 COM2 COM9 COM8 COM7 COM6 V CG CF CE CD CC CB CA VC5 VC4 VC3 VC2 VC N.C. N.C. N.C A D4 C2 D3 B E4 E3 C F4 E2 F3 D G4 F2 G3 E H4 G2 H3 F J3 H2 J4 G J2 H K3 J K4 K K2 L L2 M L4 N L3 N2 M2 P M4 P2 M3 R N3 R2 N4 T P3 T2 R3 Y4 U2 W4 V2 Y5 V3 W5 U3 Y6 V4 W6 V5 Y7 U4 W7 V6 Y8 U5 W8 V7 Y9 U6 W9 V8 Y2 U7 V9 U8 W2 T7 U9 T8 V2 R7 T9 R8 U2 P7 R9 P8 T2 N7 P9 N8 R2 M8 N9 M7 P2 M9 N2 L8 M2 L7 L2 L9 K2 K9 J2 K7 H2 K8 H9 J9 G2 J7 G9 J8 F2 H8 F9 H7 E2 G8 E9 F8 G7 D9 E8 C2 F7 C9 D8 B2 E7 B9 C8 A2 D7 B8 C7 A9 B7 C6 A8 B6 C5 A7 D4 B5 C4 A6 D3 B4 C3 A5 C2 B3 A4 B2 A3 C A2 D A B A B A9 A8 C B8 B9 A7 D9 B7 C9 A6 C8 B6 D8 A5 C7 B5 C6 A4 D7 B4 C5 A3 B3 C4 A2 B2 C3 U P4 U2 T3 V R4 V2 U3 W T4 W2 V3 Y U4 W3 V4 Y2 U5 W4 V5 Y3 U6 W5 V6 Y4 U7 W6 V7 Y5 U8 W7 V8 Y6 V9 W8 U9 Y7 W9 Y8 V Y9 U Y W Y W Y2 U Y3 V W3 W INDEX Extra pin Bottom View ±.5 φ.46 ± A B C D E F G H J K L M N P R T U V W Y

169 PAD LAYOUT PAD LAYOUT. Diagram of Pad Layout Y X (, ) mm Die. No. 6.7 mm Chip thickness: 4 µm Pad opening: 9 µm Pad 9 is used for the IC shipment test, so you should not bond it. SC8865 TECHNICAL MANUAL EPSON 6

170 62 EPSON SC8865 TECHNICAL MANUAL PAD LAYOUT.2 Pad Coordinates (Unit: mm) No Name VDD OSC3 OSC4 VSS VD OSC OSC2 TEST RESET MCU/MPU K7/EXCL3 K6/EXCL2 K5/EXCL K4/EXCL K3/BREQ K2 K K P7/TOUT2/TOUT3 P6/FOUT P5/TOUT2/TOUT3 P4/TOUT/TOUT P3/SRDY P2/SCLK P/SOUT P/SIN P7/D7 P6/ P5/ P4/D4 P3/D3 P2/ P/D P/ R/A R/A R2/A2 R3/A3 R4/A4 R5/A5 R6/A6 R7/A7 R/A8 R/A9 R2/A R3/A R4/A2 R5/A3 R6/A4 R7/A5 R2/A6 R2/A7 R22/A8 R23/A9 R24/RD R25/WR R3/CE R3/CE VDD X Y Pad Coordinates No X Y Pad Coordinates No Name VSS SEG97 SEG98 SEG99 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG2 SEG2 SEG22 SEG23 SEG24 SEG25 COM3 COM3 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM2 COM2 COM9 COM8 COM7 COM6 V CG CF CE CD CC CB CA VC5 VC4 VC3 VC2 VC X Y Pad Coordinates No Name TEST SEG39 SEG4 SEG4 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG5 SEG5 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG6 SEG6 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG7 SEG7 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG8 SEG8 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG9 SEG9 SEG92 SEG93 SEG94 SEG95 SEG96 X Y Pad Coordinates Name VSS R32/CE2 R33/BACK COM COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM COM COM2 COM3 COM4 COM5 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG2 SEG2 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG3 SEG3 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 VSS

171 APPENDIX A S5UC88P&S5UC88649P2 MANUAL (Peripheral Circuit Board for SC8865) APPENDIX A S5UC88P&S5UC88649P2 MANUAL (Peripheral Circuit Board for SC8865) This manual describes how to use the Peripheral Circuit Board for SC8865 (S5UC88P&S5UC88649P2). This circuit board is used to provide emulation functions when it is installed in the ICE (S5UC88H5), a debugging tool for the 8-bit Single Chip Microcomputer SC88 Family. The explanation assumes that the SC8865 circuit data has been downloaded into the SC88 Family Peripheral Circuit Board (S5UC88P). Refer to the "S5UC88P Manual" for how to download circuit data into the SC88 Family Peripheral Circuit Board (S5UC88P) and common specifications of the board. For details on ICE functions and how to operate the debugger, refer to the separately prepared manuals. A. Names and Functions of Each Part The following explains the names and functions of each part of the S5UC88P&S5UC88649P2. () SW LCDVCC (on the back) I/O # connector I/O #2 connector (2) (26) (26) Main board (S5UC88P) Fig. A.. Board layout I/O #3 connector I/O #4 connector (26) (26) Add-on board (S5UC88649P2) (3) (4) (5) (6) (7) (8) (9) (26) VLCD VSVD H OSC L H OSC3 L RESET S5UC88P SC88 Family Peripheral circuit board EPSON LED I/O # I/O #2 MONITOR (24) (25) (26) Fig. A..2 Panel layout (S5UC88P) SC8865 TECHNICAL MANUAL EPSON 63

172 APPENDIX A S5UC88P&S5UC88649P2 MANUAL (Peripheral Circuit Board for SC8865) () SW When downloading circuit data, set this switch to the "3" position. Otherwise, set to position "". (2) LCDVCC (on the back of the S5UC88P board) The internal power voltage (VC5) for the LCD driver can be varied using the DIP switch as shown in Table A... Be aware that the VC5 voltage level on this board is different from that of the actual IC. Table A.. Setting LCDVCC LCDVCC Setting ON OFF OFF ON OFF ON OFF OFF OFF OFF ON OFF OFF OFF OFF ON Other combinations VC5 = 6 V VC5 = 5.75 V VC5 = 5.5 V VC5 = 5 V Not allowed The voltage value assumes that the LCD contrast adjustment register LCLC3 is FH. There is a need to allow for a maximum ±6% of error due to the characteristics of the parts used on this board. (3) VLCD control Unused. (4) VSVD control This control is used for varying the power supply voltage to confirm the supply voltage detection (SVD) function. (Refer to Section A.2.2, "Differences from Actual IC".) (5) OSC H control This control is used for coarse adjustment of the OSC CR oscillation frequency. (6) OSC L control This control is used for fine adjustment of the OSC CR oscillation frequency. (7) OSC3 H control This control is used for coarse adjustment of the OSC3 CR oscillation frequency. (8) OSC3 L control This control is used for fine adjustment of the OSC3 CR oscillation frequency. (9) RESET switch This switch initializes the internal circuits of this board and feeds a reset signal to the ICE. () LED (MPU/MCU) Indicates the MPU or MCU mode. Lit: MPU mode Not lit: MCU mode () LED 2 (BUSMOD), LED 3 (CPUMOD) Indicates the bus and CPU modes (BUSMOD/ CPUMOD register settings). Table A..2 Bus and CPU modes BUSMOD Lit Lit Not lit Not lit CPUMOD Lit Not lit Lit Not lit Bus mode Expansion Single chip CPU mode Maximum Minimum Maximum Minimum (2) LED 4 (CLKCHG) Indicates the CPU operating clock. Lit: OSC3 (CLKCHG register = "") Not lit: OSC (CLKCHG register = "") (3) LED 5 (SOSC3) Indicates the OSC3 oscillation status. Lit: OSC3 oscillation is on (SOSC3 register = "") Not lit: OSC3 oscillation is off (SOSC3 register = "") (4) LED 6 (SVDON) Indicates the SVD circuit status. Lit: SVD circuit is on (SVDON register = "") Not lit: SVD circuit is off (SVDON register = "") (5) LED 7 (LCDC) Indicates the LCD circuit status. Lit: LCD circuit is on (LCDC register = Not "") Not lit: LCD circuit is off (LCDC register = "") (6) LED 8 (HLMOD) Indicates the heavy load protection status. Lit: Heavy load protection mode (HLMOD register = "") Not lit: Normal mode (HLMOD register = "") (7) LED 9 (HALT/SLEEP) Indicates the CPU status. Lit: HALT or SLEEP Not lit: RUN (8) LED (VDSEL) Indicates the power voltage (VDD or V) selected for the LCD system voltage regulator. Lit: V (VDSEL register = "") Not lit: VDD (VDSEL register = "") (9) LED (DBON) Indicates the status of the power voltage booster. Lit: ON (DBON register = "") Not lit: OFF (DBON register = "") (2) LED 2 (SEGREV) Indicates the SEG output assignment status. Lit: Reverse (SEGREV register = "") Not lit: Normal (SEGREV register = "") 64 EPSON SC8865 TECHNICAL MANUAL

173 APPENDIX A S5UC88P&S5UC88649P2 MANUAL (Peripheral Circuit Board for SC8865) (2) LED 3 (Reserved) Unused. (22) LED 4 (OSC operating clock) The OSC operating clock is connected to this LED. The corresponding monitor pin (pin 4) can be used to check the OSC clock frequency. (23) LED 5 (OSC3 operating clock) The OSC3 operating clock is connected to this LED. The corresponding monitor pin (pin 5) can be used to check the OSC3 clock frequency. (24) LED 6 (FPGA configuration) If the FPGA on the S5UC88P includes circuit data, this LED lights when the power is turned on. If this LED does not light at powerup, a circuit data must be written to the FPGA before debugging can be started (turn the power on again after writing data). (25) LED signal monitor connector This connector provides the signals that drive the LEDs shown above for monitoring. The signals listed below are output from the connector pins. The signal level is high when the LED is lit and is low when the LED is not lit Fig. A..3 LED signal monitor connector Pin : LED (MPU/MCU mode) Pin 2: LED 2 (Bus mode ) Pin 3: LED 3 (CPU mode ) Pin 4: LED 4 (CPU operating clock) Pin 5: LED 5 (OSC3 oscillation status) Pin 6: LED 6 (SVD circuit status) Pin 7: LED 7 (LCD circuit status) Pin 8: LED 8 (Heavy load protection status) Pin 9: LED 9 (HALT/SLEEP, RUN status) Pin : LED (LCD voltage regulator power status) Pin : LED (Power voltage booster status) Pin 2: LED 2 (SEG output assignment status) Pin 4: OSC operating clock Pin 5: OSC3 operating clock Pin 8: OSC CR oscillation frequency monitor pin Pin 9: OSC3 CR oscillation frequency monitor pin Pins 3, 7 and 2 are not used. The OSC3 CR oscillation clock is connected to pins 8 and 9. (The CR oscillation circuit on this board always operates even if crystal oscillation is selected by mask option and regardless of the SOSC3 register status.) These pins can be used to monitor CR oscillation when adjusting the oscillation frequency. (26) I/O #, I/O #2, I/O #3, I/O #4 connectors These are the connectors for connecting the I/ O and LCD. The I/O cables (8-pin/4-pin 2 flat type, -pin/5-pin 2 flat type, 4-pin/ 2-pin 2 flat type) are used to connect to the target system A.2 Precautions Take the following precautions when using the S5UC88P&S5UC88649P2. A.2. Precaution for operation () Turn the power of all equipment off before connecting or disconnecting cables. (2) Make sure that the input ports (KK3) are not all set to low when turning the power on until the mask option data is loaded, as the key-entry reset function may activated. (3) The mask option data must be loaded before debugging can be started. A.2.2 Differences from actual IC Caution is called for due to the following function and property related differences with the actual IC. If these precautions are overlooked, it may not operate on the actual IC, even if it operates on the ICE in which the S5UC88P&S5UC88649P2 has been installed. () I/O differences Interface power voltage This board and target system interface voltage is set to +3.3 V. To obtain the same interface voltage as in the actual IC, attach a level shifter or similar circuit on the target system side to accommodate the required interface voltage. Drive capability of each output port The drive capability of each output port on this board is higher than that of the actual IC. When designing the application system and software, refer to Chapter 8, "ELECTRICAL CHARACTERISTICS" to confirm the drive capability of each output port. Input port characteristics The AC characteristic of the input terminal is different from that of the actual IC and it affects the input interrupt function. Therefore, evaluate the operation in the actual IC if the rise/fall time of the input signal is long. Protective diode of each port All I/O ports incorporate a protective diode for VDD and VSS, and the interface signals between this board and the target system are set to +3.3 V. Therefore, this board and the target system cannot be interfaced with a voltage exceeding VDD even if the output ports are configured with open-drain output. SC8865 TECHNICAL MANUAL EPSON 65

174 APPENDIX A S5UC88P&S5UC88649P2 MANUAL (Peripheral Circuit Board for SC8865) Pull-up resistance value The pull-up resistance values on this board are set to 3 kω which differ from those for the actual IC. For the resistance values on the actual IC, refer to Chapter 8, "ELECTRICAL CHARACTERISTICS". Note that when using pull-up resistors to pull the input terminals high, the input terminals may require a certain period to reach a valid high level. Exercise caution if a key matrix circuit is configured using a combination of output and input ports, since rise delay times on these input ports differ from those of the actual IC. (2) Differences in current consumption The amount of current consumed by this board differs significantly from that of the actual IC. Inspecting the LEDs on the S5UC88P front panel may help keep track of approximate current consumption. The following factors/components greatly affect device current consumption: Those which can be verified by LEDs and monitor pins a) Run and Halt execution ratio (verified by LEDs and monitor pins on the ICE) b) CPU operating clock change control (LED 4: monitor pin 4) c) OSC3 oscillation on/off control (LED 5: monitor pin 5) d) SVD circuit on/off control (LED 6: monitor pin 6) e) LCD power supply control (LED 7: monitor pin 7) f) Heavy load protection mode (LED 8: monitor pin 8) g) SLEEP and Halt execution ratio (LED 9: monitor pin 9) h) LCD voltage regulator power selection (LED : monitor pin ) i) Power voltage booster (LED : monitor pin ) j) OSC operating clock (LED 4: monitor pin 4) k) OSC3 operating clock (LED 5: monitor pin 5) Those that can only be counteracted by system or software l) Current consumed by the internal pull-up resistors m) Input ports in a floating state (3) Functional precautions LCD circuit Pay attention to the output drive capability and output voltage of the LCD terminals (SEG, COM), since they are different from those of the actual IC. The system and the software should be designed in order to adjust the LCD contrast. The S5UC88P board allows switching of the LCD drive voltage with its switch on the back side. (Refer to Section A., "Names and Functions of Each Part") When the LCDC and LCDC registers are both set to "" (LCD power control circuit is off), the SEG and COM terminal outputs of the actual IC are fixed at VSS level. Note, however, that the COM outputs are fixed at VC4 level and the SEG outputs are fixed at VC3 level in this board. This board supports 6 6/5 8 dot font only and 2 2 dot font can not be used. (Writing and reading to/from DTFNT bit are enabled.) This board does not support reversing of the SEG assignment using the SEGREV bit. Check whether LE is lit or not to confirm the SEGREV status. (Writing and reading to/from SEGREV bit are enabled.) The actual IC outputs only COM to COM5 signals even if the display area is switched (DSPAR = "") when the LCD driver is set to /6 (r /8) duty drive. This board outputs COM6 to COM3 signals with the same waveform as the COM to COM5. Therefore, if COM6 to COM3 along with COM to COM5 are connected to the LCD panel, the LCD panel displays the same contents twice to the upper half and lower half. SVD circuit The SVD function is realized by artificially varying the power supply voltage using the VSVD control on the front panel of the S5UC88P. There is a finite delay time from when the power to the SVD circuit turns on until actual detection of the voltage. The delay time on this board differs from that of the actual IC. Refer to Chapter 8, "ELECTRICAL CHARACTERIS- TICS" when setting the appropriate wait time for the actual IC. The evaluation voltages supported in this board are different from those of the actual IC. When debugging the SVD operation using this board, evaluate the SVD results as levels not voltages. 66 EPSON SC8865 TECHNICAL MANUAL

175 APPENDIX A S5UC88P&S5UC88649P2 MANUAL (Peripheral Circuit Board for SC8865) Oscillation circuit The OSC crystal oscillation frequency is fixed at khz. The OSC CR oscillation frequency can be adjusted in the range of approx. 2 khz to 5 khz using the control on the S5UC88P front panel. Note that the actual IC does not operate with all of these frequencies; refer to Chapter 8, "ELECTRICAL CHARACTERIS- TICS" to select the appropriate operating frequency. The OSC3 crystal oscillation frequency is fixed at MHz. The OSC3 CR oscillation frequency can be adjusted in the range of approx. khz to 8 MHz using the control on the S5UC88P front panel. Note that the actual IC does not operate with all of these frequencies; refer to Chapter 8, "ELECTRICAL CHARACTERIS- TICS" to select the appropriate operating frequency. The S5UC88P&S5UC88649P2 does not include the OSC3 ceramic oscillation circuit. When ceramic oscillation circuit is selected by mask option, the S5UC88649P2 uses the onboard crystal oscillation circuit. When using an external clock, adjust the external clock (amplitude: 3.3 V ±5%, duty: 5% ±%) and input to the OSC or OSC3 terminal with VSS as GND. This board can operate normally even when the CPU clock is switched to OSC3 (CLKCHG = "") immediately after the OSC3 oscillation control circuit is turned on (SOSC3 = "") without a wait time inserted. In the actual IC, an oscillation stability wait time is required before switching the CPU clock after the OSC3 oscillation is turned on. Refer to Chapter 8, "ELECTRICAL CHARACTERISTICS" when setting the appropriate wait time for the actual IC. Use separate instructions to switch the clock from OSC3 to OSC and to turn off the OSC3 oscillation circuit. If executed simultaneously with a single instruction, these operations, although good with this board, may not function properly with the actual IC. This board contains oscillation circuits for OSC and OSC3. Keep in mind that even though the actual IC may not have a resonator connected to its OSC3, this board can operate with the OSC3 circuit. Because the logic level of the oscillation circuit is high, the timing at which the oscillation starts on this board differs from that of theactual IC. Access to undefined address space If any undefined space in the SC8865's internal ROM/RAM or I/O is accessed for data read or write operations, the read/written value is indeterminate. Additionally, it is important to remain aware that the indeterminate state differs between this board and the actual IC. Reset circuit Keep in mind that the operation sequence from when the ICE with this board installed is powered on until the time at which the program starts running differs from the sequence of the actual IC. This is because this board becomes capable of operating as a debugging system after the user program and optional data are downloaded. Internal power supply circuit The LCD drive voltage on this board is different from that on the actual IC. Size of the Kanji-font ROM The actual IC contains 896K bytes of Kanji-font memory (address H to EFFFFH). The memory size implemented in the ICE is 448K bytes. Function option Input interface level The actual IC allows selection of the input interface level either COMS level or CMOS Schmitt level by a function option. This board supports CMOS level only and selection of the function option using Winfog does not affect the interface level of this board. (4) Notes on model support Parameter file The ROM, RAM and I/O spaces in the ICE with this board installed are configured when the debugger on the personal computer starts up using the parameter file (8865.par) provided for each model. The parameter file allows the user to modify its contents according to the ROM and RAM spaces actually used. Do not configure areas other than below when using the IC in single chip maximum mode. ROM area: H to BFFFH H to EFFFFH RAM area: D8H to F7FFH Stack area: D8H to F7FFH Access disable area When using this board for development of an SC8865 application, be sure not to read and write from/to I/O memory addresses FF6H and FF9H to FFADH. Furthermore, do not change the initial values when writing to bit D4 of address FF7H, bits and D7 of address FF2H, bit D7 of address FF22H, and bit D7 of address FF26H. SC8865 TECHNICAL MANUAL EPSON 67

176 APPENDIX A S5UC88P&S5UC88649P2 MANUAL (Peripheral Circuit Board for SC8865) A.3 Connecting to the Target System This section explains how to connect the S5UC88P&S5UC88649P2 to the target system. Note: Turn the power of all equipment off before connecting or disconnecting cables. Use the I/O cables (8-pin/4-pin 2 flat type, -pin/5-pin 2 flat type, 4-pin/2-pin 2 flat type) to connect between the I/O # to I/O #4 connectors of the front panel and the target system. Connect the 8-pin, -pin and 4-pin cable connectors to the I/O # to I/O #4 connectors, and the 4-pin 2, 5-pin 2 and 2-pin 2 connectors to the target system. Be careful as power (VDD) is supplied to I/O #, I/O #2 and I/O #3 connectors. The following shows the clock frequencies generated from the on-board crystal oscillation circuits: OSC crystal oscillation circuit: khz OSC3 crystal oscillation circuit: MHz When CR oscillation is selected, the oscillation frequency can be adjusted using the controls on the front panel (OSCH and OSCL for adjusting OSC, OSC3H and OSC3L for adjusting OSC3). Use a frequency counter or other equipment to be connected to the OSC CR oscillation frequency monitor pin (pin 8) on the monitor connector or OSC3 CR oscillation frequency monitor pin (pin 9) for monitoring the frequency during adjustment. Be sure of the frequency when using this monitor pin because the CR oscillation frequency is initially undefined. VLCD VSVD H OSC L H OSC3 L RESET LCD S5UC88P SC88 Family Peripheral circuit board EPSON I/O # I/O #2 MONITOR POWER EMU SLP/HALT TRGOUT STOPOUT TRCIN BRKIN GND RESET DIAG ON/OFF ICE88UR EC88 Family In-Circuit Emulator I/O #3 (4-pin) I/O # (8-pin) I/O #2 (8-pin) I/O #4 (-pin) CN3-2 (2-pin) CN3- (2-pin) CN-2 (4-pin) CN- (4-pin) CN2- (4-pin) CN2-2 (4-pin) CN4- (5-pin) CN4-2 (5-pin) CN3-2 CN3- CN-2 CN- CN2- CN2-2 CN4- CN4-2 Target board Fig. A.3. Connecting to the target system 68 EPSON SC8865 TECHNICAL MANUAL

177 APPENDIX A S5UC88P&S5UC88649P2 MANUAL (Peripheral Circuit Board for SC8865) I/O connector pin assignment No Table A.3. I/O # connector 4-pin CN- 4-pin CN-2 Pin name VDD (3.3 V) VDD (3.3 V) VSS VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. R/A R/A R2/A2 R3/A3 R4/A4 R5/A5 R6/A6 R7/A7 R/A8 R/A9 No Pin name R2/A R3/A R4/A2 R5/A3 R6/A4 R7/A5 R2/A6 R2/A7 R22/A8 R23/A9 R24/RD R25/WR N.C. N.C. R3/CE R3/CE R32/CE2 R33/(BACK) N.C. N.C. N.C. N.C. N.C. N.C. COM COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM COM COM2 COM3 COM4 COM5 No Table A.3.2 I/O #2 connector 4-pin CN2-4-pin CN2-2 Pin name VDD (3.3 V) VDD (3.3 V) VSS VSS RESET MCU/MPU OSCEX OSC3EX N.C. N.C. N.C. N.C. N.C. SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG2 SEG2 SEG22 SEG23 SEG24 SEG25 SEG26 No Pin name SEG27 SEG28 SEG29 SEG3 SEG3 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG4 SEG4 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG5 SEG5 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG6 SEG6 SEG62 SEG63 SEG64 SEG65 SEG Fig. A.3.2 CN-/CN-2 and CN2-/CN2-2 pin layout SC8865 TECHNICAL MANUAL EPSON 69

178 APPENDIX A S5UC88P&S5UC88649P2 MANUAL (Peripheral Circuit Board for SC8865) No Table A.3.3 I/O #3 connector 2-pin CN3-2-pin CN3-2 Pin name No. Pin name K VSS K 2 VSS K2 3 P/ K3(BREQ) 4 P/D K4/EXCL 5 P2/ K5/EXCL 6 P3/D3 K6/EXCL2 7 P4/D4 K7/EXCL3 8 P5/ N.C. 9 P6/ N.C. P7/D7 N.C. VDD (3.3 V) N.C. 2 VDD (3.3 V) N.C. 3 P/SIN N.C. 4 P/SOUT N.C. 5 P2/SCLK N.C. 6 P3/SRDY N.C. 7 P4/TOUT/TOUT N.C. 8 P5/TOUT2/TOUT3 N.C. 9 P6/FOUT N.C. 2 P7/TOUT2/TOUT3 No Table A.3.4 I/O #4 connector 5-pin CN4-5-pin CN4-2 Pin name No. Pin name SEG67 SEG7 SEG68 2 SEG8 SEG69 3 SEG9 SEG7 4 SEG2 SEG7 5 SEG2 SEG72 6 SEG22 SEG73 7 SEG23 SEG74 8 SEG24 SEG75 9 SEG25 SEG76 N.C. SEG77 N.C. SEG78 2 N.C. SEG79 3 N.C. SEG8 4 N.C. SEG8 5 N.C. SEG82 6 N.C. SEG83 7 N.C. SEG84 8 N.C. SEG85 9 N.C. SEG86 2 N.C. SEG87 2 N.C. SEG88 22 N.C. SEG89 23 N.C. SEG9 24 N.C. SEG9 25 N.C. SEG92 26 N.C. SEG93 27 N.C. SEG94 28 N.C. SEG95 29 N.C. SEG96 3 N.C. SEG97 3 N.C. SEG98 32 N.C. SEG99 33 N.C. SEG 34 VSS SEG 35 COM6 SEG2 36 COM7 SEG3 37 COM8 SEG4 38 COM9 SEG5 39 COM2 SEG6 4 COM2 SEG7 4 COM22 SEG8 42 COM23 SEG9 43 COM24 SEG 44 COM25 SEG 45 COM26 SEG2 46 COM27 SEG3 47 COM28 SEG4 48 COM29 SEG5 49 COM3 SEG6 5 COM3 7 EPSON SC8865 TECHNICAL MANUAL

179 APPENDIX A S5UC88P&S5UC88649P2 MANUAL (Peripheral Circuit Board for SC8865) A.4 Product Specifications The components specifications of the S5UC88649P2 are listed below. S5UC88649P2 Dimensions (mm): 84 (W) 52 (D) 7 (H) I/O cable (-pin/5-pin x 2) S5UC88649P2 connector (-pin): KEL 883E--7L Cable connector (-pin): KEL 8822E--7L Cable connector (5-pin): Connector 3M 795-B5SC 2 Strain relief 3M Cable: 5-pin flat cable Interface: CMOS interface (3.3 V) Length: Approx. 4 cm I/O cable (4-pin/2-pin x 2) S5UC88649P2 connector (4-pin): KEL 883E-4-7L Cable connector (4-pin): KEL 8822E-4-7L Cable connector (2-pin): Connector 3M 792-B5SC 2 Strain relief 3M Cable: 2-pin flat cable Interface: CMOS interface (3.3 V) Length: Approx. 4 cm Accessories 5-pin connector for the target system: 3M LCSC 2 2-pin connector for the target system: 3M LCSC 2 SC8865 TECHNICAL MANUAL EPSON 7

180 APPENDIX B USING KANJI FONT APPENDIX B USING KANJI FONT Use the S5UC88R (2 2-dot RIS 56 kanji font package) to display kanji font on an LCD in the SC8865 microcomputer. This package contains 2 2-dot-sized fonts (Seiko Epson original design Note ) for the character codes conforming to the music shift-jis kanji stipulated in the Recording Industry Association of Japan standard RIS , which are supplied in the form of embeddable data for SC88- Family microcomputer programs. The package also contains a sample program that runs on the SC88-Family microcomputer to display this font data on an LCD, an application note for the sample program, and a bitmap utility that can be used to create custom font data. User-developed program The kanji font data is supplied in an object file format (assembler output file identified by the extension.obj) to enable it to be embedded in the SC88-Family microcomputer programs. Simply by linking this object file to the created application program, the kanji font data can be used easily. Note 2 See the "S5UC88R Manual" for details. Notes Before the kanji font data included with the package and the typefaces shown in the manual can be used, a contract for a license to use the typefaces must be concluded between Seiko Epson and the purchaser. 2 The programs necessary to obtain font data from the character codes and display the font data on an LCD must be created by the user. Compile Assemble Linker Locator Font data object ROM size used: 33,388 bytes Shown here is the typeface of an excerpted kanji font. Executable file 72 EPSON SC8865 TECHNICAL MANUAL