MF CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C6P366. Technical Manual. S1C6P366 Technical Hardware

Transcription

1 MF299-5 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER SC6P366 Technical Manual SC6P366 Technical Hardware

2 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. MS-DOS, Windows, Windows 95, Windows 98 and Windows NT are registered trademarks of Microsoft Corporation, U.S.A. PC-DOS, PC/AT, PS/2, VGA, EGA and IBM are registered trademarks of International Business Machines Corporation, U.S.A. NEC PC-98 Series and NEC are registered trademarks of NEC Corporation. All other product names mentioned herein are trademarks and/or registered trademarks of their respective owners. This product uses SuperFlash technology licensed from Silicon Storage Technology, Inc. SEIKO EPSON CORPORATION 23, All rights reserved.

3 Revisions and Additions for this manual Chapter 4 7 Section Page Item Control of LCD display and drive waveform () Display ON/OFF control Programming notes Summary of Notes by Function Programmable timer Contents A part of contents was deleted. (6) was added. (5) was added.

4

5 Configuration of product number Devices S C 6358 F A Packing specifications : Besides tape & reel A : TCP BL 2 directions B : Tape & reel BACK C : TCP BR 2 directions D : TCP BT 2 directions E : TCP BD 2 directions F : Tape & reel FRONT G : TCP BT 4 directions H : TCP BD 4 directions J : TCP SL 2 directions K : TCP SR 2 directions L : Tape & reel LEFT M : TCP ST 2 directions N : TCP SD 2 directions P : TCP ST 4 directions Q : TCP SD 4 directions R : Tape & reel RIGHT 99 : Specs not fixed Specification Package D: die form; F: QFP Model number Model name C: microcomputer, digital products Product classification S: semiconductor Development tools S5U C 63 A Packing specifications : standard packing Version : Version Tool type Hx : ICE Ex : EVA board Px : Peripheral board Wx : Flash ROM writer for the microcomputer Xx : ROM writer peripheral board Cx : C compiler package Ax : Assembler package Dx : Utility tool by the model Qx : Soft simulator Corresponding model number 63: common to SC63 Family Tool classification C: microcomputer use Product classification S5U: development tool for semiconductor products

6

7 CONTENTS CONTENTS CHAPTER OUTLINE. Features....2 Block Diagram Pin Layout Diagram Pin Description Mask Option Segment Option... 5 CHAPTER 2 POWER SUPPLY AND INITIAL RESET 6 2. Power Supply Voltage <VD> for oscillation circuit and internal circuits Voltage <VCVC3> for LCD driving Operating mode of power supply circuit Initial Reset Reset terminal (RESET) Internal register at initial resetting Terminal settings at initial resetting Test Terminal (TEST) Terminals for Flash EEPROM... CHAPTER 3 CPU, PROM, RAM 3. CPU Code PROM RAM... CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION 3 4. Memory Map Watchdog Timer Configuration of watchdog timer Interrupt function I/O memory of watchdog timer Programming notes Oscillation Circuit Configuration of oscillation circuit OSC oscillation circuit OSC3 oscillation circuit Operating voltage Switching operating clock Clock frequency and instruction execution time I/O memory of oscillation circuit Programming notes Input Ports (KK3, KK3 and K2) Configuration of input ports Interrupt function Mask option I/O memory of input ports Programming notes SC6P366 TECHNICAL MANUAL EPSON i

8 CONTENTS 4.5 Output Ports (RR3, RR3 and R2R23) Configuration of output ports Mask option High impedance control Special output I/O memory of output ports Programming notes I/O Ports (PP3, PP3, P2P23, P3P33 and P4P43) Configuration of I/O ports Mask option I/O control registers and input/output mode Pull-up during input mode I/O memory of I/O ports Programming note LCD Driver (COMCOM3, SEGSEG3) Configuration of LCD driver Power supply for LCD driving Control of LCD display and drive waveform Segment option Mask option I/O memory of LCD driver Programming notes Clock Timer Configuration of clock timer Data reading and hold function Interrupt function I/O memory of clock timer Programming notes Programmable Timer Configuration of programmable timer Tow separate 8-bit timer (MODE6 = "") operation Setting of initial value and counting down Counter mode Setting of input clock in timer mode Interrupt function Setting of TOUT output Transfer rate setting for serial interface One channel 6-bit timer (MODE6 = "") operation Setting of initial value and counting down Counter mode Setting of input clock in timer mode Interrupt function Setting of TOUT output Transfer rate setting for serial interface I/O memory of programmable timer Programming notes Serial Interface (SIN, SOUT, SCLK, SRDY) Configuration of serial interface Mask option Master mode and slave mode of serial interface Data input/output and interrupt function I/O memory of serial interface Programming notes A/D Converter Characteristics and configuration of A/D converter Terminal configuration of A/D converter ii EPSON SC6P366 TECHNICAL MANUAL

9 CONTENTS 4..3 Mask option Control of A/D converter Interrupt function I/O memory of A/D converter Programming notes Buzzer Output Circuit Configuration of buzzer output circuit Mask option Control of buzzer output I/O memory of buzzer output circuit Programming note SVD (Supply Voltage Detection) Circuit Configuration of SVD circuit SVD operation I/O memory of SVD circuit Programming notes Interrupt and HALT Interrupt factor Interrupt mask Interrupt vector I/O memory of interrupt Programming notes... CHAPTER 5 PROM PROGRAMMING AND OPERATING MODE 5. Configuration of PROM Programmer Operating Mode Normal operation mode Serial programming mode Parallel programming mode... 4 CHAPTER 6 DIFFERENCES FROM MASK ROM MODELS 5 6. Differences from SC Terminal configuration Mask option Power supply Initial reset PROM, RAM I/O memory Oscillation circuit SVD circuit Differences from SC Terminal configuration Mask option Power supply Initial reset PROM, RAM I/O memory Oscillation circuit SVD circuit... 6 CHAPTER 7 SUMMARY OF NOTES 7 7. Notes for Current Consumption Summary of Notes by Function Precautions on Mounting SC6P366 TECHNICAL MANUAL EPSON iii

10 CONTENTS CHAPTER 8 BASIC EXTERNAL WIRING DIAGRAM 25 CHAPTER 9 ELECTRICAL CHARACTERISTICS Absolute Maximum Rating Recommended Operating Conditions DC Characteristics Analog Circuit Characteristics and Power Current Consumption Oscillation Characteristics Serial Interface AC Characteristics Timing Chart Characteristics Curves (reference value) CHAPTER PACKAGE 39. Plastic Package CHAPTER PAD LAYOUT 4. Diagram of Pad Layout Pad Coordinates... 4 APPENDIX A PROM PROGRAMMING 42 A. Outline of Writing Tools A.2 Serial Programming (SC88/SC63 Serial Connector) A.2. Serial programming environment (SC88/SC63 Serial Connector) A.2.2 System connection and setup for serial programming (SC88/SC63 Serial Connector) A.2.3 Serial programming procedure (SC88/SC63 Serial Connector) A.2.4 Connection diagram for serial programming (SC88/SC63 Serial Connector) A.3 Parallel Programming... 5 A.3. Parallel programming environment... 5 A.3.2 System connection and setup for parallel programming A.3.3 Parallel programming procedure A.4 Universal ROM Writer II (S5UC88W) Specifications A.4. Outline of Universal ROM Writer II specifications A.4.2 Detailed description of the Universal ROM Writer II commands A.4.3 List of commands A.4.4 Universal ROM Writer II error messages A.5 Flash EEPROM Programming Notes APPENDIX B S5UC63P MANUAL (PERIPHERAL CIRCUIT BOARD FOR SC6358/358/P366) 68 B. Names and Functions of Each Part B.2 Connecting to the Target System... 7 B.3 Usage Precautions B.3. Operational precautions B.3.2 Differences with the actual IC iv EPSON SC6P366 TECHNICAL MANUAL

11 CHAPTER OUTLINE CHAPTER : OUTLINE The SC6P366 is a microcomputer which has a high-performance 4-bit CPU SC63 as the core CPU, rewritable PROM, RAM, serial interface, watchdog timer, programmable timer, time base counter ( system), SVD circuit, a segment type LCD driver (32 segments 4 commons), A/D converter and a special input port that can implement key position discrimination function using with the A/D converter. The SC6P366 has a built-in large capacity PROM (6K 3 bits) and RAM (2K 4 bits) that are compatible with the SC63358 and SC6358, it can therefore be used for program development.. Features OSC oscillation circuit khz (Typ.) crystal oscillation circuit OSC3 oscillation circuit....8 MHz (Typ.) CR or 4 MHz (Max.) ceramic oscillation circuit ( ) Instruction set... Basic instruction: 46 types (4 instructions with all) Addressing mode: 8 types Instruction execution time... At khz operation: Min. 6 µsec At 4 MHz operation: Min..5 µsec PROM capacity... Code PROM: 6,384 words 3 bits Segment option PROM: 2,48 words 4 bits Programming method: Parallel or serial programming (exclusive PROM writer is used) Rewriting: times RAM capacity... Data memory: 2,48 words 4 bits Display memory: 32 words 4 bits Input port... 9 bits 8 bits (with pull-up resistors) bit (for key position sensing interrupt by A/D) Output port... 2 bits (2 special outputs are available 2) I/O port... 2 bits (4 serial inputs/outputs are available 2) (4 A/D inputs are available 2) Serial interface... port (8-bit clock synchronous system) LCD driver segments 4, 3 or 2 commons ( 2), /3 bias drive Time base counter... system (clock timer) Programmable timer... Built-in, 2 channels 8 bits or channel 6 bits ( 2), with event counter function Watchdog timer... Built-in A/D converter... 8-bit resolution Maximum error: ±3 LSB, A/D clock: OSC, OSC3 (2.7 V to 5.5 V) Buzzer output... Buzzer frequency: 2 khz or 4 khz ( 2), 2 Hz interval output ( 2) Supply voltage detection (SVD) circuit... 2 values, programmable (2.7 V, 2.8 V) External interrupt... Input port interrupt: 2 systems Key sensing interrupt: system Internal interrupt... Clock timer interrupt: 4 systems Programmable timer interrupt: 2 systems Serial interface interrupt: system A/D converter: system Power supply voltage V to 5.5 V Operating temperature range C to 7 C SC6P366 TECHNICAL MANUAL EPSON

12 CHAPTER : OUTLINE Current consumption (Typ.)... Single clock: During HALT (32 khz) 3. V (LCD power OFF) 2.5 µa 3. V (LCD power ON) 37 µa During operation (32 khz) 3. V (LCD power ON) 2 µa Twin clock: During operation (4 MHz) 3. V (LCD power ON) 8 µa Package... QFP5-pin (plastic) or chip : Can be selected with mask option 2: Can be selected with software.2 Block Diagram Code PROM 6,384 words 3 bits System Reset Control RESET SPRG RXD TXD SCLK CLKIN PROM Programmer Segment Option PROM 2,48 words 4 bits Core CPU SC63 Interrupt Generator RAM 2,48 words 4 bits Clock Timer OSC OSC2 OSC3 OSC4 COM3 SEG3 OSC LCD Driver 32 SEG 4 COM Programmable Timer/Counter Input Port KK3 KK3 K2 TEST VDD VC3 CACB VD VSS Power Controller A/D I/O Port AVDD AVSS AVREF PP3 PP3 P2P23 P3P33 P4P43 SVD Serial Interface BZ Buzzer Output Output Port RR3 RR3 R2R23 Fig..2. Block diagram 2 EPSON SC6P366 TECHNICAL MANUAL

13 SC6P366 TECHNICAL MANUAL EPSON 3 CHAPTER : OUTLINE.3 Pin Layout Diagram QFP5-pin INDEX SC6P366 No Pin name SC6P366 SEG7 SEG8 SEG9 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG2 SEG2 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG3 SEG3 SC63358 SEG7 SEG8 SEG9 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG2 SEG2 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG3 SEG3 No Pin name SC6P366 CLKIN SPRG COM COM COM2 COM3 CB CA VC3 VC2 VC VSS OSC OSC2 VD OSC3 OSC4 VDD RESET TEST AVREF AVDD AVSS RXD TXD SC63358 N.C. N.C. COM COM COM2 COM3 CB CA VC3 VC2 VC VSS OSC OSC2 VD OSC3 OSC4 VDD RESET TEST AVREF AVDD AVSS N.C. N.C. No Pin name SC6P366 SCLK P43 P42 P4 P4 P33 P32 P3 P3 P23 P22 P2 P2 P3 P2 P P P3 P2 P P R23 R22 R2 R2 SC63358 N.C. P43 P42 P4 P4 P33 P32 P3 P3 P23 P22 P2 P2 P3 P2 P P P3 P2 P P R23 R22 R2 R2 No Pin name SC6P366 R3 R2 R R R3 R2 R R BZ K K K2 K3 K K K2 K3 K2 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SC63358 R3 R2 R R R3 R2 R R BZ K K K2 K3 K K K2 K3 K2 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 N.C. : No Connection Fig..3. Pin layout diagram

14 CHAPTER : OUTLINE.4 Pin Description Table.4. Pin description Pin name VDD VSS VD VCVC3 CA, CB OSC OSC2 OSC3 OSC4 KK3 KK3 K2 PP3 PP3 P2P23 P3P33 P4P43 R R R2 R3 RR3 R2R23 COMCOM3 SEGSEG3 AVDD AVSS AVREF BZ RESET TEST RXD TXD SCLK CLKIN SPRG Pin No , , In/Out I O I O I I I I/O I/O I/O I/O I/O O O O O O O O O O I I I O I/O I I Function Power (+) supply pin Power () supply pin Oscillation system regulated voltage output pin LCD system power supply pin /3 bias LCD system boosting/reducing capacitor connecting pin Crystal oscillation input pin Crystal oscillation output pin Ceramic or CR oscillation input pin (selected by mask option) Ceramic or CR oscillation output pin (selected by mask option) Input port Input port Input port with control I/O port I/O port (switching to serial I/F input/output is possible by software) I/O port I/O port I/O port (can be used as A/D input) Output port Output port Output port (switching to TOUT output is possible by software) Output port (switching to FOUT output is possible by software) Output port Output port LCD common output pin (/4, /3, /2 duty can be selected by software) LCD segment output pin Power (+) supply pin for A/D converter Power () supply pin for A/D converter Reference voltage for A/D converter Buzzer output pin Initial reset input pin Testing input pin Serial data input pin for Flash programming Serial data output pin for Flash programming Serial clock input/output pin for Flash programming Clock input pin for Flash programming Control pin for Flash programming N.C. in SC63358 Refer to Chapter 5, "PROM Programmer and Operating Mode", for the Flash programming pins. 4 EPSON SC6P366 TECHNICAL MANUAL

15 CHAPTER : OUTLINE.5 Mask Option Mask options shown below are provided for the SC6P366. <SC6P366 mask options> () OSC3 oscillation circuit Either CR oscillation circuit or ceramic oscillation circuit can be selected as the OSC3 oscillation circuit. Refer to Section 4.3.3, "OSC3 oscillation circuit", for details. The other mask options provided for the SC63358/6358 are fixed as follows in the SC6P366, so they cannot be selected. OSC oscillation circuit... Crystal oscillation Multiple key input reset... Not used Time authorize for multiple key input... Not used Input port pull-up resistor... Available Output port output specifications... Complementary output I/O port output specifications... Complementary output I/O port pull-up resistor Px, P2x, P3x... Available P4x... Not available LCD drive bias... /3 bias Serial interface input/output polarity... Negative polarity Buzzer output specification... Negative polarity.6 Segment Option () LCD segment allocation Up to 28 bits of the display memory can be selected from the data memory addresses FH to FFH. The LCD driver has a segment decoder built-in, and the data bit (DD3) of the optional address in the display memory area (FHFFH) can be allocated to the optional segment. The segment option generator SOG63358, that has been prepared as a development software tool of the SC63358, is used for this selection. Refer to Section 4.7.4, "Segment option", for details. (2) LCD segment output specification It is possible to set the optional SEG terminal for DC output. Refer to Section 4.7.4, "Segment option", for details. (3) Segment option data Recommended LCD segment option data is include in the S5UC6P366Y package. Modifying the LCD segment opotion is done at the user's own risk. SC6P366 TECHNICAL MANUAL EPSON 5

16 CHAPTER 2: POWER SUPPLY AND INITIAL RESET CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2. Power Supply The SC6P366 operating power voltage is as follows: 2.7 V to 5.5 V The SC6P366 operates by applying a single power supply within the above range between VDD/AVDD and VSS/AVSS. The SC6P366 itself generates the voltage necessary for all the internal circuits by the built-in power supply circuits shown in Table 2... Table 2.. Power supply circuits Circuit Oscillation circuit Internal logic circuits LCD driver Oscillation system voltage regulator LCD system voltage circuit A/D converter Power supply circuit Oscillation system voltage regulator Supply voltage (VDD) LCD system voltage circuit Supply voltage (VDD) Supply voltage (VDD) Analog supply voltage (AVDD) and supply voltage (VDD) Output voltage VD VDD VCVC3 VDD VDD AVDD and VDD Note: Do not drive external loads with the output voltage from the internal power supply circuits. The internal LCD system voltage circuit (/3 bias) is always used in the SC6P366. See Chapter 9, "Electrical Characteristics", for voltage values and drive capability. AVDD VDD A/D converter Internal circuits External power supply + VD VC VC2 VC3 CA CB Oscillation system voltage regulator LCD system voltage circuit VD VCVC3 Oscillation circuit SVD circuit LCD driver OSC4 COM3 SEG3 VSS AVSS Fig. 2.. Configuration of power supply 6 EPSON SC6P366 TECHNICAL MANUAL

17 2.. Voltage <VD> for oscillation circuit and internal circuits CHAPTER 2: POWER SUPPLY AND INITIAL RESET VD is the operating voltage for the oscillation circuit, and is generated by the oscillation system voltage regulator for stabilizing oscillation. In the SC63358/6358, it is necessary to switch the VD voltage level according to the oscillation circuit and operating frequency by controlling the voltage regulator. In the SC6P366, the VD voltage level is fixed, so software control for switching the VD level does not affect the actual output voltage. However, when using the SC6P366 as a development tool for the SC63358/6358, the VD software control sequence must be implemented according to the model. Refer to Chapter 6, "Differences from Mask ROM Models", for details Voltage <VCVC3> for LCD driving VC to VC3 are the voltages for LCD drive, and are generated by the LCD system voltage circuit to stabilize the display quality. Since the minimum operating voltage of the SC6P366 is 2.7 V, the LCD system voltage circuit generates VC2 as the reference voltage, and generates two other voltages by boosting or reducing VC2 (VC = / 2 VC2, VC3 = 3/2 VC2). Refer to Chapter 9, "Electrical Characteristics", for voltage values of VC to VC Operating mode of power supply circuit The oscillation system voltage regulator and A/D converter power supply circuit operate in normal mode that uses VDD as the power source. In the SC63358/6358, a booster mode (VC2 mode) is provided in order to guarantee low-voltage operation, therefore it is necessary to switch the operating mode. Since the power supply voltage of the SC6P366 is 2.7 V or more, this switching is not necessary and the software control does not affect the operating mode. However, when using the SC6P366 as a development tool for the SC63358/6358, the operating mode control routine must be implemented according to the model. Refer to Chapter 6, "Differences from Mask ROM Models", for details. SC6P366 TECHNICAL MANUAL EPSON 7

18 CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset To initialize the SC6P366 circuits, initial reset must be executed. The SC6P366 supports an external initial reset using the reset (RESET) terminal. When the power is turned on, be sure to initialize using this reset function. It is not guaranteed that the circuits are initialized by only turning the power on. Figure 2.2. shows the configuration of the initial reset circuit. OSC OSC2 OSC oscillation circuit Divider 2 Hz RESET VDD R S Q Internal initial reset 2.2. Reset terminal (RESET) Fig Configuration of initial reset circuit Initial reset can be executed externally by setting the reset terminal to a low level (VSS). After that the initial reset is released by setting the reset terminal to a high level (VDD) and the CPU starts operation. The reset input signal is maintained by the RS latch and becomes the internal initial reset signal. The RS latch is designed to be released by a 2 Hz signal (high) that is divided by the OSC clock. Therefore in normal operation, a maximum of 25 msec (when fosc = khz) is needed until the internal initial reset is released after the reset terminal goes to high level. Be sure to maintain a reset input of. msec or more. However, when turning the power on, the reset terminal should be set at a low level as in the timing shown in Figure VDD 2.7 V 2. msec or more RESET Power on.5 VDD. VDD or less (low level) Fig Initial reset at power on The reset terminal should be set to. VDD or less (low level) until the supply voltage becomes 2.7 V or more. After that, a level of.5 VDD or less should be maintained more than 2. msec. In the SC6P366, a low level input to the reset terminal initializes some analog circuits as well as the internal logic. At this time, µa or more current is consumed as the bias current Internal register at initial resetting Initial reset initializes the CPU as shown in Table The registers and flags which are not initialized by initial reset should be initialized in the program if necessary. In particular, the stack pointers SP and SP2 must be set as a pair because all the interrupts including NMI are masked after initial reset until both the SP and SP2 stack pointers are set with software. When data is written to the EXT register, the E flag is set and the following instruction will be executed in the extended addressing mode. If an instruction which does not permit extended operation is used as the following instruction, the operation is not guaranteed. Therefore, do not write data to the EXT register for initialization only. Refer to the "SC63 Core CPU Manual" for extended addressing and usable instructions. 8 EPSON SC6P366 TECHNICAL MANUAL

19 CHAPTER 2: POWER SUPPLY AND INITIAL RESET Name Data register A Data register B Extension register EXT Index register X Index register Y Program counter Stack pointer SP Stack pointer SP2 Zero flag Carry flag Interrupt flag Extension flag Queue register Table Initial values CPU core Peripheral circuits Symbol Number of bits Setting value Name Number of bits Setting value A 4 Undefined RAM 4 Undefined B 4 Undefined Display memory 4 Undefined EXT 8 Undefined Other pheripheral circuits X 6 Undefined Y 6 Undefined See Section 4., "Memory Map". PC 6 H SP 8 Undefined SP2 8 Undefined Z Undefined C Undefined I E Q 6 Undefined Terminal settings at initial resetting The output port (R) terminals and I/O port (P) terminals are shared with special output terminals, input/ output terminals of the serial interface and input terminals of the A/D converter. These functions are selected by the software. At initial reset, these terminals are set to the general purpose output port terminals and I/O port terminals. Set them according to the system in the initial routine. In addition, take care of the initial status of output terminals when designing a system. Table shows the list of the shared terminal settings. Table List of shared terminal settings Terminal name R R R2 R3 RR3 R2R23 PP3 P P P2 P3 P2P23 P3P33 P4 P4 P42 P43 Terminal status at initial reset R (High output) R (High output) R2 (High output) R3 (High output) RR3 (High output) R2R23 (High output) PP3 (Input & Pull-up) P (Input & Pull-up) P (Input & Pull-up) P2 (Input & Pull-up) P3 (Input & Pull-up) P2P23 (Input & Pull-up) P3P33 (Input & Pull-up) P4 (Input & high impedance) P4 (Input & high impedance) P42 (Input & high impedance) P43 (Input & high impedance) Special output Serial I/F A/D TOUT FOUT Master Slave converter TOUT FOUT SIN(I) SIN(I) SOUT(O) SOUT(O) SCLK(O) SCLK(I) SRDY(O) AD(I) AD(I) AD2(I) AD3(I) For setting procedure of the functions, see explanations for each of the peripheral circuits. SC6P366 TECHNICAL MANUAL EPSON 9

20 CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.3 Test Terminal (TEST) This is the terminal used for the factory inspection of the IC. During normal operation, connect the TEST terminal to VDD. 2.4 Terminals for Flash EEPROM The SC6P366 has the following terminals used for writing data to the Flash EEPROM and for factory testing. SPRG: SCLK: RXD: TXD: CLKIN: Flash EEPROM programming control terminal Clock input/output terminal for Flash EEPROM serial programming Data input terminal for Flash EEPROM serial programming Data output terminal for Flash EEPROM serial programming Flash EEPROM write-control clock input terminal The above terminals should be set up according to the operating mode. Refer to Chapter 5, "PROM Programming and Operating Mode", for details. EPSON SC6P366 TECHNICAL MANUAL

21 CHAPTER 3: CPU, PROM, RAM CHAPTER 3 CPU, PROM, RAM 3. CPU The SC6P366 has a 4-bit core CPU SC63 built-in as its CPU part. Refer to the "SC63 Core CPU Manual" for the SC63. Note: The SLP instruction cannot be used because the SLEEP operation is not assumed in the SC6P Code PROM The built-in code PROM is a PROM for loading programs, and has a capacity of 6,384 steps 3 bits. The core CPU can linearly access the program space up to step FFFFH from step H, however, the program area of the SC6P366 is step H to step 3FFFH. The program start address after initial reset is assigned to step H. The non-maskable interrupt (NMI) vector and hardware interrupt vectors are allocated to step H and steps 2HEH, respectively. H 3FFFH 4H PROM SC6P366 program area SC63 core CPU program space H H 2H EH H Program area NMI vector Hardware interrupt vectors Program start address FFFFH area Program area 3 bits Fig Configuration of code PROM 3.3 RAM The RAM is a data memory for storing various kinds of data, and has a capacity of 2,48 words 4 bits. The RAM area is assigned to addresses H to 7FFH on the data memory map. Addresses H to FFH are 4-bit/6-bit data accessible areas and in other areas it is only possible to access 4-bit data. When programming, keep the following points in mind. () Part of the RAM area is used as a stack area for subroutine call and register evacuation, so pay attention not to overlap the data area and stack area. (2) The SC63 core CPU handles the stack using the stack pointer for 4-bit data (SP2) and the stack pointer for 6-bit data (SP). 6-bit data are accessed in stack handling by SP, therefore, this stack area should be allocated to the area where 4-bit/6-bit access is possible (H to FFH). The stack pointers SP and SP2 change cyclically within their respective range: the range of SP is H to 3FFH and the range of SP2 is H to FFH. Therefore, pay attention to the SP value because it may be set to FFH or less exceeding the 4-bit/6-bit accessible range in the SC6P366. Memory accesses except for stack operations by SP are 4-bit data access. After initial reset, all the interrupts including NMI are masked until both the stack pointers SP and SP2 are set by software. Further, if either SP or SP2 is re-set when both are set already, the interrupts including NMI are masked again until the other is re-set. Therefore, the settings of SP and SP2 must be done as a pair. SC6P366 TECHNICAL MANUAL EPSON

22 CHAPTER 3: CPU, PROM, RAM (3) Subroutine calls use 4 words (for PC evacuation) in the stack area for 6-bit data (SP). Interrupts use 4 words (for PC evacuation) in the stack area for 6-bit data (SP) and word (for F register evacuation) in the stack area for 4-bit data. H FFH H FFH 2H 4-bit access area (SP2 stack area) 4/6-bit access area (SP stack area) 4-bit access area (data area) 7FFH 4 bits Fig Configuration of data RAM 2 EPSON SC6P366 TECHNICAL MANUAL

23 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION The peripheral circuits of the SC6P366 (timer, A/D, I/O, etc.) are interfaced with the CPU in the memory mapped I/O method. Thus, all the peripheral circuits can be controlled by accessing the I/O memory on the memory map using the memory operation instructions. The following sections explain the detailed operation of each peripheral circuit. 4. Memory Map The SC6P366 data memory consists of 2,48-word RAM, 32-word display memory and 76-word peripheral I/O memory area. Figure 4.. shows the overall memory map of the SC6P366, and Tables 4..(a) (f) the peripheral circuits' (I/O space) memory maps. H 8H RAM area area FH F2H Display memory area area FH FFH FFH FFFFH I/O memory area FFFFH Fig. 4.. Memory map Peripheral I/O area Note: Memory is not implemented in unused areas within the memory map. Further, some non-implementation areas and unused (access prohibition) areas exist in the peripheral I/O area. If the program that accesses these areas is generated, its operation cannot be guaranteed. Refer to the I/O memory maps shown in Tables 4.. (a)(f) for the peripheral I/O area. SC6P366 TECHNICAL MANUAL EPSON 3

24 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) FF6H FOUTE FOFQ FOFQ R Table 4.. (a) I/O memory map (FFHFF28H) Address Register D3 D2 D D Name Init Comment FFH CLKCHG OSC3 OSC CPU clock switch CLKCHG OSCC VDC OSCC On Off OSC3 oscillation On/Off 3 2 R VDC (OSC3) (OSC) (Operating voltage switch) FFH VADSEL VDSEL DBON VADSEL (VC2) (VDD) (Power source selection for A/D converter) VDSEL (VC2) (VDD) (Power source selection for oscillation system voltage regulator) R 3 2 DBON (On) (Off) (Voltage doubler On/Off) FF4H SVDS3 SVD criteria voltage setting SVDS3 SVDS2 SVDS SVDS SVDS2 [SVDS3] Voltage(V) SVDS [SVDS3] SVDS Voltage(V) FF5H SVDDT SVDON R Normal SVD evaluation data On Off SVD circuit On/Off FF7H FF2H FF2H FF22H FF24H FF25H FF26H FF28H WDEN WDRST R W SIK3 SIK2 SIK SIK K3 K2 K K R KCP3 KCP2 KCP KCP SIK3 SIK2 SIK SIK K3 K2 K K R KCP3 KCP2 KCP KCP SIK2 R Remarks Initial value at initial reset 2 Not set in the circuit 3 Constantly "" when being read 3 3 SVDDT SVDON FOUTE 3 FOFQ FOFQ 3 3 WDEN WDRST 3 SIK3 SIK2 SIK SIK K3 K2 K K KCP3 KCP2 KCP KCP SIK3 SIK2 SIK SIK K3 K2 K K KCP3 KCP2 KCP KCP SIK Reset Enable Disable FOUT output enable Enable Reset Enable Enable Enable Enable High High High High Enable Enable Enable Enable High High High High Disable Invalid Disable Disable Disable Disable Disable Disable Disable Disable Enable Disable FOUT frequency selection Watchdog timer enable Watchdog timer reset (writing) KK3 interrupt selection register KK3 input port data KK3 input comparison register KK3 interrupt selection register KK3 input port data [FOFQ, ] Frequency fosc/64 KK3 input comparison register K2 interrupt selection register fosc/8 2 fosc 3 fosc3 4 EPSON SC6P366 TECHNICAL MANUAL

25 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Address FF29H FF2AH FF2BH FF3H FF3H FF32H FF33H FF34H FF35H FF4H FF4H FF42H FF44H Register R3HIZ R2HIZ RHIZ RHIZ Table 4.. (b) I/O memory map (FF29HFF44H) D3 D2 D D Name Init K R 3 2 K2 2 High KCP R 3 2 KCP2 SENON R 3 2 SENON On Off R3HIZ High-Z Output R3 R2 R R RHIZ R R3 R2 R R R2HIZ R IOC3 IOC2 IOC IOC PUL3 PUL2 PUL PUL P3 P2 P P R23 R22 R2 R2 IOC3 IOC2 IOC IOC R2HIZ RHIZ RHIZ R3 R2 R R RHIZ R3 R2 R R R2HIZ R23 R22 R2 R2 IOC3 IOC2 IOC IOC PUL3 PUL2 PUL PUL P3 P2 P P IOC3 IOC2 IOC IOC High-Z High-Z High-Z High High High High Output Output Output High-Z Output High High High High Output Output Output Output On On On On High High High High Output High-Z Output High High High High Output Output Output Input Input Input Input Off Off Off Off Input Input Input Input K2 input port data K2 input comparison register Key sense On/Off control Comment R3 output high impedance control (FOUTE=) FOUT output high impedance control (FOUTE=) R2 output high impedance control (PTOUT=) TOUT output high impedance control (PTOUT=) R output high impedance control R output high impedance control R3 output port data (FOUTE=) Fix at "" when FOUT is used R2 output port data (PTOUT=) Fix at "" when TOUT is used R output port data R output port data R output high impedance control RR3 output port data R2 output high impedance control R2R23 output port data PP3 I/O control register PP3 pull-up control register PP3 I/O port data P3 I/O control register functions as a general-purpose register when SIF (slave) is selected P2 I/O control register (ESIF=) functions as a general-purpose register when SIF is selected P I/O control register (ESIF=) functions as a general-purpose register when SIF is selected P I/O control register (ESIF=) functions as a general-purpose register when SIF is selected SC6P366 TECHNICAL MANUAL EPSON 5

26 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Address FF45H FF46H FF48H FF49H FF4AH FF4CH FF4DH FF4EH FF5H FF5H Register Table 4.. (c) I/O memory map (FF45HFF5H) D3 D2 D D Name Init PUL3 On Off PUL3 PUL2 PUL PUL P3 P2 P P IOC23 IOC22 IOC2 IOC2 PUL23 PUL22 PUL2 PUL2 P23 P22 P2 P2 IOC33 IOC32 IOC3 IOC3 PUL33 PUL32 PUL3 PUL3 P33 P32 P3 P3 IOC43 IOC42 IOC4 IOC4 PUL43 PUL42 PUL4 PUL4 PUL2 PUL PUL P3 P2 P P IOC23 IOC22 IOC2 IOC2 PUL23 PUL22 PUL2 PUL2 P23 P22 P2 P2 IOC33 IOC32 IOC3 IOC3 PUL33 PUL32 PUL3 PUL3 P33 P32 P3 P3 IOC43 IOC42 IOC4 IOC4 PUL43 PUL42 PUL4 PUL On On On High High High High Output Output Output Output On On On On High High High High Output Output Output Output On On On On High High High High Output Output Output Output Off Off Off Input Input Input Input Off Off Off Off Input Input Input Input Off Off Off Off Input Input Input Input Comment P3 pull-up control register functions as a general-purpose register when SIF (slave) is selected P2 pull-up control register (ESIF=) functions as a general-purpose register when SIF (master) is selected SCLK (I) pull-up control register when SIF (slave) is selected P pull-up control register (ESIF=) functions as a general-purpose register when SIF is selected P pull-up control register (ESIF=) SIN pull-up control register when SIF is selected P3 I/O port data functions as a general-purpose register when SIF (slave) is selected P2 I/O port data (ESIF=) functions as a general-purpose register when SIF is selected P I/O port data (ESIF=) functions as a general-purpose register when SIF is selected P I/O port data (ESIF=) functions as a general-purpose register when SIF is selected P2P23 I/O control register P2P23 pull-up control register P2P23 I/O port data P3P33 I/O control register P3P33 pull-up control register P3P33 I/O port data P43 I/O control register (PAD3=) functions as a general-purpose register when A/D is enabled P42 I/O control register (PAD2=) functions as a general-purpose register when A/D is enabled P4 I/O control register (PAD=) functions as a general-purpose register when A/D is enabled P4 I/O control register (PAD=) functions as a general-purpose register when A/D is enabled General-purpose register 6 EPSON SC6P366 TECHNICAL MANUAL

27 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Address FF52H FF6H FF6H FF64H FF7H FF7H FF72H FF73H FF78H FF79H FF7AH FFCH FFCH Register Table 4.. (d) I/O memory map (FF52HFFCH) D3 D2 D D Name Init P43 2 High P43 P42 P4 P4 LDUTY LDUTY VCCHG R LPWR ALOFF ALON STCD R ENON BZFQ BZON ESOUT SCTRG ESIF R SD3 SD2 SD SD SD7 SD6 SD5 SD4 R TMRST TMRUN R W TM3 TM2 TM TM TM7 TM6 TM5 TM4 CHSEL R SDP SCPS SCS SCS MODE6 EVCNT FCSEL PLPOL PTOUT CKSEL CKSEL P42 P4 P4 LDUTY LDUTY VCCHG LPWR 3 ALOFF ALON STCD 3 ENON BZFQ BZON 3 ESOUT SCTRG ESIF SDP SCPS SCS SCS SD3 SD2 SD SD SD7 SD6 SD5 SD4 3 3 TMRST 3 TMRUN TM3 TM2 TM TM TM7 TM6 TM5 TM4 MODEL6 EVCNT FCSEL PLPOL CHSEL PTOUT CKSEL CKSEL On Off Reset High High High All Off All On Static On 2 khz On Enable Trigger Run SIF High High High High High High High High Off 4 khz Off Comment P43 I/O port data (PAD3=) functions as a general-purpose register when A/D is enabled P42 I/O port data (PAD2=) functions as a general-purpose register when A/D is enabled P4 I/O port data (PAD=) functions as a general-purpose register when A/D is enabled P4 I/O port data (PAD=) functions as a general-purpose register when A/D is enabled LCD drive duty switch [LDUTY, ] Duty General-purpose register (reserved register) LCD power On/Off Normal LCD all OFF control Normal LCD all ON control Dynamic Common output signal control 2 Hz intervai On/Off Buzzer frequency selection Buzzer output On/Off MSB first LSB first Serial I/F data input/output permutation Serial I/F clock phase selection Serial I/F clock mode selection MSB Reset Run 6 bit Event ct. With NR Timer On OSC3 OSC3 Disable Invalid Stop I/O Invalid Stop 8 bit 2 Timer No NR Timer Off OSC OSC /4 SOUT enable/disable control Serial I/F clock trigger (writing) Serial I/F clock status (reading) Serial I/F enable (P port function selection) Serial I/F transmit/receive data (low-order 4 bits) LSB MSB Serial I/F transmit/receive data (high-order 4 bits) LSB Clock timer reset (writing) Clock timer Run/Stop Clock timer data (6 Hz) Clock timer data (32 Hz) Clock timer data (64 Hz) Clock timer data (28 Hz) Clock timer data ( Hz) Clock timer data (2 Hz) Clock timer data (4 Hz) Clock timer data (8 Hz) TOUT output channel selection TOUT output control Prescaler source clock selection Prescaler source clock selection [SCS, ] Clock [SCS, ] Clock /3 Slave 2 OSC/2 8 bit 2 or 6 bit timer mode selection Timer counter mode selection Timer function selection (for event counter mode) Timer pulse polarity selection (for event counter mode) 2, 3 /2 PT 3 OSC SC6P366 TECHNICAL MANUAL EPSON 7

28 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Address FFC2H FFC3H FFC4H FFC5H FFC6H FFC7H FFC8H FFC9H FFCAH FFCBH FFDH FFDH FFD2H FFD3H Table 4.. (e) I/O memory map (FFC2HFFD3H) Register D3 D2 D D Name Init PTPS PTPS PTPS PTRST PTRUN PTPS PTRST 3 2 Reset Invalid W PTRUN Run Stop PTPS PTPS PTPS PTRST PTRUN PTPS PTRST 3 W PTRUN RLD3 RLD3 RLD2 RLD RLD RLD2 RLD RLD RLD7 RLD7 RLD6 RLD5 RLD4 RLD6 RLD5 RLD4 RLD3 RLD3 RLD2 RLD RLD RLD2 RLD RLD RLD7 RLD7 RLD6 RLD5 RLD4 RLD6 RLD5 RLD4 PTD3 PTD3 PTD2 PTD PTD PTD2 PTD R PTD PTD7 PTD7 PTD6 PTD5 PTD4 PTD6 PTD5 R PTD4 PTD3 PTD3 PTD2 PTD PTD PTD2 PTD R PTD PTD7 PTD7 PTD6 PTD5 PTD4 PTD6 PTD5 R PTD4 ADRUN ADRUN ADCLK CHS CHS ADCLK CHS W CHS PAD3 PAD3 PAD2 PAD PAD PAD2 PAD PAD ADDR3 ADDR3 ADDR2 ADDR ADDR ADDR2 ADDR R ADDR ADDR7 ADDR8 ADDR6 ADDR5 ADDR4 ADDR6 ADDR5 R ADDR Reset Run Start OSC3 Enable Enable Enable Enable Invalid Stop Invalid OSC Disable Disable Disable Disable Prescaler division ratio selection Timer reset (reload) Timer Run/Stop Comment [PTPS, ] Division ratio Prescaler [PTPS, ] division ratio selection Division ratio Timer reset (reload) Timer Run/Stop MSB / /4 2 /32 Programmable timer reload data (low-order 4 bits) LSB MSB Programmable timer reload data (high-order 4 bits) LSB MSB Programmable timer reload data (low-order 4 bits) LSB MSB Programmable timer reload data (high-order 4 bits) LSB MSB Programmable timer data (low-order 4 bits) LSB MSB Programmable timer data (high-order 4 bits) LSB MSB Programmable timer data (low-order 4 bits) LSB MSB Programmable timer data (high-order 4 bits) LSB A/D Run/Off control A/D input clock selection A/D input channel selection [CHS, ] Input channel / P43 input channel enable/disable control P42 input channel enable/disable control P4 input channel enable/disable control P4 input channel enable/disable control A/D converted data (DD3) A/D converted data (D4D7) P4 /4 P4 2 /32 2 P42 3 /256 3 /256 3 P43 8 EPSON SC6P366 TECHNICAL MANUAL

29 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Address FFE2H FFE3H FFE4H FFE5H FFE6H FFE7H FFF2H FFF3H FFF4H FFF5H FFF6H FFF7H D3 EIPT EIPT R EIT3 EIT2 EIT EIT Table 4.. (f) I/O memory map (FFE2HFFF7H) Register D2 D D Name Init 2 2 Enable Mask Enable Mask EISIF R EIAD R EIK R EIK2 EIK R IPT IPT R IT3 IT2 IT IT ISIF R IAD R IK R IK2 IK R 3 3 EIPT EIPT EISIF EIK 3 3 EIK2 EIK EIT3 EIT2 EIT EIT EIAD 3 3 IPT IPT ISIF IK 3 3 IK2 IK IT3 IT2 IT IT IAD Enable Mask Enable Mask 2 2 Enable Enable Enable Enable Enable Enable Mask Mask Mask Mask Mask Mask Enable Mask (R) Yes (W) Reset (R) Yes (W) Reset (R) Yes (W) Reset (R) Yes (W) Reset (R) Yes (W) Reset (R) Yes (W) Reset (R) No (W) Invalid (R) No (W) Invalid (R) No (W) Invalid (R) No (W) Invalid (R) No (W) Invalid (R) No (W) Invalid Comment Interrupt mask register (Programmable timer ) Interrupt mask register (Programmable timer ) Interrupt mask register (Serial I/F) Interrupt mask register (KK3) Interrupt mask register (K2) Interrupt mask register (KK3) Interrupt mask register (Clock timer Hz) Interrupt mask register (Clock timer 2 Hz) Interrupt mask register (Clock timer 8 Hz) Interrupt mask register (Clock timer 6 Hz) Interrupt mask register (A/D converter) Interrupt factor flag (Programmable timer ) Interrupt factor flag (Programmable timer ) Interrupt factor flag (Serial I/F) Interrupt factor flag (KK3) Interrupt factor flag (K2) Interrupt factor flag (KK3) Interrupt factor flag (Clock timer Hz) Interrupt factor flag (Clock timer 2 Hz) Interrupt factor flag (Clock timer 8 Hz) Interrupt factor flag (Clock timer 6 Hz) Interrupt factor flag (A/D converter) SC6P366 TECHNICAL MANUAL EPSON 9

30 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer) 4.2 Watchdog Timer 4.2. Configuration of watchdog timer The SC6P366 has a built-in watchdog timer that operates with a 256 Hz divided clock from the OSC as the source clock. The watchdog timer starts operating after initial reset, however, it can be stopped by the software. The watchdog timer must be reset cyclically by the software while it operates. If the watchdog timer is not reset in at least 34 seconds, it generates a non-maskable interrupt (NMI) to the CPU. Figure is the block diagram of the watchdog timer. OSC dividing signal 256 Hz Watchdog timer enable signal Watchdog timer reset signal Watchdog timer Non-maskable interrupt (NMI) Fig Watchdog timer block diagram The watchdog timer contains a -bit binary counter, and generates the non-maskable interrupt when the last stage of the counter (.25 Hz) overflows. Watchdog timer reset processing in the program's main routine enables detection of program overrun, such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is incorporated where periodic processing takes place, just as for the timer interrupt routine. The watchdog timer operates in the HALT mode. If a HALT status continues for 34 seconds, the nonmaskable interrupt releases the HALT status Interrupt function If the watchdog timer is not reset periodically, the non-maskable interrupt (NMI) is generated to the core CPU. Since this interrupt cannot be masked, it is accepted even in the interrupt disable status (I flag = ""). However, it is not accepted when the CPU is in the interrupt mask state until SP and SP2 are set as a pair, such as after initial reset or during re-setting the stack pointer. The interrupt vector of NMI is assigned to H in the program memory. 2 EPSON SC6P366 TECHNICAL MANUAL

31 4.2.3 I/O memory of watchdog timer CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer) Table shows the I/O address and control bits for the watchdog timer. Address FF7H D3 Table Control bits of watchdog timer Register D2 D D Name Init 3 2 WDEN WDRST 3 2 WDEN Enable Disable R W WDRST 3 Reset Reset Invalid * Initial value at initial reset *2 Not set in the circuit *3 Constantly "" when being read Watchdog timer enable Watchdog timer reset (writing) WDEN: Watchdog timer enable register (FF7H D) Selects whether the watchdog timer is used (enabled) or not (disabled). When "" is written: Enabled When "" is written: Disabled Reading: Valid Comment When "" is written to the WDEN register, the watchdog timer starts count operation. When "" is written, the watchdog timer does not count and does not generate the interrupt (NMI). At initial reset, this register is set to "". WDRST: Watchdog timer reset (FF7H D) Resets the watchdog timer. When "" is written: Watchdog timer is reset When "" is written: No operation Reading: Always "" When "" is written to WDRST, the watchdog timer is reset and restarts immediately after that. When "" is written, no operation results. This bit is dedicated for writing, and is always "" for reading Programming notes () When the watchdog timer is being used, the software must reset it within 3-second cycles. (2) Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled state (not used) before generating an interrupt (NMI) if it is not used. SC6P366 TECHNICAL MANUAL EPSON 2

32 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.3 Oscillation Circuit 4.3. Configuration of oscillation circuit The SC6P366 has two oscillation circuits (OSC and OSC3). OSC is a crystal oscillation circuit that supplies the operating clock to the CPU and peripheral circuits. OSC3 is either a CR or a ceramic oscillation circuit. When processing with the SC6P366 requires high-speed operation, the CPU operating clock can be switched from OSC to OSC3 by the software. Figure is the block diagram of this oscillation system. OSC oscillation circuit Divider To peripheral circuits OSC3 oscillation circuit Clock switch To CPU CPU clock selection signal OSC oscillation circuit Oscillation circuit control signal Fig Oscillation system block diagram The OSC oscillation circuit generates the main clock for the CPU and the peripheral circuits. The oscillator type is a crystal oscillation circuit and the oscillation frequency is khz (Typ.). Figure is the block diagram of the OSC oscillation circuit. CGX OSC To CPU (and peripheral circuits) X'tal OSC2 FX R RDX C DX VSS VSS Fig OSC oscillation circuit As shown in Figure , the crystal oscillation circuit can be configured simply by connecting the crystal oscillator (X'tal) of khz (Typ.) between the OSC and OSC2 terminals and the trimmer capacitor (CGX) between the OSC and VSS terminals. 22 EPSON SC6P366 TECHNICAL MANUAL

33 4.3.3 OSC3 oscillation circuit CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) The SC6P366 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock for high speed operation and the source clock for peripheral circuits needing a high speed clock (programmable timer, FOUT output). The mask option enables selection of either the CR (Typ..8 MHz) or ceramic (Max. 4 MHz ceramic oscillation) oscillation circuit. When CR oscillation is selected, only a resistance is required as an external element. When ceramic oscillation is selected, a ceramic oscillator and two capacitors (gate and drain capacitance) are required. Figure is the block diagram of the OSC3 oscillation circuit. C CR RCR OSC3 OSC4 To CPU (and some peripheral circuits) Oscillation circuit control signal (a) CR oscillation circuit CGC CDC Ceramic OSC3 OSC4 FC R RDC To CPU (and some peripheral circuits) Oscillation circuit control signal VSS (b) Ceramic oscillation circuit Fig OSC3 oscillation circuit As shown in Figure , the CR oscillation circuit can be configured simply by connecting the resistor RCR between the OSC3 and OSC4 terminals when CR oscillation is selected. See Chapter 9, "Electrical Characteristics" for resistance value of RCR. When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the ceramic oscillator (Max. 4 MHz) between the OSC3 and OSC4 terminals, capacitor CGC between the OSC3 and OSC4 terminals, and capacitor CDC between the OSC4 and VSS terminals. For both CGC and CDC, connect capacitors that are about pf. To reduce current consumption of the OSC3 oscillation circuit, oscillation can be stopped by the software (OSCC register). SC6P366 TECHNICAL MANUAL EPSON 23