CMOS 8-BIT SINGLE CHIP MICROCOMPUTER S1C8F360

Transcription

1 CMOS 8-BIT SINGLE CHIP MICROCOMPUTER SC8F36 Technical Manual

2 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of Economy, Trade and Industry or other approval from another government agency. Windows 2 and Windows XP are registered trademarks of Microsoft Corporation, U.S.A. PC/AT and IBM are registered trademarks of International Business Machines Corporation, U.S.A. All other product names mentioned herein are trademarks and/or registered trademarks of their respective owners. This product uses SuperFlash technology licensed from Silicon Storage Technology, Inc. SEIKO EPSON CORPORATION 27, All rights reserved.

3 SC8F36 Technical Manual Revision History Code No. Page Chapter/Section Contents INTRODUCTION The description was modified. The SC8F36 has a built-in... SC88832 and SC Features Table.. was modified. 3.3 Pin Layout Diagram The QFP8-76pin package was deleted. 4 The PFBGA-8pin package was added. 5.4 Pin Description Table.4. was modified. The description was modified. Notes: The pin assignment... with the SC883xx/888xx Switching the CPU clocks The description was added. Notes: If the HALT instruction... OSC3 high-speed clock Programming notes The description was added. (6) If the HALT instruction... OSC3 high-speed clock Configuration of output ports The description was added. Note: If an output terminal (including... for more information Configuration of I/O ports The description was added. Note: If an output of this IC is used... for more information Configuration of programmable timer Count operation and setting basic mode The description was added. Note: If the TOUT terminal is used... for more information. Fig and were modified. The description was added. Note: The programmable timer... OSC3 (high-speed clock) Configuration of sound generator The description was added. Note: If the BZ terminal is used... for more information Terminal configuration of A/D converter The description was added. If the A/D converter is not used... the input voltage level Terminal Configuration The description was modified. The SC8F36 has terminals... or PFBGA-8pin package. Table 7.. was modified Supply voltage range Table was modified List of Differences between The table was modified. SC8F36 and Supported Models Precautions on Mounting The description was added. <Output Terminals> When an output terminal is... consumption as possible. The description was modified. <Precautions for Visible Radiation (when bare chip is mounted)> Visible radiation causes... before the product is shipped. 79. Plastic Package The QFP8-76pin package was deleted. 8 The PFBGA-8pin package was added. 83~93 Sections A. to A.2 Descriptions were modified with USB-Serial On Board Writer (S5UC88W4) added. 22, 24, Sections A.3 to A.5 The HEX file names were changed. 27, 29, 24, B.3 Connecting to the Target System Table B.3.2 was modified. 227 B.5.2 Differences from actual IC The description was added. Oscillation circuit When using an external clock... with VSS as GND.

4

5 Configuration of product number Devices S C 884 F A Packing specifications : Besides tape & reel A : TCP BL 2 directions B : Tape & reel BACK C : TCP BR 2 directions D : TCP BT 2 directions E : TCP BD 2 directions F : Tape & reel FRONT G : TCP BT 4 directions H : TCP BD 4 directions J : TCP SL 2 directions K : TCP SR 2 directions L : Tape & reel LEFT M : TCP ST 2 directions N : TCP SD 2 directions P : TCP ST 4 directions Q : TCP SD 4 directions R : Tape & reel RIGHT 99 : Specs not fixed Specification Package D: die form; F: QFP, B: BGA Model number Model name C: microcomputer, digital products Product classification S: semiconductor Development tools S5U C D Packing specifications : standard packing Version : Version Tool type Hx : ICE Ex : EVA board Px : Peripheral board Wx : Flash ROM writer for the microcomputer Xx : ROM writer peripheral board Cx : C compiler package Ax : Assembler package Dx : Utility tool by the model Qx : Soft simulator Corresponding model number 88348: for SC88348 Tool classification C: microcomputer use Product classification S5U: development tool for semiconductor products

6

7 Preface CONTENTS The SC8F36 is a development tool/preprocessor IC for the SC88862, SC88832 and SC8837. The ROM has been changed to a Flash EEPROM (described as PROM in this manual) and a -bit A/D converter with four analog inputs is included. Almost all other circuits are compatible with the SC883xx/888xx mask ROM models. Furthermore, an exclusive PROM writer should be used for PROM programming. Refer to Appendix A, "PROM Programming", for how to program the PROM. Refer to the following manuals in addition to this manual. (Note that the pin assignment of the SC8F36 is different from that of the SC883xx/888xx.) SC8837 Technical Manual SC88832/88862 Technical Manual Contents INTRODUCTION.... Features....2 Block Diagram Pin Layout Diagram Pin Description Mask Option POWER SUPPLY Operating Voltage Internal Power Supply Circuit Heavy Load Protection Mode CPU AND BUS CONFIGURATION CPU Internal Memory PROM RAM I/O memory Display memory Exception Processing Vectors CC (Customized Condition Flag) Chip Mode MCU mode and MPU mode Bus mode External Bus Data bus Address bus Read (RD)/write (WR) signals Chip enable (CE) signal WAIT control Bus authority release state INITIAL RESET Initial Reset Factor Initial Settings After Initial Reset...8 SC8F36 TECHNICAL MANUAL EPSON i

8 CONTENTS 5 PERIPHERAL CIRCUITS AND THEIR OPERATION I/O Memory Map System Controller and Bus Control Bus mode settings Address decoder (CE output) settings WAIT state settings Setting the bus authority release request signal Stack page setting Control of system controller Programming notes Watchdog Timer Configuration of watchdog timer Interrupt function Control of watchdog timer Programming notes Oscillation Circuits and Operating Mode Configuration of oscillation circuits Mask option OSC oscillation circuit OSC3 oscillation circuit Operating mode Switching the CPU clocks Control of oscillation circuit and operating mode Programming notes Input Ports (K ports) Configuration of input ports Mask option Interrupt function and input comparison register Control of input ports Programming note Output Ports (R ports) Configuration of output ports Mask option High impedance control DC output Special output Control of output ports Programming notes I/O Ports (P ports) Configuration of I/O ports Mask option I/O control registers and I/O mode Control of I/O ports Programming notes Serial Interface Configuration of serial interface Mask option Transfer modes Clock source Transmit-receive control Operation of clock synchronous transfer Operation of asynchronous transfer Interrupt function Control of serial interface Programming notes ii EPSON SC8F36 TECHNICAL MANUAL

9 CONTENTS 5.9 Clock Timer Configuration of clock timer Interrupt function Control of clock timer Programming notes Stopwatch Timer Configuration of stopwatch timer Count up pattern Interrupt function Control of stopwatch timer Programming notes Programmable Timer Configuration of programmable timer Count operation and setting basic mode Setting of input clock Timer mode Event counter mode Pulse width measurement timer mode Interrupt function Setting of TOUT output Transmission rate setting of serial interface Control of programmable timer Programming notes LCD Controller Configuration of LCD controller Mask option Switching drive duty LCD power supply LCD driver Display memory Display control CL and FR outputs Control of LCD controller Programming notes Sound Generator Configuration of sound generator Control of buzzer output Setting of buzzer frequency and sound level Digital envelope One-shot output Control of sound generator Programming notes Analog Comparator Configuration of analog comparator Mask option Analog comparator operation Control of analog comparator Programming notes A/D Converter Characteristics and configuration of A/D converter Terminal configuration of A/D converter Mask option A/D conversion Interrupt function Control of A/D converter Programming notes SC8F36 TECHNICAL MANUAL EPSON iii

10 CONTENTS 5.6 Supply Voltage Detection (SVD) Circuit Configuration of SVD circuit Mask option Operation of SVD circuit Control of SVD circuit Programming notes Interrupt and Standby Status Interrupt generation conditions Interrupt factor flag Interrupt enable register Interrupt priority register and interrupt priority level Exception processing vectors Control of interrupt Programming notes PROM PROGRAMMER AND OPERATING MODES Configuration of PROM Programmer Operating Modes Normal operation mode PROM serial programming mode PROM parallel programming mode DIFFERENCES FROM SC883xx/SC888xx Terminal Configuration Mask Option Power Supply Supply voltage range LCD drive voltage (VCVC5) Initial Reset ROM RAM Oscillation Circuit LCD Controller A/D Converter SVD Circuit List of Differences between SC8F36 and Supported Models SUMMARY OF NOTES Notes Related to the PROM Notes on Differences form the SC883xx/SC888xx Notes for Low Current Consumption Precautions on Mounting BASIC EXTERNAL WIRING DIAGRAM ELECTRICAL CHARACTERISTICS Absolute Maximum Rating Recommended Operating Conditions DC Characteristics Analog Circuit Characteristics Power Current Consumption...64 iv EPSON SC8F36 TECHNICAL MANUAL

11 CONTENTS.6 AC Characteristics Oscillation Characteristics Characteristics Curves (reference value)...72 PACKAGE Plastic Package PAD LAYOUT Diagram of Pad Layout Pad Coordinates...82 APPENDIX A PROM PROGRAMMING A. Outline of Writing Tools...83 A.2 Serial Programming (On Board Writer)...84 A.2. Serial programming environment (On Board Writer) A.2.2 System connection for serial programming (On Board Writer) A.2.3 Serial programming procedure (On Board Writer) A.2.4 Connection diagram for serial programming (when On Board Writer is used)... 9 A.2.5 On Board Writer Control Software A.2.5. Starting up A Setup A Operating method A.2.6 List of commands... 2 A.2.7 List of error messages... 2 A.3 Serial Programming (Universal Writer)...22 A.3. Serial programming environment (Universal Writer) A.3.2 System connection and setup for serial programming (Universal Writer) A.3.3 Serial programming procedure (Universal Writer) A.3.4 Connection diagram for serial programming (when Universal Writer is used) A.4 Parallel Programming (Universal Writer)...27 A.4. Parallel programming environment (Universal Writer) A.4.2 System connection and setup for parallel programming (Universal Writer) A.4.3 Parallel programming procedure (Universal Writer) A.5 Universal Writer Specifications...2 A.5. Outline of Universal Writer specifications... 2 A.5.2 Universal Writer commands A.5.3 List of Universal Writer commands A.5.4 Universal Writer error messages A.6 Flash EEPROM Programming Notes...29 APPENDIX B S5UC88P&S5UC8886P2 MANUAL (Peripheral Circuit Board for SC8F36) B. Names and Functions of Each Part...22 B.2 Installation B.2. Installing S5UC8886P2 to S5UC88P B.2.2 Installing into the ICE (S5UC88H5) B.3 Connecting to the Target System B.4 Downloading Circuit Data to the S5UC88P B.5 Precautions B.5. Precaution for operation B.5.2 Differences from actual IC B.6 Product Specifications B.6. S5UC88P specifications B.6.2 S5UC8886P2 specifications SC8F36 TECHNICAL MANUAL EPSON v

12

13 INTRODUCTION INTRODUCTION The SC8F36 is a CMOS 8-bit Flash built-in microcomputer for mass production. It is composed of the core CPU (MODEL3), rewritable PROM (Flash EEPROM), RAM, dot-matrix type LCD driver, three types of timers and asynchronous/ clock synchronous selectable serial interface. The SC8F36 has a built-in large-capacity PROM (6K 8 bits) and a RAM (2K 8 bits), and is upper compatible with the SC88862, SC88832 and SC8837. The SC8F36 can be used for developing programs.. Features Table.. lists the features of the SC8F36. Table.. Main features Core CPU OSC oscillation circuit OSC3 oscillation circuit Instruction set SC88 (MODEL3) CMOS 8-bit core CPU Crystal oscillation circuit khz (Typ.) Crystal oscillation circuit/ceramic oscillation circuit/cr oscillation circuit 8.2 MHz (Max.) 68 types (usable for multiplication and division instructions) Min. instruction execution time.244 µsec/8.2 MHz (2 clock) Internal PROM capacity 6K bytes (supports serial- and parallel-programming method using the exclusive PROM writer) Internal RAM capacity 2K bytes/ram 3,26 bits/display memory Bus line Address bus: 9 bits (also usable as a general output port when not used as a bus) Data bus: 8 bits (also usable as a general I/O port when not used as a bus) CE signal: WR signal: RD signal: 4 bits bit bit (also usable as a general output port when not used as a bus) Input port Output port I/O port Serial interface Timer bits (2 bits can be set for event counter external clock input and bus request signal input terminal) 9 bits (6 bits can be set for buzzer output, LCD control, FOUT, TOUT and bus acknowledge signal output terminal) 8 bits (4 bits each can be set for serial interface input/output and analog comparator/ad input) ch (optional clock synchronous system or asynchronous system) Programmable timer (8 bits): 2ch (ch can be set as a an event counter or 2ch as a 6 bits programmable timer for ch) Clock timer (8 bits): Stopwatch timer (8 bits): ch ch LCD driver Dot matrix type (compatible with 5 8 or 5 5 fonts) 5 segments 32 common (/5 bias) 67 segments 6 common (/5 bias) 67 segments 8 common (/5 bias) Expandable external LCD driver Built-in LCD power supply circuit (booster type, 5 potentials) Sound generator Watchdog timer Analog comparator A/D converter Supply voltage detection Envelope function, equipped with volume control Built-in 2ch built-in (not available if A/D converter is used) Resolution: bits, input: 4ch, Maximum error: ±3 LSB (not available if analog comparator is used) Can detect up to 6 different voltage levels (SVD) circuit Interrupt Supply voltage Current consumption External interrupt: Internal interrupt: Normal mode: Low power mode: High speed mode: HALT mode: Input interrupt Timer interrupt Serial interface interrupt A/D converter interrupt 2.4 V5.5 V (Max. 4.2 MHz) 2. V3.5 V (Max. 5 khz) 3.5 V5.5 V (Max. 8.2 MHz) 2 µa (Typ./normal mode) 2 systems (3 types) 3 systems (9 types) system (3 types) system ( type) VD = 2.2 V VD =.85 V VD = 3. V Run (32 khz): 2 µa (Typ./normal mode) Run (4 MHz):.5 ma (Typ./normal mode) Supply form QFP2-76pin, PFBGA-8pin or chip * The number of bits cited for output ports and I/O ports does not include those shared with the bus. SC8F36 TECHNICAL MANUAL EPSON

14 INTRODUCTION.2 Block Diagram Core CPU SC88 OSC, 2 OSC3, 4 Oscillator Interrupt Controller MCU/MPU BREQ (K) BACK (R5) System Controller Input Port KK7 K (EVIN) K (BREQ) RESET TEST EVIN (K) VDD VSS VD VDF Reset/Test Watchdog Timer Programmable Timer /Event Counter Clock Timer Stopwatch Timer I/O Port Serial Interface Analog Comparator /AD Converter External Memory Interface Sound Generator Output Port P (SIN) P (SOUT) P2 (SCLK) P3 (SRDY) P4 (CMPP/AD4) P5 (CMPM/AD5) P6 (CMPP/AD6) P7 (CMPM/AD7) PP7 (DD7) RR7, RR7, R2R22 (AA7, A8A5, A6A8) R23, R24 (RD, WR) R3R33 (CECE3) R25, R26 (CL, FR/TOUT) R27 (TOUT) R34 (FOUT) R35R37 R5 (BZ) R5 (BACK/BZ) VOSC VCVC5 CACE AVDD Power Generator LCD Driver SEGSEG5 COM6COM3 (SEG66SEG5) COMCOM5 AVSS AVREF PROM 6K byte * Supply Voltage Detector RAM 2K byte PROM Programmer SPRG RXD TXD SCLK CLKW VEPEXT The PROM block indicated with a dotted line differ from the SC88xxx. Fig..2. SC8F36 block diagram 2 EPSON SC8F36 TECHNICAL MANUAL

15 SC8F36 TECHNICAL MANUAL EPSON 3 INTRODUCTION.3 Pin Layout Diagram QFP2-76pin INDEX Pin No. Pin name Pin No. Pin name SEG46 SEG47 SEG48 SEG49 SEG5 COM3/SEG5 COM3/SEG52 COM29/SEG53 COM28/SEG54 COM27/SEG55 COM26/SEG56 COM25/SEG57 COM24/SEG58 COM23/SEG59 COM22/SEG6 COM2/SEG6 COM2/SEG62 COM9/SEG63 COM8/SEG64 COM7/SEG65 COM6/SEG66 VDF SPRG CLKW VEPEXT RXD SCLK TXD CE CD CC CB CA VC5 VC4 VC3 VC2 VC OSC3 OSC4 VD VDD VSS VOSC SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG2 SEG2 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG3 SEG3 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG4 SEG4 SEG42 SEG43 SEG44 SEG45 Pin No. Pin name OSC OSC2 TEST RESET MCU/MPU K/BREQ K/EVIN K7 K6 K5 K4 K3 K2 K K P7/CMPM/AD7 P6/CMPP/AD6 P5/CMPM/AD5 P4/CMPP/AD4 P3/SRDY P2/SCLK P/SOUT P/SIN AVDD AVSS AVREF VDD P7/D7 P6/D6 P5/D5 P4/D4 P3/D3 P2/D2 P/D P/D R/A R/A R2/A2 R3/A3 R4/A4 R5/A5 R6/A6 R7/A7 R/A8 Pin No. Pin name R/A9 R2/A R3/A R4/A2 R5/A3 R6/A4 R7/A5 R2/A6 R2/A7 R22/A8 R23/RD R24/WR R25/CL R26/FR/TOUT R27/TOUT R3/CE R3/CE R32/CE2 R33/CE3 R34/FOUT R35 R36 R37 VSS R5/BZ R5/BACK/BZ COM COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM COM COM2 COM3 COM4 COM5 SEG SEG Fig..3. SC8F36 pin layout (QFP2-76pin)

16 INTRODUCTION PFBGA-8pin A Corner Top View Bottom View A Corner A B C D E F G H J K L M N P Index A B C D E F G H J J L M N P A B R A R7 R4 R P4 AVREF P2 P7 K4 K RESET OSC2 OSC A7 A4 A D4 SCLK CMPM EVIN AD7 N.C. R R5 R P3 VDD P K3 K7 MCU/MPU TEST VOSC A8 A5 A D3 SOUT P6 CMPP AD6 VSS 4 N.C. A B C R2 A R3 A R6 A6 R2 A2 P2 D2 P7 D7 P SIN P5 CMPM AD5 K2 K6 K BREQ VDD VD OSC4 C D R4 A2 R5 A3 R6 A4 R3 A3 P D P6 D6 AVDD P4 CMPP AD4 K K5 OSC3 VC VC2 VC3 D E R7 A5 R2 A6 R2 A7 R22 A8 P D P5 D5 AVSS P3 SRDY K VC4 VC5 CA CB CC E F R23 RD R24 WR R25 CL R26 FR TOUT R27 TOUT CD CE TXD SCLK RXD F G R3 CE R3 CE R32 CE2 R33 CE3 R34 FOUT VEPEXT CLKW SPRG VDF COM6 SEG66 G H R35 R36 R37 VSS R5 BZ Top View COM7 SEG65 COM8 SEG64 COM9 SEG63 COM2 SEG62 COM2 SEG6 H J R5 BACK BZ COM COM COM2 COM3 COM22 SEG6 COM23 SEG59 COM24 SEG58 COM25 SEG57 COM26 SEG56 J K COM4 COM5 COM6 COM7 COM8 SEG6 SEG2 SEG26 SEG3 SEG36 COM27 SEG55 COM28 SEG54 COM29 SEG53 COM3 SEG52 K L COM9 COM COM COM2 SEG SEG5 SEG2 SEG25 SEG3 SEG35 SEG4 COM3 SEG585 SEG5 SEG49 L COM3 M COM4 COM5 SEG7 SEG SEG4 SEG9 SEG24 SEG29 SEG34 SEG39 SEG43 SEG48 SEG47 M N SEG SEG SEG4 SEG6 SEG9 SEG3 SEG8 SEG23 SEG28 SEG33 SEG38 SEG42 SEG45 SEG46 N P SEG2 SEG3 SEG5 SEG8 SEG2 SEG7 SEG22 SEG27 SEG32 SEG37 SEG4 SEG44 N.C. N.C Fig..3.2 SC8F36 pin layout (PFBGA-8pin) P 4 EPSON SC8F36 TECHNICAL MANUAL

17 INTRODUCTION.4 Pin Description Table.4. SC8F36 pin description Pin name Pin No. QFP2-76 PFBGA-8 In/Out Function VDD VSS VD VDF 86, 5 87, B6, C2 B4, H4 C3 G3 VOSC VCVC5 CACE OSC OSC2 OSC3 OSC4 MCU/MPU KK7 K/EVIN K/BREQ RR7/AA7 RR7/A8A5 R2R22/A6A8 R23/RD R24/WR R25/CL R26/FR/TOUT* R27/TOUT R3R33/CECE3 R34/FOUT R35R37 R5/BZ R5/BACK/BZ* PP7/DD7 P/SIN P/SOUT P2/SCLK P3/SRDY P4/CMPP/AD4 P5/CMPM/AD5 P6/CMPP/AD6 P7/CMPM/AD7 COMCOM5 COM6COM3 /SEG66SEG5 SEGSEG5 RESET TEST AVDD AVSS AVREF TXD RXD SCLK CLKW SPRG VEPEXT COMCOM5: , B3 D2, D3, D4, E, E E2, E3, E4, F, F A3 A2 D C4 B E9, D9, C9, B9, A9, D, C, B A C A4, B4, C4, D4, A3, B3, C3, A2 B2, B, C, C2, D, D2, D3, E E2, E3, E4 F F2 F3 F4 F5 G, G2, G3, G4 G5 H, H2, H3 H5 J D5, C5, B5, A5, E6, D6, C6 C7 B7 A7 E8 D8 C8 B8 A8 2 3 A B2 D7 E7 A6 F2 F4 F3 G G2 G I O I O I I I I O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O I I O I I/O I I Power supply (+) terminal Power supply (GND) terminal Internal logic system voltage regulator output terminal Internal logic and PROM system voltage regulator output terminal (VDF = VD when normal operation mode) Oscillation system voltage regulator output terminal LCD drive voltage output terminals Booster capacitor connection terminals for LCD OSC crystal oscillation input terminal OSC crystal oscillation output terminal OSC3 crystal/ceramic or CR oscillation input terminal OSC3 crystal/ceramic or CR oscillation output terminal Terminal for setting MCU or MPU modes Input terminals (KK7) Input terminal (K) or event counter external clock input terminal (EVIN) Input terminal (K) or bus request signal input terminal (BREQ) Output terminals (RR7) or address bus (AA7) Output terminals (RR7) or address bus (A8A5) Output terminals (R2R22) or address bus (A6A8) Output terminal (R23) or read signal output terminal (RD) Output terminal (R24) or write signal output terminal (WR) Output terminal (R25) or LCD synchronous signal output terminal (CL) Output terminal (R26) or LCD frame signal output terminal (FR) TOUT is an optional output for the SC888xx. Output terminal (R27) or programmable timer underflow signal output terminal (TOUT) Output terminals (R3R33) or chip enable output terminals (CECE3) Output terminal (R34) or clock output terminal (FOUT) Output terminals (R35R37) Output terminal (R5) or buzzer output terminal (BZ) Output terminal (R5) or bus acknowledge signal output terminal (BACK) BZ is an optional output for the SC888xx. I/O terminals (PP7) or data bus (DD7) I/O terminal (P) or serial I/F data input terminal (SIN) I/O terminal (P) or serial I/F data output terminal (SOUT) I/O terminal (P2) or serial I/F clock I/O terminal (SCLK) I/O terminal (P3) or serial I/F ready signal output terminal (SRDY) I/O terminal (P4), analog comparator non-inverted input terminal or A/D converter input terminal I/O terminal (P5), analog comparator inverted input terminal or A/D converter input terminal I/O terminal (P6), analog comparator non-inverted input terminal or A/D converter input terminal I/O terminal (P7), analog comparator inverted input terminal or A/D converter input terminal LCD common output terminals LCD common output terminals (when /32 duty is selected) or LCD segment output terminal (when /6 duty is selected) LCD segment output terminals Initial reset input terminal Test input terminal Analog system power supply (+) terminal Analog system power supply () terminal Analog system reference voltage terminal Serial data output terminal for Flash programming Serial data input terminal for Flash programming Serial clock I/O terminal for Flash programming Clock input terminal for Flash programming Flash programming control input terminal Flash test terminal (high-voltage circuit monitor terminal) J2, J3, J4, J5, K, K2, K3, K4, K5, L, L2, L3, L4, M, M2, M3 2 COM6/SEG66COM3/SEG5: G4, H, H, H2, H3, H4, J, J, J2, J3, J4, K, K2, K3, K4, L2 3 SEGSEG5: N, N2, P2, P3, N3, P4, N4, M4, P5, N5, M5, L5, P6, N6, M6, L6, K6, P7, N7, M7, L7, K7, P8, N8, M8, L8, K8, P9, N9, M9, L9, K9, P, N, M, L, K, P, N, M, L, P2, N2, M2, P3, N3, N4, M4, M3, L4, L3 Notes: The pin assignment of the SC8F36 (QFP2-76pin, PFBGA-8pin) is incompatible with the SC883xx/888xx. " " indicates that the pin function of the SC888xx differs from that of the SC883xx. SC8F36 TECHNICAL MANUAL EPSON 5

18 INTRODUCTION.5 Mask Option In the SC8F36, two mask-option sets are available. Table.5. SC8F36 mask option list Mask option OSC oscillation circuit OSC3 oscillation circuit Multiple key entry reset SVD reset MPU initial bus mode Input port K pull-up resistor K K2 K3 K4 K5 K6 K7 K K RESET MCU/MPU I/O port P pull-up resistor P P2 P3 P4 P5 P6 P7 P P P2 P3 P4 P5 P6 P7 Output port R output R specification R2 R3 R4 R5 R6 R7 R R R2 R3 R4 R5 R6 R7 LCD drive duty LCD power supply R26 port function R5 port function Set SC8F36D4 * SC8F36F43 *2 For SC883xx/SC888xx Set 2 SC8F36D5 * SC8F36F532 *2 Crystal ( khz) Crystal ( khz) CR Crystal/ceramic Not used Not used Not used Not used Expanded 52K max. Expanded 52K max. With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Software selection Software selection Software selection Software selection R26/FR R26/FR R5 R5 : Product number for bare chip 2: Product number for QFP2-76pin package 6 EPSON SC8F36 TECHNICAL MANUAL

19 2 POWER SUPPLY In this section, we will explain the operating voltage and the configuration of the internal power supply circuit of the SC8F Operating Voltage The SC8F36 operating power voltage is as follows: Normal mode: 2.4 V to 5.5 V Low power mode: 2. V to 3.5 V High speed mode: 3.5 V to 5.5 V 2.2 Internal Power Supply Circuit The SC8F36 incorporates the power supply circuit shown in Figure When voltage within the range described above is supplied to VDD (+) and VSS (GND), all the voltages needed for the internal circuit are generated internally in the IC. Roughly speaking, the power supply circuit is divided into three sections. The internal logic voltage regulator generates the operating voltage <VD> for driving the internal logic circuits and the OSC3 oscillation circuit. The VD voltage can be selected from the following three types:.85 V for low-power mode, 2.2 V for normal mode and 3. V for high-speed mode. It should be selected by a program to switch according to the supply voltage and oscillation frequency. External power supply VDD AVDD VD VDF Internal logic system voltage regulator VDD VD 2 POWER SUPPLY See Section 5.4, "Oscillation Circuits and Operating Mode", for the switching of operating mode. The oscillation system voltage regulator generates the operating voltage <VOSC> for the OSC oscillation circuit. The LCD system power supply circuit generates the drive voltage for the LCD. Drive voltage has five potentials VCVC5 for /5 bias: VC and VC2 are generated by the LCD voltage regulator, and are boosted to generate VC3VC5. See Chapter, "ELECTRICAL CHARACTERIS- TICS" for the voltage values. In the SC8F36, the LCD drive voltage is supplied to the built-in LCD driver which drives the LCD panel connected to the SEG and COM terminals. Note: It is necessary to connect a load resistance between terminals VSSVC. Internal voltage setting circuit OSC3 oscillation circuit Internal circuit PROM block OSC3, OSC4 VOSC Oscillation system voltage regulator VOSC OSC oscillation circuit OSC, OSC2 VC VC2 LCD system voltage regulator VC, VC2 VC3 VC4 VC5 CA CB CC CD CE LCD system voltage booster VC3VC5 LCD driver COMCOM5 COM6COM3/SEG66SEG5 SEGSEG5 AVSS A/D converter VSS Fig Configuration of power supply circuit SC8F36 TECHNICAL MANUAL EPSON 7

20 2 POWER SUPPLY 2.3 Heavy Load Protection Mode The SC8F36 has a heavy load protection function for stable operation even when the supply voltage fluctuates by driving a heavy load. The IC enters heavy load protection mode when the peripheral circuits are in the following status: () The OSC3 oscillation circuit is switched ON (OSCC = "" and not in SLEEP) (2) The buzzer output is switched ON (BZON = "" or BZSHT = "") SLEEP status OSCC BZON Heavy load protection mode BZSHT Fig Configuration of heavy load protection mode control circuit For details of the OSC3 oscillation circuit and buzzer output, see "5.4 Oscillation Circuits and Operating Mode" and "5.3 Sound Generator", respectively. 8 EPSON SC8F36 TECHNICAL MANUAL

21 3 CPU AND BUS CONFIGURATION 3 CPU AND BUS CONFIGURATION In this section, we will explain the CPU, operating mode and bus configuration. 3. CPU The SC8F36 utilize the SC88 8-bit core CPU whose register configuration, command set, etc. are virtually identical to other units in the family of processors incorporating the SC88. See the "SC88 Core CPU Manual" for the SC88. Specifically, the SC8F36 employ the Model 3 SC88 CPU which has a maximum address space of 52K bytes Internal Memory The SC8F36 is equipped with internal PROM (Flash EEPROM) and RAM as shown in Figure Small scale applications can be handled by one chip. It is also possible to utilize internal memory in combination with external memory. Furthermore, internal PROM can be disconnected from the bus and the resulting space released for external applications PROM FFFFH FFH FD42H F8H F7FFH FH EFFFH H I/O memory Display memory RAM (2K bytes) PROM (6K bytes) Fig Internal memory map The SC8F36 has a built-in 6K-byte Flash EPROM. The PROM is allocated to H EFFFH. The PROM areas shown above can be released to external memory depending on the setting of the MCU/MPU terminal. (See "3.5 Chip Mode".) RAM The internal RAM capacity is 2K bytes and is allocated to FHF7FFH. Even when external memory which overlaps the internal RAM area is expanded, the RAM area is not released to external memory. Access to this area is via internal RAM I/O memory A memory mapped I/O method is employed in the SC8F36 for interfacing with internal peripheral circuit. Peripheral circuit control bits and data register are arranged in data memory space. Control and data exchange are conducted via normal memory access. I/O memory is arranged in page : FFHFFFFH area. See Section 5., "I/O Memory Map", for details of the I/O memory. Even when external memory which overlaps the I/O memory area is expanded, the I/O memory area is not released to external memory. Access to this area is via I/O memory Display memory The SC8F36 is equipped with an internal display memory which stores a display data for LCD driver. Display memory is arranged in page : FxH Fx42H (x = 8DH) in the data memory area. See Section 5.2, "LCD Controller", for details of the display memory. Like the I/O memory, display memory cannot be released to external memory. 3.3 Exception Processing Vectors H25H in the program area of the SC8F36 is assigned as exception processing vectors. Furthermore, from 28H to FFH, software interrupt vectors are assignable to any two bytes which begin with an even address. Table 3.3. lists the vector addresses and the exception processing factors to which they correspond. SC8F36 TECHNICAL MANUAL EPSON 9

22 3 CPU AND BUS CONFIGURATION Table 3.3. Exception processing vector table Vector address Exception processing factor Priority H Reset High 2H Zero division 4H Watchdog timer (NMI) 6H Programmable timer interrupt 8H Programmable timer interrupt AH K, K input interrupt CH K4K7 input interrupt EH KK3 input interrupt H Serial I/F error interrupt 2H Serial I/F receiving complete interrupt 4H Serial I/F transmitting complete interrupt 6H Stopwatch timer Hz interrupt 8H Stopwatch timer Hz interrupt AH Stopwatch timer Hz interrupt CH Clock timer 32 Hz interrupt EH Clock timer 8 Hz interrupt 2H Clock timer 2 Hz interrupt 22H Clock timer Hz interrupt 24H A/D converter interrupt Low 26H System reserved (cannot be used) No 28H priority : Software interrupt rating FEH For each vector address and the address after it, the start address of the exception processing routine is written into the subordinate and super ordinate sequence. When an exception processing factor is generated, the exception processing routine is executed starting from the recorded address. When multiple exception processing factors are generated at the same time, execution starts with the highest priority item. The priority sequence shown in Table 3.3. assumes that the interrupt priority levels are all the same. The interrupt priority levels can be set by software in each system. (See Section 5.7 "Interrupt and Standby Status".) Note: For exception processing other than reset, SC (system condition flag) and PC (program counter) are evacuated to the stack and branches to the exception processing routines. Consequently, when returning to the main routine from exception processing routines, please use the RETE instruction. See the "SC88 Core CPU Manual" for information on CPU operations when an exception processing factor is generated. 3.4 CC (Customized Condition Flag) The SC8F36 does not use the customized condition flag (CC) in the core CPU. Accordingly, it cannot be used as a branching condition for the conditional branching instruction (JRS, CARS). 3.5 Chip Mode 3.5. MCU mode and MPU mode The chip operating mode can be set to one of two settings using the MCU/MPU terminal. The MCU/ MPU terminal has a built-in pull-up resistor. MCU mode...set the MCU/MPU terminal to HIGH Switch to this setting when using internal PROM. With respect to areas other than internal memory, external memory can even be expanded. See Section 3.5.2, "Bus mode", for the memory map. In the MCU mode, during initial reset, only systems in internal memory are activated. Internal PROM is normally fixed as the top portion of the program memory from the common area (logical space H7FFFH). Exception processing vectors are assigned in internal PROM. Furthermore, the application initialization routines that start with reset exception processing must likewise be written to internal PROM. Since bus and other settings which correlate with external expanded memory can be executed in software, this processing is executed in the initialization routine written to internal PROM. Once these bus mode settings are made, external memory can be accessed. When accessing internal memory in this mode, the chip enable (CE) and read (RD)/write (WR) signals are not output to external memory, and the data bus (DD7) goes into high impedance status (pull-up status with the "pull-up resistors for PP7. Consequently, in cases where addresses overlap in external and internal memory, the areas in external memory will be unavailable. MPU mode...set the MCU/MPU terminal to LOW Internal PROM area is released to an external device source. Internal PROM then becomes unusable and when this area is accessed, chip enable (CE) and read (RD)/write (WR) signals are output to external memory and the data bus (DD7) become active. These signals are not output to an external source when other areas of internal memory are accessed. When employing this mode, the exception processing vectors and initialization routine must be assigned within the common area (H7FFFH). Note: Setting of MCU/MPU terminal is latched at the rising edge of a reset signal input from the RESET terminal. Therefore, if the setting is to be changed, the RESET terminal must be set to LOW level once again. EPSON SC8F36 TECHNICAL MANUAL

23 3 CPU AND BUS CONFIGURATION Bus mode In order to set bus specifications to match the configuration of external expanded memory, four different bus modes described below are selectable in software. Single chip mode - MCU mode - FFFFH I/O memory FFH FD42H Display memory F8H F7FFH Internal RAM FH EFFFH H Internal PROM Fig Memory map for the single chip mode The single chip mode setting applies when the SC8F36 is used as a single chip microcomputer without external expanded memory. Since this mode employs internal PROM, the system can only be operated in the MCU mode discussed in Section In the MPU mode, the system cannot be set to the single chip mode. Since there is no need for an external bus line in this mode, terminals normally set for bus use can be used as general purpose output ports or I/O ports. Accordingly, the output ports are in a 34-bit configuration in the SC8F36 and the I/O ports are in a 6-bit configuration. CPU operation in this mode is equivalent to the SC88 core CPU Model 3 minimum mode. Addresses assigned to internal memory within physical space H to FFFFH are only effective as a target for accessing. Expanded 64K mode (MPU mode) The expanded 64K mode setting applies when the SC8F36 is used with 64K bytes or less of external expanded memory. This mode is only usable on the MPU mode setting. When the SC8F36 is started in the MPU mode, the expanded 64K mode is set after an initial reset. Since the internal PROM area is released in the MPU mode, external memory in this model can be assigned to the area from H to EFFFH. The area from FH to FFFFH is assigned to internal memory (RAM, etc.) and cannot be used to access an external device. This mode setting is suitable for small- to midscale systems. The address range of the chip enable (CE) signal, adapted to memory chips with a capacity of from 8 to 64K bytes, can be selected in software to any one of four settings. See Section 3.6.4, "Chip enable (CE) signal", for the CE signal. CPU operation in this mode is equivalent to the SC88 core CPU Model 3 minimum mode. The area within physical space H to FFFFH is only effective as a target for accessing. - MPU mode - FFFFH Internal memory FH EFFFH External memory area H See Figure 3.2. for the internal memory Fig Memory map for the expanded 64K mode (MPU mode) Expanded 52K minimum mode The expanded 52K minimum mode setting applies when the SC8F36 is used with over 64K bytes and less than 52K bytes 4 of external expanded memory. This mode is usable regardless of the MCU/MPU mode setting. Because internal PROM is being used in the MCU mode, external memory in this model can be assigned to the area from 8H to 27FFFFH. Since the internal PROM area is released in the MPU mode, external memory in this model can be assigned to the area from H to FFFFFH. SC8F36 TECHNICAL MANUAL EPSON

24 3 CPU AND BUS CONFIGURATION However, the area from FH to FFFFH is assigned to internal memory and cannot be used to access an external device. CPU operation in this mode is equivalent to the SC88 core CPU Model3 minimum mode. The area within physical space H to FFFFFH in the MPU mode or physical space 8H to 27FFFFH + internal memory in the MCU mode is effective as a target for accessing. Furthermore, since program memory expansion is limited to less than 64K bytes configured with the common area (H to 7FFFH) and one optional bank area (internal PROM + 32K in the MCU mode), this mode is suitable for smallto mid-scale program memory and large-scale data memory systems. The address range of chip enable (CE) signals in this mode is fixed at 52K bytes. - MCU mode - - MPU mode - 27FFFFH FFFFFH : External memory area External memory area Because internal PROM is being used in the MCU mode, external memory in this model can be assigned to the area from 8H to 27FFFFH. Since the internal PROM area is released in the MPU mode, external memory in this model can be assigned to the area from H to FFFFFH. The area from FH to FFFFH is assigned to internal memory and cannot be used to access an external device. CPU operation in this mode is equivalent to the SC88 core CPU Model 3 maximum mode, the area within physical space H to FFFFFH in the MPU mode or physical space 8H to 27FFFFH + internal memory in the MCU mode is effective as a target for accessing. In the above mentioned physical space, since program memory and data memory can be secured with an optional (maximum 52K bytes 4 program + data) size, this mode is suitable for systems with large-scale program and data capacity. The address range of chip enable (CE) signals in this mode is fixed at 52K bytes. - MCU mode - - MPU mode - 27FFFFH FFFFFH 8H 7FFFFH H FFFFH Unused area Internal memory : External memory area External memory area Internal memory External memory area 8H 7FFFFH H FFFFH Unused area Internal memory H See Figure 3.2. for the internal memory Fig Memory map for the expanded 52K minimum mode Internal memory External memory area Expanded 52K maximum mode The expanded 52K maximum mode setting applies when the SC8F36 is used with over 64K bytes and less than 52K bytes 4 of external expanded memory. This mode is usable regardless of the MCU/MPU mode setting. H See Figure 3.2. for the internal memory Fig Memory map for the expanded 52K maximum mode There is an explanation on how all these settings are actually made in "5.2 System Controller and Bus Control" of this Manual. 2 EPSON SC8F36 TECHNICAL MANUAL

25 3 CPU AND BUS CONFIGURATION 3.6 External Bus The SC8F36 has bus terminals that can address a maximum of 52K 4 bytes and memory (and other) devices can be externally expanded according to the range of each bus mode described in the previous section. SC8F36 BREQ BACK RD WR CE CE CE2 CE3 External device Address bus (AA8) Data bus (DD7) External device Fig External bus lines External device External device Below is an explanation of external bus terminals. For information on control methods, see Section 5.2, "System Controller and Bus Control" Data bus The SC8F36 possesses an 8-bit external data bus (DD7). The terminals and I/O circuits of data bus DD7 are shared with I/O ports PP7, switching between these functions being determined by the bus mode setting. In the single chip mode, the 8-bit terminals are all set as I/O ports PP7 and in the other expanded modes, they are set as data bus (DD7). When set as data bus, the data register and I/O control register of each I/O port are detached from the I/O circuits and usable as a general purpose data register with read/write capabilities. Each data bus line has a built-in pull-up resistor that goes ON in input mode. (The same holds true when the terminals are used as I/O ports.) Bus mode Single chip I/O port P P P2 P3 P4 P5 P6 P7 Data bus D D D2 D3 D4 D5 D6 D7 Bus mode 64K 52K (min.) 52K (max.) Fig Correspondence between data bus and I/O ports Address bus The SC8F36 possesses a 9-bit external address bus AA8. The terminals and output circuits of address bus AA8 are shared with output ports RR7 (=AA7), RR7 (=A8A5) and R2 R22 (=A6A8), switching between these functions being determined by the bus mode setting. In the single chip mode, the 9-bit terminals are all set as output ports RR7, RR7 and R2R22. In the expanded 64K mode, 6 of the 9-bit terminals, AA5, are set as the address bus, while the remaining 3 bits, A6A8, are set as output ports R2R22. In the expanded 52K minimum and maximum modes, all of the 9-bit terminals are set as the address bus (AA8). When set as an address bus, the data register and high impedance control register of each output port are detached from the output circuit and used as a general purpose data register with read/write capabilities. Bus mode Single chip 64K Output port R R R2 R3 R4 R5 R6 R7 R R R2 R3 R4 R5 R6 R7 R2 R2 R22 Fig Correspondence between address bus and output ports Address bus A A A2 A3 A4 A5 A6 A7 A8 A9 A A A2 A3 A4 A5 A6 A7 A8 64K Read (RD)/write (WR) signals The output terminals and output circuits for the read (RD)/write (WR) signals directed to external devices are shared respectively with output ports R23 and R24, switching between these functions being determined by the bus mode setting. In the single chip mode, both of these terminals are set as output port terminals and in the other Bus mode 52K (min.) 52K (max.) expanded modes, they are set as read (RD)/write (WR) signal output terminals. When set as read (RD)/write (WR) signal output terminal, the data register and high impedance control register for each output port (R23, R24) are detached from the output circuit and is usable as a general purpose data register with read/write capabilities. SC8F36 TECHNICAL MANUAL EPSON 3

26 3 CPU AND BUS CONFIGURATION These two signals are only output when the memory area of the external device is being accessed. They are not output when internal memory is accessed. See Section 3.6.5, "WAIT control", for the output timing of the signal. Bus mode Single chip Output port R23 R24 RD/WR signal RD WR Bus mode 64K 52K (min.) 52K (max.) Fig Correspondence between read (RD)/write (WR) signal and output ports Chip enable (CE) signal The SC8F36 is equipped with address decoders which can output four different chip enable (CE) signals. Consequently, four devices equipped with a chip enable (CE) or chip select (CS) terminal can be directly connected without setting the address decoder to an external device. The four chip enable (CECE3) signal output terminals and output circuits are shared with output ports R3R33 and in modes other than the single chip mode, the selection of chip enable (CE) or output port can be set in software for each of the four bits. When set for chip enable (CE) output, the data register and high impedance control register for each output port are detached from the output circuit and is usable as general purpose data register with read/write capabilities. In the single chip mode, these terminals are set as output ports R3R33. Bus mode Single chip Output port R3 R3 R32 R33 CE signal CE CE CE2 CE3 Bus mode 64K 52K (min.) 52K (max.) Fig Correspondence between CE signals and output ports The address range assigned to the four chip enable (CE) signals is determined by the bus mode setting. In the expanded 64K mode, the four different address ranges which match the amount of memory in use can be selected in software. Table shows the address ranges which are assigned to the chip enable (CE) signal in each mode. When accessing the internal memory area, the CE signal is not output. Care should be taken here because the address range for these portions of memory involves irregular settings. The arrangement of memory space for external devices does not necessarily have to be continuous from a subordinate address and any of the chip enable signals can be used to assign areas in memory. Each of these signals is only output when the memory area of the external device is being accessed. They are not output when internal memory is accessed. Note: The CE signals will be inactive status when the chip enters the standby mode (HALT mode or SLEEP mode). See Section 3.6.5, "WAIT control", for the output timing of signal. Table CECE3 address settings () Expanded 64K mode (MPU mode only) CE signal Address range (selected in software) 8K bytes 6K bytes 32K bytes 64K bytes CE CE CE2 CE3 HFFFH 2H3FFFH 4H5FFFH 6H7FFFH H3FFFH 4H7FFFH 8HBFFFH CHEFFFH H7FFFH 8HEFFFH HEFFFH (2) Expanded 52K minimum/maximum modes CE signal MCU mode CE 2H27FFFFH CE 8HFFFFFH CE2 H7FFFFH CE3 8HFFFFFH Address range MPU mode HEFFFH, H7FFFFH 8HFFFFFH H7FFFFH 8HFFFFFH 4 EPSON SC8F36 TECHNICAL MANUAL

27 3 CPU AND BUS CONFIGURATION WAIT control In order to insure accessing of external low speed devices during high speed operations, the SC8F36 is equipped with a WAIT function which prolongs access time. (See the "SC88 Core CPU Manual" for details of the WAIT function.) The WAIT state numbers to be inserted can be selected in software from a series of 8 as shown in Table Table Selectable WAIT state numbers Selection No Insert states * One state is a /2 cycle of the clock in length. The WAIT states set in software are inserted between bus cycle states T3T4. Note, however, that WAIT states cannot be inserted when an internal register and internal memory are being accessed and when operating with the OSC oscillation circuit (see "5.4 Oscillation Circuits and Operating Mode"). Consequently, WAIT state settings are meaningless in the single chip mode. Figure shows the memory read/write timing charts. CLK T T2 T3 T4 T T2 T3 T4 AA8 Address Address CE CE WR RD DD7 Read data Write data Read cycle () No WAIT Write cycle WAIT (4 states inserted) WAIT (4 states inserted) CLK T T2 T3 Tw Tw2 Tw Tw2 T4 T T2 T3 Tw Tw2 Tw Tw2 T4 AA8 CE Address Address CE WR RD DD7 Read data Write data Read cycle (2) WAIT state insertion Fig Memory read/write cycle Write cycle SC8F36 TECHNICAL MANUAL EPSON 5

28 3 CPU AND BUS CONFIGURATION Bus authority release state The SC8F36 is equipped with a bus authority release function on request from an external device so that DMA (Direct Memory Access) transfer can be conducted between external devices. The internal memory cannot be accessed by this function. There are two terminals used for this function: the bus authority release request signal (BREQ) input terminal and the bus authority release acknowledge signal (BACK) output terminal. The BREQ input terminal is shared with input port terminal K and the BACK output terminal with output port terminal R5, use with setting to BREQ/BACK terminals done in software. In the single chip mode, or when using a system which does not require bus authority release, set respective terminals as input and output ports. Input port K Output port R5 BREQ input BACK output Fig BREQ/BACK terminals When the bus authority release request (BREQ = LOW) is received from an external device, the SC8F36 switches the address bus, data bus, RD/ WR signal, and CE signal lines to a high impedance state, outputs a LOW level from the BACK terminal and releases bus authority. As soon as a LOW level is output from the BACK terminal, the external device can use the external bus. When DMA is completed, the external device returns the BREQ terminal to HIGH and releases bus authority. Figure shows the bus authority release sequence. During bus authority release state, internal memory cannot be accessed from the external device. In cases where external memory has areas which overlap areas in internal memory, the external memory areas can be accessed accordance with the CE signal output by the external device. Note: Be careful with the system, such that an external device does not become the bus master, other than during the bus release status. After setting the BREQ terminal to LOW level, hold the BREQ terminal at LOW level until the BACK terminal becomes LOW level. If the BREQ terminal is returned to HIGH level, before the BACK terminal becomes LOW level, the shift to the bus authorization release status will become indefinite. CLK Tw2 T4 T T2 T3 Tw Tw2 T4 Tz Tz2 Tz Tz2 Tz Tz2 Tz Tz2 T T2 T3 AA8 IX HL PC DD7 (IX) (IX) ANY WR RD BREQ L L L L H BACK Program execution status Bus authority release status Program execution status LD [HL],[IX] Fig Bus authority release sequence 6 EPSON SC8F36 TECHNICAL MANUAL

29 4 INITIAL RESET 4 INITIAL RESET Initial reset in the SC8F36 is required in order to initialize circuits. This section of the Manual contains a description of initial reset factors and the initial settings for internal registers, etc. 4. Initial Reset Factor Initial reset can be done by executed externally inputting a LOW level to the RESET terminal. Figure 4.. shows the configuration of the initial reset circuit. The CPU and peripheral circuits are initialized when the RESET terminal is pulled down to LOW. When the RESET terminal is returned to HIGH, the CPU commences reset exception processing. (See "SC88 Core CPU Manual".) When this occurs, reset exception processing vectors, Bank, HH from program memory are read out and the program (initialization routine) which begins at the readout address is executed. Be sure to maintain the RESET terminal at LOW level for the regulation time after the power on to assure the initial reset. In addition, be sure to use the RESET terminal for the first initial reset after the power is turned on. After cancellation of the LOW level input to the RESET terminal, when the power is turned on, the start-up of the CPU is held back until the oscillation stabilization waiting time (8,92/fOSC sec.) has elapsed. Figure 4..2 shows the operating sequence following initial reset release. RESET VDD SLEEP status Oscillation stability waiting signal Internal initial reset Fig. 4.. Configuration of initial reset circuit fosc RESET Internal initial reset Internal address bus PC PC PC - Internal data bus Dummy Dummy VECL Internal read signal 892/fOSC [sec] Oscillation stable waiting time Dummy cycle Reset exception processing Fig Initial reset sequence SC8F36 TECHNICAL MANUAL EPSON 7

30 4 INITIAL RESET 4.2 Initial Settings After Initial Reset The CPU internal registers are initialized as follows during initial reset. Table 4.2. Initial settings Register name Code Bit length Setting value Data register A A 8 Undefined Data register B B 8 Undefined Index (data) register L L 8 Undefined Index (data) register H H 8 Undefined Index register IX IX 6 Undefined Index register IY IY 6 Undefined Program counter PC 6 Undefined* Stack pointer SP 6 Undefined Base register BR 8 Undefined Zero flag Z Carry flag C Overflow flag V Negative flag N Decimal flag D Unpack flag U Interrupt flag I Interrupt flag I New code bank register NB 8 H Code bank register CB 8 Undefined* Expand page register EP 8 H Expand page register for IX XP 8 H Expand page register for IY YP 8 H * Reset exception processing loads the preset values stored in bank, HH into the PC. At the same time, H of the NB initial value is loaded into CB. Initialize the registers which are not initialized at initial reset using software. Since the internal RAM and display memory are not initialized at initial reset, be sure to initialize using software. The respectively stipulated initializations are done for internal peripheral circuits. If necessary, the initialization should be done using software. For initial value at initial reset, see the sections on the I/O memory map and peripheral circuit descriptions in the following chapter of this Manual. 8 EPSON SC8F36 TECHNICAL MANUAL

31 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) 5 PERIPHERAL CIRCUITS AND THEIR OPERATION The peripheral circuits of the SC8F36 is interfaced with the CPU by means of the memory mapped I/O method. For this reason, just as with other memory access operations, peripheral circuits can be controlled by manipulating I/O memory. Below is a description of the operation and control method for each individual peripheral circuit. 5. I/O Memory Map Table 5..(a) I/O Memory map (FFHFF2H, MCU mode) Address Bit Name Function SR Comment FF D7 BSMD Bus mode (CPU mode) (MCU) BSMD BSMD Mode 52K (Maximum) Do not set D6 BSMD 52K (Minimum) BSMD to B. Single chip D5 CEMD register D4 CEMD register D3 D2 D D CE3 CE2 CE CE CE3 (R33) CE2 (R32) CE (R3) CE (R3) CE signal output Enable/Disable Enable: CE signal output Disable: DC (R3x) output CE3 enable CE2 enable CE enable CE enable CE3 disable CE2 disable CE disable CE disable In the Single chip mode, these setting are fixed at DC output. FF D7 SPP7 Stack pointer page address (MSB) D6 SPP6 D5 SPP5 < SP page allocatable address > D4 SPP4 Single chip mode: only page D3 SPP3 64K mode: only page D2 SPP2 52K (min) mode: 27H page D SPP 52K (max) mode: 27H page D SPP (LSB) FF2 D7 EBR Bus release enable register (K and R5 terminal specification) K R5 BREQ BACK Input port Output port D6 D5 D4 WT2 WT WT Wait control register WT2 WT WT Number of state No wait D3 CLKCHG CPU operating clock switch OSC3 OSC D2 OSCC OSC3 oscillation On/Off control On Off Operating mode selection D VDC VDC VDC Operating mode D VDC High speed (VD=3.V) Low power (VD=.85V) Normal (VD=2.2V) Note: All the interrupts including NMI are disabled, until you write the optional value into both the "FFH" and "FFH" addresses. SC8F36 TECHNICAL MANUAL EPSON 9

32 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(b) I/O Memory map (FFHFF2H, MPU mode) Address Bit Name Function SR FF D7 BSMD Bus mode (CPU mode) (MPU) BSMD BSMD Mode 52K (Maximum) D6 BSMD 52K (Minimum) 64K 64K D5 CEMD Chip enable mode CEMD CEMD D4 CEMD D3 D2 D D CE3 CE2 CE CE FF D7 SPP7 D6 SPP6 D5 SPP5 D4 SPP4 D3 SPP3 D2 SPP2 D SPP D SPP FF2 D7 EBR D6 WT2 D5 WT D4 WT CE3 (R33) CE2 (R32) CE (R3) CE (R3) CE signal output Enable/Disable Enable: CE signal output Disable: DC (R3x) output Stack pointer page address < SP page allocatable address > Single chip mode: only page 64K mode: only page 52K (min) mode: 27H page 52K (max) mode: 27H page WT2 WT Mode 64K (CE) 32K (CE, CE) 6K (CECE3) 8K (CECE3) (MSB) (LSB) Bus release enable register K (K and R5 terminal specification) R5 Wait control register Number of state WT No wait CE3 enable CE2 enable CE enable CE enable BREQ BACK CE3 disable CE2 disable CE disable CE disable Input port Output port Comment Only for 64K bus mode D3 CLKCHG CPU operating clock switch OSC3 OSC D2 OSCC OSC3 oscillation On/Off control On Off Operating mode selection D VDC VDC VDC Operating mode D VDC High speed (VD=3.V) Low power (VD=.85V) Normal (VD=2.2V) Note: All the interrupts including NMI are disabled, until you write the optional value into both the "FFH" and "FFH" addresses. 2 EPSON SC8F36 TECHNICAL MANUAL

33 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Address Bit Name FF9 D7 D6 D5 D4 D3 D2 LCDB D LCDAJ D DUTY8 FF D7 D6 D5 D4 LCCLK D3 LCFRM D2 DTFNT D LDUTY D SGOUT FF D7 D6 DSPAR D5 LCDC D4 LCDC D3 LC3 D2 LC2 D LC D LC FF2 D7 D6 D5 SVDSP Table 5..(c) I/O Memory map (FF9HFF3H) Function SR Comment Constantly "" when being read Reserved Power TYPE A (4.5V)/B (5.5V) switch TYPE A TYPE B LCD drive duty switch /8 duty /6, /32 * Constantly "" when being read CL output control for expanded LCD driver On Off FR output control for expanded LCD driver On Off LCD dot font selection 5 x 5 dots 5 x 8 dots LCD drive duty selection /6 duty /32 duty * register Reserved register "" when being read LCD display memory area selection Display area Display area LCD display control LCDC LCDC LCD display These bits are reset All LCDs lit to (, ) when All LCDs out SLP instruction Normal display is executed. Drive off LCD contrast adjustment LC3 : LC2 : LC : LC : SVD auto-sampling control D3 SVD3 SVD detection level D2 SVD2 SVD3 SVD2 SVD SVD D SVD D SVD : : : : FF3 D7 D6 D5 D4 D3 CMPON Comparator On/Off control D2 CMPON Comparator On/Off control D CMPDT Comparator data D CMPDT Comparator data Contrast Dark : : Light D4 SVDON SVD continuous sampling control/status R W Detection level Level 5 Level 4 : Level On Busy On On On + > - + > - Off Ready Off Off Off + < - + < - * Writing "" to DUTY8 (FF9 D) disables /6 and /32 duty selection using LDUTY (FF D). *2 After initial reset, this status is set "" until conclusion of hardware first sampling. *3 Initial values are set according to the supply voltage detected at first sampling by hardware. Until conclusion of first sampling, SVDSVD3 data are undefined. Constantly "" when being read These registers are reset to "" when *2 SLP instruction is executed. X R *3 X R X R X R Constantly "" when being read R R SC8F36 TECHNICAL MANUAL EPSON 2

34 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(d) I/O Memory map (FF2HFF25H) Address Bit Name Function SR FF2 D7 D5 D3 D PK PSIF PSW PTM D6 D4 D2 D PK PSIF PSW PTM KK7 interrupt priority register Serial interface interrupt priority register Stopwatch timer interrupt priority register Clock timer interrupt priority register FF2 D7 D6 D5 D4 D3 PPT D2 PPT Programmable timer interrupt priority register D PK D PK K and K interrupt priority register FF22 D7 D6 ESW Stopwatch timer Hz interrupt enable register D5 ESW Stopwatch timer Hz interrupt enable register D4 ESW Stopwatch timer Hz interrupt enable register D3 ETM32 Clock timer 32 Hz interrupt enable register D2 ETM8 Clock timer 8 Hz interrupt enable register D ETM2 Clock timer 2 Hz interrupt enable register D ETM Clock timer Hz interrupt enable register FF23 D7 EPT Programmable timer interrupt enable register D6 EPT Programmable timer interrupt enable register D5 EK K and K interrupt enable register D4 EKH K4K7 interrupt enable register D3 EKL KK3 interrupt enable register D2 ESERR Serial I/F (error) interrupt enable register D ESREC Serial I/F (receiving) interrupt enable register D ESTRA Serial I/F (transmitting) interrupt enable register FF24 D7 D6 FSW Stopwatch timer Hz interrupt factor flag D5 FSW Stopwatch timer Hz interrupt factor flag D4 FSW Stopwatch timer Hz interrupt factor flag D3 FTM32 Clock timer 32 Hz interrupt factor flag D2 FTM8 Clock timer 8 Hz interrupt factor flag D FTM2 Clock timer 2 Hz interrupt factor flag D FTM Clock timer Hz interrupt factor flag FF25 D7 FPT Programmable timer interrupt factor flag D6 FPT Programmable timer interrupt factor flag D5 FK K and K interrupt factor flag D4 FKH K4K7 interrupt factor flag D3 FKL KK3 interrupt factor flag D2 FSERR Serial I/F (error) interrupt factor flag D FSREC Serial I/F (receiving) interrupt factor flag D FSTRA Serial I/F (transmitting) interrupt factor flag PK PSIF PSW PTM PPT PK Interrupt enable Interrupt enable PK PSIF PSW PTM PPT PK (R) Interrupt factor is generated (W) Reset (R) Interrupt factor is generated (W) Reset Priority level Level 3 Level 2 Level Level Priority level Level 3 Level 2 Level Level Interrupt disable Interrupt disable (R) No interrupt factor is generated (W) No operation (R) No interrupt factor is generated (W) No operation Comment Constantly "" when being read "" when being read "" when being read 22 EPSON SC8F36 TECHNICAL MANUAL

35 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(e) I/O Memory map (FF28HFF3H) Address Bit FF28 D7 D6 D5 D4 D3 D2 D D FF2A D7 D6 D5 D4 D3 D2 D D FF2C D7 Name PADC PADC EAD FAD Function A/D converter interrupt priority register Reserved Reserved A/D converter interrupt enable register Reserved A/D converter interrupt factor flag PADC PADC Priority Level 3 Level 2 Level Level Prohibited Prohibited Enable Disable R) Generated Not generated SR Comment Do not write "". Constantly "" when being read Constantly "" when being read D6 D5 D4 D3 D2 D D FF3 D7 D6 D5 D4 D3 D2 D D FF3 D7 D6 MODE6 8/6-bit mode selection CHSEL TOUT output channel selection PTOUT TOUT output control CKSEL Prescaler source clock selection CKSEL Prescaler source clock selection EVCNT FCSEL Reserved W) Timer counter mode selection Timer In timer mode function selection In event counter mode Reset 6-bit x Timer On fosc3 fosc3 Event counter Pulse width measurement With No operation 8-bit x 2 Timer Off fosc fosc Timer Normal mode Without Constantly "" when being read Constantly "" when being read D5 D4 D3 D2 D D PLPOL PSC PSC CONT PSET PRUN noise rejector noise rejector Timer pulse polarity Down count timing in event counter mode Rising edge of K input Falling edge of K input selection In pulse width High level Low level measurement measurement measurement mode for K input for K input Timer prescaler dividing ratio selection PSC PSC Prescaler dividing ratio Source clock / 64 Source clock / 6 Source clock / 4 Source clock / Timer continuous/one-shot mode selection Timer preset Timer Run/Stop control Continuous Preset Run One-shot No operation Stop W "" when being read SC8F36 TECHNICAL MANUAL EPSON 23

36 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(f) I/O Memory map (FF32HFF36H) Address Bit Name Function SR FF32 D7 D6 D5 D4 PSC D3 PSC D2 CONT D PSET D PRUN FF33 D7 D6 D5 D4 D3 D2 D D RLD7 RLD6 RLD5 RLD4 RLD3 RLD2 RLD RLD FF34 D7 RLD7 D6 RLD6 D5 RLD5 D4 RLD4 D3 RLD3 D2 RLD2 D RLD D RLD FF35 D7 PTD7 D6 PTD6 D5 PTD5 D4 PTD4 D3 PTD3 D2 PTD2 D PTD D PTD FF36 D7 PTD7 D6 PTD6 D5 PTD5 D4 PTD4 D3 PTD3 D2 PTD2 D PTD D PTD Timer prescaler dividing ratio selection PSC PSC Prescaler dividing ratio Source clock / 64 Source clock / 6 Source clock / 4 Source clock / Timer continuous/one-shot mode selection Continuous Timer preset Preset Timer Run/Stop control Run One-shot No operation Stop W Timer reload data D7 (MSB) Timer reload data D6 Timer reload data D5 Timer reload data D4 Timer reload data D3 Timer reload data D2 Timer reload data D Timer reload data D (LSB) High Low Timer reload data D7 (MSB) Timer reload data D6 Timer reload data D5 Timer reload data D4 Timer reload data D3 High Low Timer reload data D2 Timer reload data D Timer reload data D (LSB) Timer counter data D7 (MSB) Timer counter data D6 Timer counter data D5 Timer counter data D4 Timer counter data D3 Timer counter data D2 Timer counter data D Timer counter data D (LSB) High Low R Timer counter data D7 (MSB) Timer counter data D6 Timer counter data D5 Timer counter data D4 Timer counter data D3 High Low R Timer counter data D2 Timer counter data D Timer counter data D (LSB) Comment Constantly "" when being read "" when being read 24 EPSON SC8F36 TECHNICAL MANUAL

37 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(g) I/O Memory map (FF4HFF44H) Address Bit Name Function SR Comment FF4 D7 D6 FOUT2 FOUT frequency selection "" when being read D5 D4 FOUT FOUT FOUT2 FOUT FOUT Frequency fosc / fosc / 2 fosc / 4 fosc / 8 fosc3 / fosc3 / 2 fosc3 / 4 fosc3 / 8 D3 D2 D D FF4 D7 D6 D5 D4 D3 D2 D D FF42 D7 D6 D5 D4 D3 D2 D D FF43 D7 D6 D5 D4 D3 D2 D D FF44 D7 D6 D5 D4 D3 D2 D D FOUTON WDRST TMRST TMRUN TMD7 TMD6 TMD5 TMD4 TMD3 TMD2 TMD TMD SWRST SWRUN SWD7 SWD6 SWD5 SWD4 SWD3 SWD2 SWD SWD BZSTP BZSHT SHTPW ENRTM ENRST ENON BZON FOUT output control Watchdog timer reset Clock timer reset Clock timer Run/Stop control Clock timer data Hz Clock timer data 2 Hz Clock timer data 4 Hz Clock timer data 8 Hz Clock timer data 6 Hz Clock timer data 32 Hz Clock timer data 64 Hz Clock timer data 28 Hz Stopwatch timer reset Stopwatch timer Run/Stop control Stopwatch timer data BCD (/ sec) Stopwatch timer data BCD (/ sec) One-shot buzzer forcibly stop One-shot buzzer trigger/status R W One-shot buzzer duration width selection Envelope attenuation time Envelope reset Envelope On/Off control Buzzer output control On Off Reset No operation Reset No operation Run Stop High Low Reset No operation Run Stop Forcibly stop No operation Busy Ready Trigger No operation 25 msec 3.25 msec sec.5 sec Reset No operation On Off On Off W W R W R W W Constantly "" when being read Constantly "" when being read Constantly "" when being read "" when being read * * Reset to "" during one-shot output. SC8F36 TECHNICAL MANUAL EPSON 25

38 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(h) I/O Memory map (FF45HFF49H) Address Bit Name Function SR FF45 D7 D6 DUTY2 D5 DUTY D4 DUTY D3 D2 BZFQ2 D BZFQ D BZFQ FF48 D7 D6 EPR D5 PMD D4 SCS D3 SCS D2 SMD D SMD D ESIF FF49 D7 D6 FER D5 PER D4 OER D2 RXEN D TXTRG D TXEN Buzzer signal duty ratio selection DUTY2 Buzzer frequency (Hz) /6 8/2 2/24 2/28 7/6 7/2 /24 /28 6/6 6/2 /24 /28 5/6 5/2 9/24 9/28 4/6 4/2 8/24 8/28 3/6 3/2 7/24 7/28 2/6 2/2 6/24 6/28 /6 /2 5/24 5/28 Buzzer frequency selection BZFQ2 BZFQ BZFQ Frequency (Hz) Parity enable register Parity mode selection Clock source selection SCS SCS Clock source Programmable timer fosc3 / 4 fosc3 / 8 fosc3 / 6 Serial I/F mode selection SMD SMD Mode Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master Serial I/F enable register Framing error flag Parity error flag Overrun error flag D3 RXTRG Receive trigger/status Receive enable Transmit trigger/status Transmit enable R W R W R W R W R W With parity Odd Serial I/F Error Reset () Error Reset () Error Reset () Run Trigger Enable Run Trigger Enable Non parity Even I/O port No error No operation No error No operation No error No operation Stop No operation Disable Stop No operation Disable Comment "" when being read "" when being read "" when being read Only for asynchronous mode In the clock synchronous slave mode, external clock is selected. "" when being read Only for asynchronous mode 26 EPSON SC8F36 TECHNICAL MANUAL

39 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(i) I/O Memory map (FF4AHFF54H) Address Bit Name Function SR FF4A D7 TRXD7 Transmit/Receive data D7 (MSB) D6 TRXD6 Transmit/Receive data D6 D5 TRXD5 Transmit/Receive data D5 D4 TRXD4 Transmit/Receive data D4 D3 TRXD3 Transmit/Receive data D3 High Low X D2 TRXD2 Transmit/Receive data D2 D TRXD Transmit/Receive data D D TRXD Transmit/Receive data D (LSB) FF5 D7 D6 D5 D4 D3 D2 D D SIK7 SIK6 SIK5 SIK4 SIK3 SIK2 SIK SIK K7 interrupt selection register K6 interrupt selection register K5 interrupt selection register K4 interrupt selection register K3 interrupt selection register K2 interrupt selection register K interrupt selection register K interrupt selection register Interrupt enable Interrupt disable FF5 D7 D6 D5 D4 D3 D2 D SIK K interrupt selection register Interrupt Interrupt D SIK K interrupt selection register enable disable FF52 D7 KCP7 K7 interrupt comparison register D6 KCP6 K6 interrupt comparison register D5 KCP5 K5 interrupt comparison register Interrupt Interrupt D4 KCP4 K4 interrupt comparison register generated generated D3 KCP3 K3 interrupt comparison register at falling at rising D2 KCP2 K2 interrupt comparison register edge edge D KCP K interrupt comparison register D KCP K interrupt comparison register FF53 D7 D6 D5 D4 D3 D2 D KCP K interrupt comparison register Falling Rising D KCP K interrupt comparison register edge edge FF54 D7 K7D K7 input port data D6 K6D K6 input port data D5 K5D K5 input port data D4 K4D K4 input port data High level Low level D3 K3D K3 input port data input input D2 K2D K2 input port data D KD K input port data D KD K input port data R Comment Constantly "" when being read Constantly "" when being read SC8F36 TECHNICAL MANUAL EPSON 27

40 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(j) I/O Memory map (FF55HFF7H) Address Bit Name Function SR FF55 D7 D6 D5 D4 D3 D2 D KD K input port data High level Low level D KD K input port data input input R FF6 D7 IOC7 P7 I/O control register D6 IOC6 P6 I/O control register D5 IOC5 P5 I/O control register D4 IOC4 P4 I/O control register D3 IOC3 P3 I/O control register Output Input D2 IOC2 P2 I/O control register D IOC P I/O control register D IOC P I/O control register FF6 D7 D6 D5 IOC7 IOC6 IOC5 P7 I/O control register P6 I/O control register P5 I/O control register D4 IOC4 P4 I/O control register D3 IOC3 P3 I/O control register Output Input D2 D D IOC2 IOC IOC P2 I/O control register P I/O control register P I/O control register FF62 D7 P7D P7 I/O port data D6 P6D P6 I/O port data D5 P5D P5 I/O port data D4 P4D P4 I/O port data D3 P3D P3 I/O port data High Low D2 P2D P2 I/O port data D PD P I/O port data D PD P I/O port data FF63 D7 P7D P7 I/O port data D6 P6D P6 I/O port data D5 P5D P5 I/O port data D4 P4D P4 I/O port data D3 P3D P3 I/O port data High Low D2 P2D P2 I/O port data D PD P I/O port data D PD P I/O port data FF7 D7 HZR5 R5 high impedance control High Complementary D6 HZR5 R5 high impedance control impedance D5 HZR4H register D4 HZR4L register D3 HZRH R4R7 high impedance control D2 HZRL RR3 high impedance control High Complementary D HZRH R4R7 high impedance control impedance D HZRL RR3 high impedance control Comment Constantly "" when being read Reserved register 28 EPSON SC8F36 TECHNICAL MANUAL

41 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(k) I/O Memory map (FF7HFF76H) Address Bit Name Function SR FF7 D7 HZR27 R27 high impedance control D6 HZR26 R26 high impedance control D5 HZR25 R25 high impedance control D4 HZR24 R24 high impedance control High Complementary D3 HZR23 R23 high impedance control impedance D2 HZR22 R22 high impedance control D HZR2 R2 high impedance control D HZR2 R2 high impedance control FF72 D7 HZR37 R37 high impedance control D6 HZR36 R36 high impedance control D5 HZR35 R35 high impedance control D4 HZR34 R34 high impedance control High Complementary D3 HZR33 R33 high impedance control impedance D2 HZR32 R32 high impedance control D HZR3 R3 high impedance control D HZR3 R3 high impedance control FF73 D7 R7D R7 output port data D6 R6D R6 output port data D5 R5D R5 output port data D4 R4D R4 output port data D3 R3D R3 output port data High Low D2 R2D R2 output port data D RD R output port data D RD R output port data FF74 D7 R7D R7 output port data D6 R6D R6 output port data D5 R5D R5 output port data D4 R4D R4 output port data D3 R3D R3 output port data High Low D2 R2D R2 output port data D RD R output port data D RD R output port data FF75 D7 R27D R27 output port data D6 R26D R26 output port data D5 R25D R25 output port data D4 R24D R24 output port data D3 R23D R23 output port data High Low D2 R22D R22 output port data D R2D R2 output port data D R2D R2 output port data FF76 D7 R37D R37 output port data D6 R36D R36 output port data D5 R35D R35 output port data D4 R34D R34 output port data D3 R33D R33 output port data High Low D2 R32D R32 output port data D R3D R3 output port data D R3D R3 output port data Comment SC8F36 TECHNICAL MANUAL EPSON 29

42 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(l) I/O Memory map (FF77HFF82H) Address Bit Name Function SR FF77 D7 R47D D6 R46D D5 R45D D4 R44D D3 R43D D2 R42D D R4D D R4D FF78 D7 D6 D5 D4 D3 D2 D R5D D R5D FF8 D7 D6 D5 D4 D3 PRAD D2 PSAD2 D PSAD D PSAD register register register register register register register register R5 output port data R5 output port data A/D converter clock control A/D converter division ratio PSAD2 PSAD PSAD Division ratio fosc / fosc3 / 64 fosc3 / 32 fosc3 / 6 fosc3 / 8 fosc3 / 4 fosc3 / 2 fosc3 / High High On Low Low Off Comment Reserved register Constantly "" when being read Constantly "" when being read FF8 D7 D6 D5 D4 D3 D2 D D FF82 D7 D6 D5 D4 D3 D2 D D PAD7 PAD6 PAD5 PAD4 ADRUN CHS CHS P7 A/D converter input control P6 A/D converter input control P5 A/D converter input control P4 A/D converter input control A/D conversion start control register Analog input channel selection CHS CHS Input channel AD7 AD6 AD5 AD4 A/D converter input Start I/O port Invalid W Constantly "" when being read Constantly "" when being read 3 EPSON SC8F36 TECHNICAL MANUAL

43 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map) Table 5..(m) I/O Memory map (FF83HFF84H) Address Bit Name Function SR FF83 D7 ADDR9 A/D conversion result D9 (MSB) D6 ADDR8 A/D conversion result D8 D5 ADDR7 A/D conversion result D7 D4 ADDR6 A/D conversion result D6 D3 ADDR5 A/D conversion result D5 R D2 ADDR4 A/D conversion result D4 D ADDR3 A/D conversion result D3 D ADDR2 A/D conversion result D2 FF84 D7 D6 D5 D4 D3 D2 D ADDR A/D conversion result D D ADDR A/D conversion result D (LSB) R Comment Constantly "" when being read SC8F36 TECHNICAL MANUAL EPSON 3

44 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control) 5.2 System Controller and Bus Control The system controller is a management unit which sets such items as the bus mode in accordance with memory system configuration factors. For the purposes of controlling the system, the following settings can be performed in software: () Bus mode (CPU mode) settings (2) Chip enable (CE) signal output settings (3) WAIT state settings for external memory (4) Bus authority release request / acknowledge signal (BREQ/BACK) settings (5) Page address setting of the stack pointer Below is a description of the how these settings are to be made Bus mode settings As explained in "3.5.2 Bus mode", the SC8F36 has four bus modes. Settings for bus modes must be made in software and must match the capacity of the external memory. As shown in Table 5.2.., bus mode settings are performed on the basis of the preset values for each mode written to the registers BSMD and BSMD. Setting value BSMD BSMD Table Bus mode settings Bus mode Expanded 52K maximum mode Expanded 52K minimum mode Expanded 64K mode (MPU mode) Single chip mode (MCU mode) Expanded 64K mode (MPU mode) Configuration of external memory ROM+RAM>64K bytes (Program>64K bytes) ROM+RAM>64K bytes (Program 64K bytes) ROM+RAM 64K bytes None ROM+RAM 64K bytes * The single chip mode setting is only possible when this IC is used in the MCU mode. The single chip mode setting is incompatible with the MPU mode, since this mode does not utilize internal PROM. 32 EPSON SC8F36 TECHNICAL MANUAL

45 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control) The function of I/O terminals is set as shown in Table in accordance with mode selection. Table I/O terminal settings Terminal Bus mode Single chip Expanded 64K mode Expanded 52K mode R R R2 R3 R4 R5 R6 R7 R R R2 R3 R4 R5 R6 R7 R2 R2 R22 R23 R24 P P P2 P3 P4 P5 P6 P7 Output port R Output port R Output port R2 Output port R3 Output port R4 Output port R5 Output port R6 Output port R7 Output port R Output port R Output port R2 Output port R3 Output port R4 Output port R5 Output port R6 Output port R7 Output port R2 Output port R2 Output port R22 Output port R23 Output port R24 I/O port P I/O port P I/O port P2 I/O port P3 I/O port P4 I/O port P5 I/O port P6 I/O port P7 Address bus A Address bus A Address bus A2 Address bus A3 Address bus A4 Address bus A5 Address bus A6 Address bus A7 Address bus A8 Address bus A9 Address bus A Address bus A Address bus A2 Address bus A3 Address bus A4 Address bus A5 Address bus A6 Address bus A7 Address bus A8 RD signal WR signal Data bus D Data bus D Data bus D2 Data bus D3 Data bus D4 Data bus D5 Data bus D6 Data bus D7 At initial reset, the bus mode is set as explained below. In MCU mode: At initial reset, the SC8F36 is set in single chip mode. Accordingly, in MCU mode, even if a memory has been externally expanded, the system is activated by the program written to internal PROM. In the system with externally expanded memory, perform the applicable bus mode settings during the initialization routine originating in internal PROM. In MPU mode: At initial reset, the SC8F36 enters expanded 64K mode. In the system with more than 64K-byte externally expanded memory, perform the applicable bus mode settings during the initialization routine originating in internal PROM. SC8F36 TECHNICAL MANUAL EPSON 33

46 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control) Address decoder (CE output) settings As explained in Section 3.6.4, the SC8F36 is equipped with address decoders that can output a maximum of four chip enable signals (CECE3) to external devices. The output terminals and output circuits for CE CE3 are shared with output ports R3R33. At initial reset, they are set as output port terminals. For this reason, when operating in a mode other than single chip mode, the ports to be used as CE signal output terminals must be set as such. This setting is performed through software which writes "" to registers CECE3 corresponding the CE signals to be used. Table shows the address range assigned to the four chip enable (CE) signals. The arrangement of memory space for external devices does not necessarily have to be continuous from a subordinate address and any of the chip enable signals can be used to assign areas in memory. However, in the MPU mode, program memory must be assigned to CE. In the expanded 52K mode, the address range of each of the CE signals is fixed. In the expanded 64K mode, the four address ranges, which match the amount of memory in use, are selected with registers CEMD and CEMD. These signals are only output when the appointed external memory area is accessed and are not output when internal memory is accessed. Table Address settings of CECE3 () Expanded 64K mode (MPU mode only) CEMD CEMD Chip size CE CE CE2 64K bytes HEFFFH 32K bytes H7FFFH 8HEFFFH 6K bytes H3FFFH 4H7FFFH 8HBFFFH 8K bytes HFFFH 2H3FFFH 4H5FFFH CE3 CHEFFFH 6H7FFFH (2) Expanded 52K minimum/maximum modes CE signal MCU mode CE 2H27FFFFH CE 8HFFFFFH CE2 H7FFFFH CE3 8HFFFFFH Address range MPU mode HEFFFH, H7FFFFH 8HFFFFFH H7FFFFH 8HFFFFFH 34 EPSON SC8F36 TECHNICAL MANUAL

47 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control) WAIT state settings In order to insure accessing of external low speed devices during high speed operations, the SC8F36 is equipped with a WAIT function which prolongs access time. The number of wait states inserted can be selected from a choice of eight as shown in Table by means of registers WTWT2. Table Setting the number of WAIT states WT2 WT WT Number of inserted states No wait * A state is /2 cycles of the clock in length. WAIT states set in software are inserted between bus cycle states T3T4. Note, however, that WAIT states cannot be inserted when an internal register and internal memory are being accessed and when operating with the OSC oscillation circuit (see "5.4 Oscillation Circuits and Operating Mode"). Consequently, WAIT state settings in single chip mode are meaningless. With regard to WAIT insertion timing, see Section 3.6.5, "WAIT control" Stack page setting Although the stack area used to evacuate registers during subroutine calls can be arbitrarily moved to any area in data RAM using the stack pointer SP, its page address is set in registers SPPSPP7 in I/O memory. At initial reset, SPPSPP7 are set to "H" (page ). Since the internal RAM is arranged on page (FHF7FFH), the stack area in single chip mode is inevitably located in page. In expanded 64K mode where RAM is externally expanded, stack page is likewise limited to page. In order to place the stack area at the final address in internal RAM, the stack pointer SP is placed at an initial setting of "F8H". (SP is pre-decremented.) In the expanded 52K mode, to place the stack in external expanded RAM, set a corresponding page to SPPSPP7. The page addresses to which SPP SPP7 can be set are H27H and must be within a RAM area. * A page is each recurrent 64K division of data memory beginning at address zero Setting the bus authority release request signal With systems performing DMA transfer, the bus authority release request signal (BREQ) input terminal and acknowledge signal (BACK) output terminal have to be set. The BREQ input terminal is shared with input port terminal K and the BACK output terminal with output port terminal R5. At initial reset, these terminal facilities are set as input port terminal and output port terminal, respectively. The terminals can be altered to function as BREQ/BACK terminals by writing a "" to register EBR. For details on bus authority release, see "3.6.6 Bus authority release state" and "SC88 Core CPU Manual". SC8F36 TECHNICAL MANUAL EPSON 35

48 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control) Control of system controller Table shows the control bits for the system controller. Table (a) System controller control bits (MCU mode) Address Bit Name Function SR Comment FF D7 BSMD Bus mode (CPU mode) (MCU) BSMD BSMD Mode 52K (Maximum) Do not set D6 BSMD 52K (Minimum) BSMD to B. Single chip D5 CEMD register D4 CEMD register D3 D2 D D CE3 CE2 CE CE CE3 (R33) CE2 (R32) CE (R3) CE (R3) CE signal output Enable/Disable Enable: CE signal output Disable: DC (R3x) output CE3 enable CE2 enable CE enable CE enable CE3 disable CE2 disable CE disable CE disable In the Single chip mode, these setting are fixed at DC output. FF D7 SPP7 Stack pointer page address (MSB) D6 SPP6 D5 SPP5 < SP page allocatable address > D4 SPP4 Single chip mode: only page D3 SPP3 64K mode: only page D2 SPP2 52K (min) mode: 27H page D SPP 52K (max) mode: 27H page D SPP (LSB) FF2 D7 EBR Bus release enable register (K and R5 terminal specification) K R5 BREQ BACK Input port Output port D6 D5 D4 WT2 WT WT Wait control register WT2 WT WT Number of state No wait D3 CLKCHG CPU operating clock switch OSC3 OSC D2 OSCC OSC3 oscillation On/Off control On Off Operating mode selection D VDC VDC VDC Operating mode D VDC High speed (VD=3.V) Low power (VD=.85V) Normal (VD=2.2V) Note: All the interrupts including NMI are disabled, until you write the optional value into both the "FFH" and "FFH" addresses. 36 EPSON SC8F36 TECHNICAL MANUAL

49 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control) Table (b) System controller control bits (MPU mode) Address Bit Name Function SR FF D7 BSMD Bus mode (CPU mode) (MPU) BSMD BSMD Mode 52K (Maximum) D6 BSMD 52K (Minimum) 64K 64K D5 CEMD Chip enable mode CEMD CEMD D4 CEMD D3 D2 D D CE3 CE2 CE CE FF D7 SPP7 D6 SPP6 D5 SPP5 D4 SPP4 D3 SPP3 D2 SPP2 D SPP D SPP FF2 D7 EBR D6 WT2 D5 WT D4 WT CE3 (R33) CE2 (R32) CE (R3) CE (R3) CE signal output Enable/Disable Enable: CE signal output Disable: DC (R3x) output Stack pointer page address < SP page allocatable address > Single chip mode: only page 64K mode: only page 52K (min) mode: 27H page 52K (max) mode: 27H page WT2 WT Mode 64K (CE) 32K (CE, CE) 6K (CECE3) 8K (CECE3) (MSB) (LSB) Bus release enable register K (K and R5 terminal specification) R5 Wait control register Number of state WT No wait CE3 enable CE2 enable CE enable CE enable BREQ BACK CE3 disable CE2 disable CE disable CE disable Input port Output port Comment Only for 64K bus mode D3 CLKCHG CPU operating clock switch OSC3 OSC D2 OSCC OSC3 oscillation On/Off control On Off Operating mode selection D VDC VDC VDC Operating mode D VDC High speed (VD=3.V) Low power (VD=.85V) Normal (VD=2.2V) Note: All the interrupts including NMI are disabled, until you write the optional value into both the "FFH" and "FFH" addresses. SC8F36 TECHNICAL MANUAL EPSON 37

50 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control) BSMD, BSMD: FFH D6, D7 Bus modes are set as shown in Table Table Bus mode settings Setting values BSMD BSMD Bus mode Expanded 52K maximum mode Expanded 52K minimum mode Expanded 64K mode (MPU mode) Single chip mode (MCU mode) Expanded 64K mode (MPU mode) The single chip mode setting is only possible when this IC is used in the MCU mode. The single chip mode setting is incompatible with the MPU mode, since this mode does not utilize internal PROM. At initial reset, single chip mode is set in the MCU mode and expanded 64K mode is set in the MPU mode. CEMD, CEMD: FFH D4, D5 Sets the CE signal address range (valid only in the expanded 64K mode ). Settings are made according to external memory chip size as shown in Table Table CE signal settings CEMD CEMD Address range Usable terminals 64K bytes 32K bytes 6K bytes 8K bytes CE CE, CE CECE3 CECE3 These settings are invalid for any mode other than expanded 64K mode. At initial reset, each register is set to "" (64K bytes). Settings of these registers are valid only in the MPU mode. CEMD and CEMD can be used as general purpose registers with read/write capabilities in the MCU mode. CECE3: FFH DD3 Sets the CE output terminals being used. When "" is written: CE output enable When "" is written: CE output disable Reading: Valid CE output is enabled when a "" is written to registers CECE3 which correspond to the CE output being used. A "" written to any of the registers disables CE signal output from that terminal and it reverts to its alternate function as an output port terminal (R3R33). At initial reset, register CE is set to "" in the MCU mode and in the MPU mode, "" is set in the register. Registers CECE3 are always set to "" regardless of the MCU/MPU mode setting. Note: To avoid a malfunction from an interrupt generated before the bus configuration is initialized, all interrupts including NMI are masked until you write an optional value into address "FFH". SPPSPP7: FFH Sets the page address of stack area. In single chip mode and expanded 64K mode, set page address to "H". In expanded 52K mode, it can be set to any value within the range "H""27H". Since a carry and borrow from/to the stack pointer SP is not reflected in register SPP, the upper limit on continuous use of the stack area is 64K bytes. At initial reset, this register is set to "H" (page ). Note: To avoid a malfunction from an interrupt generated before the bus configuration is initialized, all interrupts including NMI are disabled, until you write an optional value into "FFH" address. Furthermore, to avoid generating an interrupt while the stack area is being set, all interrupts including NMI are disabled in one instruction execution period after writing to address "FFH". 38 EPSON SC8F36 TECHNICAL MANUAL

51 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control) WTWT2: FF2H D4D6 How WAIT state settings are performed. The number of WAIT states to be inserted based on register settings is as shown in Table Table Setting WAIT states WT2 WT WT Number of inserted states No wait * A state is /2 cycles of the clock in length. At initial reset, this register is set to "" (no wait). EBR: FF2H D7 Sets the BREQ/BACK terminals function. When "" is written: BREQ/BACK enabled When "" is written: BREQ/BACK disabled Reading: Valid How BREQ and BACK terminal functions are set. Writing "" to EBR enables BREQ/BACK input/ output. Writing "" sets the BREQ terminal as input port terminal K and the BACK terminal as output port terminal R5. At initial reset, EBR is set to "" (BREQ/BACK disabled) Programming notes () All the interrupts including NMI are masked, until you write the optional value into both the "FFH" and "FFH" addresses. Consequently, even if you do not change the content of this address (You use the initial value, as is.), you should still be sure to perform the writing operation using the initialization routine. (2) When setting stack fields, including page addresses as well, you should write them in the order of the register SPP ("FFH") and the stack pointer SP. Example: When setting the "78H" address LD EP, #H LD HL, #FFH LD [HL], #7H LD SP, #8H During this period the interrupts (including NMI) are masked. SC8F36 TECHNICAL MANUAL EPSON 39

52 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Watchdog Timer) 5.3 Watchdog Timer 5.3. Configuration of watchdog timer The SC8F36 is equipped with a watchdog timer driven by OSC as source oscillation. The watchdog timer must be reset periodically in software, and if reset of more than 34 seconds (when fosc = khz) does not take place, a non-maskable interrupt signal is generated and output to the CPU. Figure is a block diagram of the watchdog timer. OSC oscillation circuit fosc Divider WDRST Hz Watchdog timer reset signal Watchdog timer Fig Block diagram of watchdog timer Non-maskable interrupt (NMI) By running watchdog timer reset during the main routine of the program, it is possible to detect program runaway as if watchdog timer processing had not been applied. Normally, this routine is integrated at points that are regularly being processed. The watchdog timer continues to operate during HALT and when a HALT state is continuous for longer than 34 seconds, the CPU shifts to exception processing. During SLEEP, the watchdog timer is stopped Interrupt function In cases where the watchdog timer is not periodically reset in software, the watchdog timer outputs an interrupt signal to the CPU's NMI (level 4) input. Unmaskable and taking priority over other interrupts, this interrupt triggers the generation of exception processing. See the "SC88 Core CPU Manual" for more details on NMI exception processing. This exception processing vector is set at 4H Control of watchdog timer Table shows the control bits for the watchdog timer. WDRST: FF4H D2 Resets the watchdog timer. When "" is written: Watchdog timer is reset When "" is written: No operation Reading: Constantly "" By writing "" to WDRST, the watchdog timer is reset, after which it is immediately restarted. Writing "" will mean no operation. Since WDRST is for writing only, it is constantly set to "" during readout Programming notes () The watchdog timer must reset within 3-second cycles by software. (2) Do not execute the SLP instruction for 2 msec after a NMI interrupt has occurred (when fosc is khz). Table Watchdog timer control bits Address Bit Name Function SR Comment FF4 D7 "" when being read D6 FOUT2 FOUT frequency selection D5 D4 FOUT FOUT FOUT2 FOUT FOUT Frequency fosc / fosc / 2 fosc / 4 fosc / 8 fosc3 / fosc3 / 2 fosc3 / 4 fosc3 / 8 D3 FOUTON FOUT output control On Off D2 WDRST Watchdog timer reset Reset No operation W Constantly "" when D TMRST Clock timer reset Reset No operation W being read D TMRUN Clock timer Run/Stop control Run Stop 4 EPSON SC8F36 TECHNICAL MANUAL

53 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Oscillation Circuits and Operating Mode) 5.4 Oscillation Circuits and Operating Mode 5.4. Configuration of oscillation circuits The SC8F36 is twin clock system with two internal oscillation circuits (OSC and OSC3). OSC oscillation circuit generates the khz (Typ.) main clock and OSC3 oscillation circuit the sub-clock when the CPU and some peripheral circuits (output port, serial interface and programmable timer) are in high speed operation. Figure shows the configuration of the oscillation circuit. SLEEP status OSC oscillation circuit OSC3 oscillation circuit Clock switch To peripheral circuit (fosc) To CPU (CLK) Oscillation circuit control signal CPU clock selection signal OSCC CLKCHG To some peripheral circuit (fosc3) Fig Configuration of oscillation circuits At initial reset, OSC oscillation circuit is selected for the CPU operating clock and OSC3 oscillation circuit is in a stopped state. ON/OFF switching of the OSC3 oscillation circuit and switching of the system clock between OSC and OSC3 are controlled in software. OSC3 circuit is utilized when high speed operation of the CPU and some peripheral circuits become necessary. Otherwise, OSC should be used to generate the operating clock and OSC3 circuit placed in a stopped state in order to reduce current consumption OSC oscillation circuit The OSC oscillation circuit generates the khz (Typ.) system clock which is utilized during low speed operation (low power mode) of the CPU and peripheral circuits. Furthermore, even when OSC3 is utilized as the system clock, OSC continues to generate the source clock for the clock timer and stopwatch timer. This oscillation circuit stops when the SLP instruction is executed. The OSC oscillation circuit type is fixed at crystal oscillation. Figure shows the configuration of the OSC oscillation circuit. CG X'tal OSC OSC2 VSS Fig OSC oscillation circuit SLEEP status fosc VSS As shown in Figure , a crystal oscillation circuit can be easily formed by connecting a crystal oscillator X'tal (Typ khz) between the OSC and OSC2 terminals along with a trimmer capacitor CG (525 pf) between the OSC terminal and VSS Mask option In the SC8F36, the OSC oscillation circuit type is fixed at crystal oscillation. In terms of oscillation circuit types for OSC3, either crystal/ceramic oscillation or CR oscillation can be selected by mask option. SC8F36 TECHNICAL MANUAL EPSON 4

54 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Oscillation Circuits and Operating Mode) OSC3 oscillation circuit The OSC3 oscillation circuit generates the system clock when the CPU and some peripheral circuits (output port, serial interface and programmable timer) are in high speed operation. This oscillation circuit stops when the SLP instruction is executed, or the OSCC register is set to "". In terms of oscillation circuit types, either crystal / ceramic oscillation or CR oscillation can be selected by mask option. Figure shows the configuration of the OSC3 oscillation circuit. CG2 X'tal 2 or Ceramic CD2 VSS RCR3 OSC3 Rf OSC4 fosc3 Oscillation circuit control signal SLEEP status () Crystal/Ceramic oscillation circuit OSC3 OSC4 fosc3 (2) CR oscillation circuit Fig OSC3 oscillation circuit Oscillation circuit control signal SLEEP status When crystal/ceramic oscillation circuit is selected, the crystal or ceramic oscillation circuit are formed by connecting either a crystal oscillator (X'tal2) or a combination of ceramic oscillator (Ceramic) and feedback resistor (Rf) between OSC3 and OSC4 terminals and connecting two capacitors (CG2, CD2) between the OSC3 terminal and VSS, and between the OSC4 terminal and VSS, respectively. When CR oscillation is selected, the CR oscillation circuit is formed merely by connecting a resistor (RCR3) between OSC3 and OSC4 terminals Operating mode You can select three types of operating modes using software, to obtain a stable operation and good characteristics (operating frequency and current consumption) over a broad operation voltage. Here below are indicated the features of the respective modes. Normal mode (VDD = 2.4 V5.5 V) This mode is set following the initial reset. It permits the OSC3 oscillation circuit (Max. 4.2 MHz) to be used and also permits relative low power operation. Low power mode (VDD = 2. V3.5 V) This is a lower power mode than the normal mode. It makes ultra-low power consumption possible by operation on the OSC oscillation circuit, although the OSC3 circuit cannot be used. High speed mode (VDD = 3.5 V5.5 V) This mode permits higher speed operation than the normal mode. Since the OSC3 oscillation circuit (Max. 8.2 MHz) can be used, you should use this mode, when you require operation at 4.2 MHz or more. However, the current consumption will increase relative to the normal mode. Using software to switch over among the above three modes to meet your actual usage circumstances will make possible a low power system. For example, you will be able to reduce current consumption by switching over to the normal mode when using the OSC3 as the CPU clock and, conversely, changing over to the low power mode when using the OSC as the CPU clock (OSC3 oscillation circuit is OFF). Note: Do not turn the OSC3 oscillation circuit ON in the low power mode. Do not switch over the operating mode (normal mode high speed mode) in the OSC3 oscillation circuit ON status, as this will cause faulty operation. You can not use two modes, the low power mode and the high speed mode on one application, with respect to the operating voltages. 42 EPSON SC8F36 TECHNICAL MANUAL

55 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Oscillation Circuits and Operating Mode) Switching the CPU clocks You can use either OSC or OSC3 as the system clock for the CPU and you can switch over by means of software. You can save power by turning the OSC3 oscillation circuit off while the CPU is operating in OSC. When you must operate on OSC3, you can change to high speed operation by turning the OSC3 oscillation circuit ON and switching over the system clock. In this case, since several msec to several tens of msec are necessary for the oscillation to stabilize after turning the OSC3 oscillation circuit ON, you should switch over the clock after stabilization time has elapsed. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter, "ELECTRICAL CHARACTERISTICS".) When switching over from the OSC3 to the OSC, turn the OSC3 oscillation circuit OFF immediately following the clock changeover. The basic clock switching procedure is as described above, however, you must also combine it with the changeover of the operating mode to permit low current consumption and high speed operation. Figure indicates the status transition diagram for the operation mode and clock changeover. Notes: When turning ON the OSC3 oscillation circuit after switching the operating mode, you should allow a minimum waiting time of 5 msec. If the HALT instruction is executed or HALT mode is canceled while the CPU is running with the high-speed clock generated by the OSC3 oscillation circuit, the internal logic operating voltage VD becomes unstable momentarily and it may cause unexpected problem, such as runaway, be occurred. Do not use the HALT instruction while the CPU is running with the OSC3 high-speed clock. Program Execution Status High speed mode OSC ON OSC3 OFF CPU clock OSC OSCC= OSCC= High speed mode OSC ON OSC3 ON CPU clock OSC CLKCHG= CLKCHG= High speed mode OSC ON OSC3 ON CPU clock OSC3 VDC= VDC= Normal mode OSC OSC3 CPU clock VDC= VDC= RESET ON OFF OSC OSCC= OSCC= Normal mode OSC OSC3 CPU clock ON ON OSC CLKCHG= CLKCHG= Normal mode OSC OSC3 CPU clock ON ON OSC3 VDC= VDC= VDC= VDC= Low power mode OSC ON OSC3 OFF CPU clock OSC Interrupt * HALT instruction Interrupt * (Input interrupt) SLP instruction HALT status OSC ON OSC3 ON or OFF CPU clock STOP SLEEP status OSC OFF OSC3 OFF CPU clock STOP Standby Status * The return destination from the standby status becomes the program execution status prior to shifting to the standby status. Fig Status transition diagram for the operation mode and clock changeover SC8F36 TECHNICAL MANUAL EPSON 43

56 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Oscillation Circuits and Operating Mode) Control of oscillation circuit and operating mode Table shows the control bits for the oscillation circuits and operating modes. Table Oscillation circuit and operating mode control bits Address Bit Name Function SR FF2 Bus release enable register K BREQ Input port D7 EBR (K and R5 terminal specification) R5 BACK Output port Wait control register Number D6 WT2 of state D5 WT D4 WT WT2 WT WT No wait D3 CLKCHG CPU operating clock switch D2 OSCC OSC3 oscillation On/Off control Operating mode selection D VDC VDC VDC Operating mode High speed (VD=3.V) D VDC Low power (VD=.85V) Normal (VD=2.2V) OSC3 On OSC Off Comment VDC, VDC: FF2H D, D Selects the operating mode according to supply voltage and operating frequency. Table shows the correspondence between register preset values and operating modes. Table Correspondence between register preset values and operating modes Operating mode Normal mode Low power mode High speed mode VDC VDC VD Power voltage Operating frequency 2.2 V V 4.2 MHz (Max.).85 V V 5 khz (Max.) 3. V V 8.2 MHz (Max.) * The VD voltage is the value where VSS has been made the standard (GND). At initial reset, this register is set to "" (normal mode). OSCC: FF2H D2 Controls the ON and OFF settings of the OSC3 oscillation circuit. When "" is written: OSC3 oscillation ON When "" is written: OSC3 oscillation OFF Reading: Valid When the CPU and some peripheral circuits (output port, serial interface and programmable timer) are to be operated at high speed, OSCC is to be set to "". At all other times, it should be set to "" in order to reduce current consumption. At initial reset, OSCC is set to "" (OSC3 oscillation OFF). 44 EPSON SC8F36 TECHNICAL MANUAL

57 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Oscillation Circuits and Operating Mode) CLKCHG: FF2H D3 Selects the operating clock for the CPU. When "" is written: OSC3 clock When "" is written: OSC clock Reading: Valid When the operating clock for the CPU is switched to OSC3, CLKCHG should be set to "" and when the clock is switched to OSC, CLKCHG should be set to "". At initial reset, CLKCHG is set to "" (OSC clock) Programming notes () When the high speed CPU operation is not necessary, you should operate the peripheral circuits according to the setting outline indicate below. CPU operating clock OSC OSC3 oscillation circuit OFF (When the OSC3 clock is not necessary for some peripheral circuits.) Operating mode Low power mode (When VDDVSS is 3.5 V or less) or Normal mode (When VDDVSS is 3.5 V or more) (2) Do not turn the OSC3 oscillation circuit ON in the low power mode. Do not switch over the operating mode (normal mode high speed mode) in the OSC3 oscillation circuit ON status, as this will cause faulty operation. (3) When turning ON the OSC3 oscillation circuit after switching the operating mode, you should allow a minimum waiting time of 5 msec. (4) Since several msec to several tens of msec are necessary for the oscillation to stabilize after turning the OSC3 oscillation circuit ON. Consequently, you should switch the CPU operating clock (OSC OSC3) after allowing for a sufficient waiting time once the OSC3 oscillation goes ON. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter, "ELECTRICAL CHARACTERIS- TICS".) (5) When switching the clock from OSC3 to OSC, be sure to switch OSC3 oscillation OFF with separate instructions. Using a single instruction to process simultaneously can cause a malfunction of the CPU. (6) If the HALT instruction is executed or HALT mode is canceled while the CPU is running with the high-speed clock generated by the OSC3 oscillation circuit, the internal logic operating voltage VD becomes unstable momentarily and it may cause unexpected problem, such as runaway, be occurred. Do not use the HALT instruction while the CPU is running with the OSC3 high-speed clock. SC8F36 TECHNICAL MANUAL EPSON 45

58 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports) 5.5 Input Ports (K ports) 5.5. Configuration of input ports The SC8F36 is equipped with input port bits (KK7, K and K) all of which are usable as general purpose input port terminals with interrupt function. K terminal doubles as the external clock (EVIN) input terminal of the programmable timer (event counter) with input port functions sharing the input signal as is. (See "5. Programmable Timer") Furthermore, it should be noted, however, that K terminal is shared with the bus authority release request signal (BREQ) input terminal. Function assignment of this terminal can be selected in software. When this terminal is selected for BREQ signal, K cannot be used as an input port. (See "5.2 System Controller and Bus Control") In the explanation below, it is assumed that K is set as an input port. Figure shows the structure of the input port. VDD Input interrupt circuit Each input port terminal is directly connected via a three-state buffer to the data bus. Furthermore, the input signal state at the instant of input port readout is read in that form as data. Input ports KK7, K and K are all equipped with pull-up resistors. When changing the input terminal from LOW level to HIGH with the built-in pull-up resistor, a delay in the waveform rise time will occur depending on the time constant of the pull-up resistor and the load capacitance of the terminal. It is necessary to set an appropriate wait time for introduction of an input port. In particular, special attention should be paid to key scan for key matrix formation. Make this wait time the amount of time or more calculated by the following expression. Wait time = RIN x (CIN + load capacitance on the board) x.6 [sec] RIN: Pull up resistance Max. value CIN: Terminal capacitance Max. value Mask option In the SC8F36, the input port specification is fixed at "Input with pull-up resistor". Kxx KxxD Data bus Address VSS Fig Structure of input port 46 EPSON SC8F36 TECHNICAL MANUAL

59 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports) Interrupt function and input comparison register Input port KK7, K and K are all equipped with an interrupt function. These input ports are divided into three groupings: KK3 (KL), K4 K7 (KH) and KK (K). Furthermore, the interrupt generation condition for each series of terminals can be set by software. When the interrupt generation condition set for each series of terminals is met, the interrupt factor flag FKL, FKH or FK corresponding to the applicable series is set at "" and an interrupt is generated. K Input comparison register KCP Address Address K K2 K3 Input port KD Interrupt selection register SIK Interrupt can be prohibited by setting the interrupt enable registers EKL, EKH and EK for the corresponding interrupt factor flags. Furthermore, the priority level for input interrupt can be set at the desired level (3) using the interrupt priority registers PKPK and PK PK corresponding to each of two groups Kx (KK7) and Kx (KK). For details on the interrupt control registers for the above and on operations subsequent to interrupt generation, see "5.7 Interrupt and Standby Status". The exception processing vectors for each interrupt factor are set as follows: K and K input interrupt: AH K4K7 input interrupt: CH KK3 input interrupt: EH Figure shows the configuration of the input interrupt circuit. Interrupt factor flag FKL Address Interrupt enable register EKL Address K4 Interrupt priority register PK, PK Interrupt priority level judgment circuit Interrupt request Input port K4D Address Data bus Input comparison register KCP4 Address Interrupt selection register SIK4 Address K5 K6 K7 Interrupt factor flag FKH Address Interrupt enable register EKH Address K Input port KD Input comparison register KCP Address Interrupt factor flag FK Interrupt selection register SIK Address K Address Interrupt enable register EK Address Interrupt priority level judgment circuit Interrupt priority register PK, PK Address Interrupt request Fig Configuration of input interrupt circuit SC8F36 TECHNICAL MANUAL EPSON 47

60 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports) The interrupt selection registers SIKSIK3, SIK4SIK7 and SIKSIK and input comparison registers KCPKCP3, KCP4KCP7 and KCPKCP for each port are used to set the interrupt generation condition described above. Input port interrupt can be permitted or prohibited by the setting of the interrupt selection register SIK. In contrast to the interrupt enable register EK which masks the interrupt factor for each series of terminals, the interrupt selection register SIK is masks the bit units. The input comparison register KCP selects whether the interrupt for each input port will be generated on the rising edge or the falling edge of input. When the data content of the input terminals in which interrupt has been permitted by the interrupt selection register SIK and the data content of the input comparison register KCP change from a conformity state to a non-conformity state, the interrupt factor flag FK should be set to "" and an interrupt is generated. Figure shows an example of interrupt generation in the series of terminals KL (KK3). Because interrupt has been prohibited for K by the interrupt selection register SIK, with the settings as shown in (2), an interrupt will not be generated. Since K3 is "" in the next settings (3) in the figure, the non-conformity between the input terminal data KK3 where interrupt is permitted and the data from the input comparison registers KCP KCP3 generates an interrupt. In line with the explanation above, since the change in the contents of input data and input comparison registers KCP from a conformity state to a nonconformity state introduces an interrupt generation condition, switching from one non-conformity state to another, as is the case in (4) in the figure, will not generate an interrupt. Consequently, in order to be able to generate a second interrupt, either the input terminal must be returned to a state where its content is once again in conformity with that of the input comparison register KCP, or the input comparison register KCP must be reset. Input terminals for which interrupt is prohibited will not influence an interrupt generation condition. Interrupt is generated in exactly the same way in the other two series of terminals KH (K4K7) and K (K and K). Interrupt selection register SIK3 SIK2 SIK SIK Input comparison register KCP3 KCP2 KCP KCP With the settings shown above, interrupt of KL (KK3) is generated under the condition shown below. () (2) (3) (4) Input port K3 K2 K K3 K2 K K3 K2 K K3 K2 K K K K K (Initial values) Interrupt generation Because interrupt has been prohibited for K, interrupt will be generated when non-conformity occurs between the contents of the three bits KK3 and the three bits input comparison register KCPKCP3. Fig Interrupt generation example in KL (KK3) 48 EPSON SC8F36 TECHNICAL MANUAL

61 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports) Control of input ports Table shows the input port control bits. Table (a) Input port control bits Address Bit Name Function FF5 D7 D6 D5 D4 D3 D2 D D SIK7 SIK6 SIK5 SIK4 SIK3 SIK2 SIK SIK K7 interrupt selection register K6 interrupt selection register K5 interrupt selection register K4 interrupt selection register K3 interrupt selection register K2 interrupt selection register K interrupt selection register K interrupt selection register Interrupt enable Interrupt disable FF5 D7 D6 D5 D4 D3 D2 D SIK K interrupt selection register Interrupt Interrupt D SIK K interrupt selection register enable disable FF52 D7 KCP7 K7 interrupt comparison register D6 KCP6 K6 interrupt comparison register D5 KCP5 K5 interrupt comparison register Interrupt Interrupt D4 KCP4 K4 interrupt comparison register generated generated D3 KCP3 K3 interrupt comparison register at falling at rising D2 KCP2 K2 interrupt comparison register edge edge D KCP K interrupt comparison register D KCP K interrupt comparison register FF53 D7 D6 D5 D4 D3 D2 D KCP K interrupt comparison register Falling Rising D KCP K interrupt comparison register edge edge FF54 D7 K7D K7 input port data D6 K6D K6 input port data D5 K5D K5 input port data D4 K4D K4 input port data High level Low level D3 K3D K3 input port data input input D2 K2D K2 input port data D KD K input port data D KD K input port data FF55 D7 D6 D5 D4 D3 D2 D D KD KD K input port data K input port data High level input Low level input SR R R Comment Constantly "" when being read Constantly "" when being read Constantly "" when being read SC8F36 TECHNICAL MANUAL EPSON 49

62 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports) Table (b) Input port control bits Address Bit Name Function SR FF2 D7 D6 D5 D4 D3 D2 D D PK PK PSIF PSIF PSW PSW PTM PTM FF2 D7 D6 D5 D4 D3 PPT D2 PPT D PK D PK FF23 D7 EPT D6 EPT D5 EK D4 EKH D3 EKL D2 ESERR D ESREC D ESTRA FF25 D7 FPT D6 FPT D5 FK D4 FKH D3 FKL D2 FSERR D FSREC D FSTRA KK7 interrupt priority register Serial interface interrupt priority register Stopwatch timer interrupt priority register Clock timer interrupt priority register Programmable timer interrupt priority register K and K interrupt priority register Programmable timer interrupt enable register Programmable timer interrupt enable register K and K interrupt enable register K4K7 interrupt enable register KK3 interrupt enable register Serial I/F (error) interrupt enable register Serial I/F (receiving) interrupt enable register Serial I/F (transmitting) interrupt enable register Programmable timer interrupt factor flag Programmable timer interrupt factor flag K and K interrupt factor flag K4K7 interrupt factor flag KK3 interrupt factor flag Serial I/F (error) interrupt factor flag Serial I/F (receiving) interrupt factor flag Serial I/F (transmitting) interrupt factor flag PK PK PSIF PSIF PSW PSW PTM PTM PPT PK Interrupt enable PPT PK (R) Interrupt factor is generated (W) Reset Priority level Level 3 Level 2 Level Level Priority level Level 3 Level 2 Level Level Interrupt disable (R) No interrupt factor is generated (W) No operation Comment Constantly "" when being read KDK7D: FF54H KD, KD: FF55H D, D Input data of input port terminal Kxx can be read out. When "" is read: HIGH level When "" is read: LOW level Writing: Invalid The terminal voltage of each of the input port K K7, K and K can be directly read out as either a "" for HIGH (VDD) level or a "" for LOW (VSS) level. This bit is exclusively for readout and are not usable for write operations. SIKSIK7: FF5H SIK, SIK: FF5H D, D Sets the interrupt generation condition (interrupt permission/prohibition) for input port terminals KK7, K and K. When "" is written: Interrupt permitted When "" is written: Interrupt prohibited Reading: Valid SIKxx is the interrupt selection register which correspond to the input port Kxx. A "" setting permits interrupt in that input port and a "" prohibits it. Changes of state in an input terminal in which interrupt is prohibited, will not influence interrupt generation. At initial reset, this register is set to "" (interrupt prohibited). 5 EPSON SC8F36 TECHNICAL MANUAL

63 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports) KCPKCP7: FF52H KCP, KCP: FF53H D, D Sets the interrupt generation condition (interrupt generation timing) for input port terminals K K7, K and K. When "" is written: Falling edge When "" is written: Rising edge Reading: Valid KCPxx is the input comparison register which correspond to the input port Kxx. Interrupt in those ports which have been set to "" is generated on the falling edge of the input and in those set to "" on the rising edge. At initial reset, this register is set to "" (falling edge). PK, PK: FF2H D6, D7 PK, PK: FF2H D, D Sets the input interrupt priority level. The two bits PK and PK are the interrupt priority registers corresponding to the interrupts for KK7 (KL and KH). Corresponding to KK (K), the two bits PK and PK perform the same function. Table shows the interrupt priority level which can be set by this register. Table Interrupt priority level settings PK PK PK PK Interrupt priority level Level 3 (IRQ3) Level 2 (IRQ2) Level (IRQ) Level (None) At initial reset, this register is set to "" (level ). EKL, EKH, EK: FF23H D3, D4, D5 How interrupt generation to the CPU is permitted or prohibited. When "" is written: Interrupt permitted When "" is written: Interrupt prohibited Reading: Valid The interrupt enable register EKL corresponds to KK3, EKH to K4K7, and EK to KK. Interrupt is permitted in those series of terminals set to "" and prohibited in those set to "". At initial reset, this register is set to "" (interrupt prohibited). FKL, FKH, FK: FF25H D3, D4, D5 Indicates the generation state for an input interrupt. When "" is read: Interrupt factor present When "" is read: Interrupt factor not present When "" is written: Reset factor flag When "" is written: Invalid The interrupt factor flag FKL corresponds to K K3, FKH to K4K7, and FK to KK and they are set to "" by the occurrence of an interrupt generation condition. When set in this manner, if the corresponding interrupt enable register is set to "" and the corresponding interrupt priority register is set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag will be set to "" by the occurrence of an interrupt generation condition. To accept the subsequent interrupt after interrupt generation, re-setting of the interrupt flags (set interrupt flag to lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and interrupt factor flag reset are necessary. The interrupt factor flag is reset to "" by writing "". At initial reset, this flag is all reset to "" Programming note When changing the input terminal from LOW level to HIGH with the built-in pull-up resistor, a delay in the waveform rise time will occur depending on the time constant of the pull-up resistor and the load capacitance of the terminal. It is necessary to set an appropriate wait time for introduction of an input port. In particular, special attention should be paid to key scan for key matrix formation. Make this wait time the amount of time or more calculated by the following expression. Wait time = RIN x (CIN + load capacitance on the board) x.6 [sec] RIN: Pull up resistance Max. value CIN: Terminal capacitance Max. value SC8F36 TECHNICAL MANUAL EPSON 5

64 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports) 5.6 Output Ports (R ports) 5.6. Configuration of output ports The SC8F36 is equipped with a 34-bit output port (RR7, RR7, R2R27, R3R37, R5, R5). Depending on the bus mode setting, the configuration of the output ports may vary as shown in the table below. Table Configuration of output ports Terminal Bus mode Single chip Expanded 64K Expanded 52K R Output port R Address A R Output port R Address A R2 Output port R2 Address A2 R3 Output port R3 Address A3 R4 Output port R4 Address A4 R5 Output port R5 Address A5 R6 Output port R6 Address A6 R7 Output port R7 Address A7 R Output port R Address A8 R Output port R Address A9 R2 Output port R2 Address A R3 Output port R3 Address A R4 Output port R4 Address A2 R5 Output port R5 Address A3 R6 Output port R6 Address A4 R7 Output port R7 Address A5 R2 Output port R2 Address A6 R2 Output port R2 Address A7 R22 Output port R22 Address A8 R23 Output port R23 RD signal R24 Output port R24 WR signal R25 Output port R25 R26 Output port R26 R27 Output port R27 R3 Output port R3 Output port R3/CE signal R3 Output port R3 Output port R3/CE signal R32 Output port R32 Output port R32/CE2 signal R33 Output port R33 Output port R33/CE3 signal R34 Output port R34 R35 Output port R35 R36 Output port R36 R37 Output port R37 R5 Output port R5 R5 Output port R5 Output port R5/BACK signal Only the configuration of the output ports in single chip mode will be discussed here. With respect to bus control, see "5.2 System Controller and Bus Control". Figure shows the basic structure (excluding special output circuits) of the output ports. Data bus Address High impedance control register Data register Address VDD VSS Rxx Fig Structure of output ports In modes other than single chip mode, the data registers and high impedance control registers of the output ports used for bus function can be used as general purpose registers with read/write capabilities. This will not in any way affect bus signal output. The output specification of each output port is as complementary output with high impedance control in software possible. Besides normal DC output, output ports R25R27, R34, R5 and R5 have a special output function, which can be selected by software and mask option. Note: If an output terminal (including a special output terminal) of this IC is used to drive an external component that consumes a large amount of current such as a bipolar transistor, design the pattern of traces on the printed circuit board so that the operation of the external component does not affect the IC power supply. Refer to <Output Terminals> in Section 8.4, "Precautions on Mounting", for more information Mask option Output specification In the SC8F36, the output specification of all the output ports is fixed at complementary output. R26 and R5 port specifications (for SC888xx) The mask option allows selection of special outputs for the R26 and R5 output ports as well as the DC/FR output (R26) or DC/BACK output (R5). The R26 port can be set as the TOUT output port (TOUT signal inverted output) and the R5 port can be set as the BZ output port (buzzer signal inverted output). 52 EPSON SC8F36 TECHNICAL MANUAL

65 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports) High impedance control The output port can be high impedance controlled in software. This makes it possible to share output signal lines with an other external device. A high impedance control register is set for each series of output port terminals as shown below. Either complementary output and high impedance state can be selected with this register. Table Correspondence between output ports and high impedance control registers Register Output port terminal HZRL HZRH HZRL HZRH HZR2 HZR2 HZR22 HZR23 HZR24 HZR25 HZR26 HZR27 HZR3 HZR3 HZR32 HZR33 HZR34 HZR35 HZR36 HZR37 HZR4L HZR4H HZR5 HZR5 * * * This is a 2-bit reserved register, it can be used as a general purpose register with read/write capabilities. When a high impedance control register HZRxx is set to "", the corresponding output port terminal becomes high impedance state and when set to "", it becomes complementary output DC output RR3 R4R7 RR3 R4R7 R2 R2 R22 R23 R24 R25 R26 R27 R3 R3 R32 R33 R34 R35 R36 R37 R5 R5 As Figure shows, when "" is written to the output port data register, the output terminal switches to HIGH (VDD) level and when "" is written it switches to LOW (VSS) level. When output is in a high impedance state, the data written to the data register is output from the terminal at the instant when output is switched to complementary Special output Besides normal DC output, output ports R25R27, R34, R5 and R5 can also be assigned special output functions in software or mask option as shown in Table Table Special output ports Output port Special output R25 CL output (Software selection) R26 FR/TOUT output (Mask option selection) R27 TOUT output (Software selection) R34 FOUT output (Software selection) R5 BZ output (Software selection) R5 BZ output (Mask option selection) <Special Outputs for SC883xx> The following special outputs are available when a mask option compatible with the SC883xx is selected. CL and FR output (R25 and R26) In order for the SC8F36 to handle connection to an externally expanded LCD driver, output ports R25 and R26 can be used to output a CL signal (LCD synchronous signal) and FR signal (LCD frame signal), respectively. The configuration of output ports R25 and R26 are shown in Figure Register LCCLK Register R25D CL signal Register LCFRM Register R26D FR signal Fig Configuration of R25 and R26 R25 output R26 output The output control for the CL signal is done by the register LCCLK. When you set "" for the LCCLK, the CL signal is output from the output port terminal R25, when "" is set, the HIGH (VDD) level is output. At this time, "" must always be set for the data register R25D. The output control for the FR signal is done by the register LCFRM. When you set "" for the LCFRM, the FR signal is output from the output port terminal R26, when "" is set, the HIGH (VDD) level is output. At this time, "" must always be set for the data register R26D. The frequencies of each signal are changed as shown in Table according to the drive duty selection. SC8F36 TECHNICAL MANUAL EPSON 53

66 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports) Table Frequencies of CL and FR signals Drive duty /32 /6 /8 CL signal (Hz) 2,48,24,24 FR signal (Hz) Since the signals are generated asynchronously from the registers LCCLK and LCFRM, when the signals are turned ON or OFF by the register settings, a hazard of a /2 cycle or less is generated. Figure shows the output waveforms of the CL and FR signals. LCCLK/LCFRM CL output (R25) FR output (R26) Fig Output waveforms of CL and FR signals (when /6 duty is selected) TOUT output (R27) In order for the SC8F36 to provide clock signal to an external device, the output port terminal R27 can be used to output a TOUT signal (clock output by the programmable timer). The configuration of output port R27 is shown in Figure Register PTOUT Register R27D R27 output TOUT signal Fig Configuration of R27 The output control for the TOUT signal is done by the register PTOUT. When you set "" for the PTOUT, the TOUT signal is output from the output port terminal R27, when "" is set, the HIGH (VDD) level is output. At this time, "" must always be set for the data register R27D. The TOUT signal is the programmable timer underflow divided by /2. With respect to frequency control, see "5. Programmable Timer". Since the TOUT signal is generated asynchronously from the register PTOUT, when the signal is turned ON or OFF by the register settings, a hazard of a / 2 cycle or less is generated. Figure shows the output waveform of the TOUT signal. PTOUT TOUT output (R27) Fig Output waveform of TOUT signal FOUT output (R34) In order for the SC8F36 to provide clock signal to an external device, a FOUT signal (oscillation clock fosc or fosc3 dividing clock) can be output from the output port terminal R34. Figure shows the configuration of output port R34. Register FOUTON FOUT signal Register R34D R34 output Fig Configuration of R34 The output control for the FOUT signal is done by the register FOUTON. When you set "" for the FOUTON, the FOUT signal is output from the output port terminal R34, when "" is set, the HIGH (VDD) level is output. At this time, "" must always be set for the data register R34D. The frequency of the FOUT signal can be selected in software by setting the registers FOUTFOUT2. The frequency is selected any one from among eight settings as shown in Table Table FOUT frequency setting FOUT2 FOUT FOUT FOUT frequency fosc / fosc / 2 fosc / 4 fosc / 8 fosc3 / fosc3 / 2 fosc3 / 4 fosc3 / 8 fosc: OSC oscillation frequency fosc3: OSC3 oscillation frequency When the FOUT frequency is made "fosc3/n", you must turn on the OSC3 oscillation circuit before outputting FOUT. A time interval of several msec to several msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes, is necessary, due to the oscillation element that is used. Consequently, if an abnormality occurs as the result of an unstable FOUT signal being output externally, you should allow an adequate waiting time after turning ON of the OSC3 oscillation, before turning outputting FOUT. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter, "ELEC- TRICAL CHARACTERISTICS".) At initial reset, OSC3 oscillation circuit is set to OFF state. 54 EPSON SC8F36 TECHNICAL MANUAL

67 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports) Since the FOUT signal is generated asynchronously from the register FOUTON, when the signal is turned ON or OFF by the register settings, a hazard of a /2 cycle or less is generated. Figure shows the output waveform of the FOUT signal. FOUTON FOUT output (R34) Fig Output waveform of FOUT signal BZ output (R5) In order for the SC8F36 to drive an external buzzer, a BZ signal (sound generator output) can be output from the output port terminal R5. The configuration of the output port R5 is shown in Figure Register BZSHT Register BZSTP One-shot time up Register BZON Register R5D Fig Configuration of R5 The output control for the BZ signal is done by the registers BZON, BZSHT and BZSTP. When you set "" for the BZON or BZSHT, the BZ signal is output from the output port terminal R5, when "" is set for the BZON or "" is set for the BZSTP, the LOW (VSS) level is output. At this time, "" must always be set for the data register R5D. The BZ signal which is output makes use of the output of the sound generator. With respect to control of frequency and envelope, see "5.3 Sound Generator". Since the BZ signal is generated asynchronously from the registers BZON, BZSHT and BZSTP, when the signal is turned ON or OFF by the register settings, a hazard of a /2 cycle or less is generated. Figure shows the output waveform of the BZ signal. BZON/BZSHT BZ signal BZ output (R5) S R Q Fig Output waveform of BZ signal R5 output <Special Outputs for SC888xx> The following special outputs are available when a mask option compatible with the SC888xx is selected. TOUT output (R27), TOUT output (R26) In order for the SC8F36 to provide clock signal to an external device, the R27 output port terminal can be used to output a TOUT signal (clock output by the programmable timer). Furthermore, the R26 output port terminal can be used to output a TOUT signal (TOUT inverted signal). The configuration of the output ports R26 and R27 is shown in Figure Register R27D Register PTOUT TOUT signal Register R26D Mask option R27 output R26 output Fig Configuration of R26 and R27 The output control for the TOUT (TOUT) signals is done by the register PTOUT. When you set "" for the PTOUT, the TOUT (TOUT) signal is output from the R27 (R26) output port terminal. When "" is set, the R27 goes HIGH (VDD) and the R26 goes LOW (VSS). To output the TOUT signal, "" must always be set for the data register R27D. The data register R26D does not affect the TOUT output. The TOUT signal is generated from the programmable timer underflow signal by halving the frequency. With respect to frequency control, see "5. Programmable Timer". Since the TOUT (TOUT) signal is generated asynchronously from the register PTOUT, when the signal is turned ON or OFF by setting the register, a hazard of a /2 cycle or less is generated. Figure shows the output waveform of the TOUT (TOUT) signal. PTOUT TOUT output (R27) TOUT output (R26) * when selected by mask option Fig TOUT (TOUT) output waveform Note: When the mask option that does not support the TOUT output for R26 is selected, R26 and R27 can be used for the FR and CL outputs, respectively (see <Special Outputs for SC883xx>). SC8F36 TECHNICAL MANUAL EPSON 55

68 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports) FOUT output (R34) In order for the SC8F36 to provide clock signal to an external device, a FOUT signal (divided clock of oscillation clock fosc or fosc3) can be output from the output port terminal R34. Figure shows the configuration of output port R34. Register FOUTON FOUT signal Register R34D R34 output Fig Configuration of R34 The output control for the FOUT signal is done by the register FOUTON. When you set "" for the FOUTON, the FOUT signal is output from the output port terminal R34, when "" is set, the HIGH (VDD) level is output. At this time, "" must always be set for the data register R34D. The frequency of the FOUT signal can be selected in software by setting the registers FOUTFOUT2. The frequency is selected any one from among eight settings as shown in Table Table FOUT frequency setting FOUT2 FOUT FOUT FOUT frequency fosc / fosc / 2 fosc / 4 fosc / 8 fosc3 / fosc3 / 2 fosc3 / 4 fosc3 / 8 fosc: OSC oscillation frequency fosc3: OSC3 oscillation frequency When the FOUT frequency is made "fosc3/n", you must turn on the OSC3 oscillation circuit before outputting FOUT. A time interval of several µsec to several msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes, is necessary, due to the oscillation element that is used. Consequently, if an abnormality occurs as the result of an unstable FOUT signal being output externally, you should allow an adequate waiting time after turning ON of the OSC3 oscillation, before turning outputting FOUT. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter, "ELECTRICAL CHARACTERISTICS".) At initial reset, OSC3 oscillation circuit is set to OFF state. Since the FOUT signal is generated asynchronously from the register FOUTON, when the signal is turned ON or OFF by the register settings, a hazard of a /2 cycle or less is generated. Figure shows the output waveform of the FOUT signal. FOUTON FOUT output (R34) Fig Output waveform of FOUT signal BZ output (R5), BZ output (R5) In order for the SC8F36 to drive an external buzzer, a BZ signal (sound generator output) can be output from the output port terminal R5. Furthermore, the R5 output port terminal can be used to output a BZ signal (BZ inverted signal). The configuration of the output ports R5 and R5 is shown in Figure Register BZSHT Register BZSTP One-shot time up Register BZON Register R5D BZ signal Register R5D S R Q Mask option R5 output R5 output Fig Configuration of R5 and R5 The output control for the BZ (BZ) signal is done by the registers BZON, BZSHT and BZSTP. When you set "" for the BZON or BZSHT, the BZ (BZ) signal is output from the output port terminal R5 (R5). When "" is set for the BZON or "" is set for the BZSTP, the R5 goes LOW (VSS) and the R5 goes HIGH (VDD). To output the BZ signal, "" must always be set for the data register R5D. The data register R5D does not affect the BZ output. The BZ (BZ) signal is generated by the sound generator. With respect to control of frequency and envelope, see "5.3 Sound Generator". Since the BZ (BZ) signal is generated asynchronously from the registers BZON, BZSHT and BZSTP, when the signal is turned ON or OFF by setting the registers, a hazard of a /2 cycle or less is generated. Figure shows the output waveform of the BZ (BZ) signal. BZON/BZSHT BZ output (R5) BZ output (R5) * when selected by mask option Fig BZ (BZ) output waveform 56 EPSON SC8F36 TECHNICAL MANUAL

69 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports) Control of output ports Table shows the output port control bits. Table (a) Output port control bits Address Bit Name Function SR Comment FF7 D7 D6 HZR5 HZR5 R5 high impedance control R5 high impedance control High impedance Complementary D5 D4 HZR4H HZR4L register register Reserved register D3 HZRH R4R7 high impedance control D2 D HZRL HZRH RR3 high impedance control R4R7 high impedance control High impedance Complementary D HZRL RR3 high impedance control FF7 D7 HZR27 R27 high impedance control D6 HZR26 R26 high impedance control D5 HZR25 R25 high impedance control D4 D3 HZR24 HZR23 R24 high impedance control R23 high impedance control High impedance Complementary D2 HZR22 R22 high impedance control D HZR2 R2 high impedance control D HZR2 R2 high impedance control FF72 D7 HZR37 R37 high impedance control D6 HZR36 R36 high impedance control D5 HZR35 R35 high impedance control D4 D3 HZR34 HZR33 R34 high impedance control R33 high impedance control High impedance Complementary D2 HZR32 R32 high impedance control D HZR3 R3 high impedance control D HZR3 R3 high impedance control FF73 D7 R7D R7 output port data D6 R6D R6 output port data D5 R5D R5 output port data D4 D3 R4D R3D R4 output port data R3 output port data High Low D2 R2D R2 output port data D RD R output port data D RD R output port data FF74 D7 R7D R7 output port data D6 R6D R6 output port data D5 R5D R5 output port data D4 D3 R4D R3D R4 output port data R3 output port data High Low D2 R2D R2 output port data D RD R output port data D RD R output port data FF75 D7 R27D R27 output port data D6 R26D R26 output port data D5 R25D R25 output port data D4 D3 R24D R23D R24 output port data R23 output port data High Low D2 R22D R22 output port data D R2D R2 output port data D R2D R2 output port data SC8F36 TECHNICAL MANUAL EPSON 57

70 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports) Table (b) Output port control bits Address Bit Name Function SR FF76 D7 R37D R37 output port data D6 R36D R36 output port data D5 R35D R35 output port data D4 R34D R34 output port data D3 R33D R33 output port data High Low D2 R32D R32 output port data D R3D R3 output port data D R3D R3 output port data FF77 D7 D6 D5 R47D R46D R45D register register register D4 R44D register D3 R43D register D2 D D R42D R4D R4D register register register FF78 D7 D6 D5 D4 D3 D2 D D R5D R5D R5 output port data R5 output port data FF D7 D6 D5 D4 LCCLK CL output control for expanded LCD driver D3 LCFRM FR output control for expanded LCD driver D2 DTFNT LCD dot font selection D LDUTY LCD drive duty selection D SGOUT register FF3 D7 D6 D5 D4 MODE6 8/6-bit mode selection D3 CHSEL TOUT output channel selection D2 PTOUT TOUT output control D CKSEL Prescaler source clock selection D CKSEL Prescaler source clock selection High Low High Low On Off On Off 5 x 5 dots 5 x 8 dots /6 duty /32 duty 6-bit x 8-bit x 2 Timer Timer On Off fosc3 fosc fosc3 fosc FF44 D7 D6 BZSTP One-shot buzzer forcibly stop Forcibly stop No operation D5 BZSHT One-shot buzzer trigger/status R W Busy Trigger Ready No operation D4 D3 D2 D D SHTPW ENRTM ENRST ENON BZON One-shot buzzer duration width selection Envelope attenuation time Envelope reset Envelope On/Off control Buzzer output control 25 msec sec Reset On On 3.25 msec.5 sec No operation Off Off W W Comment Reserved register Constantly "" when being read Constantly "" when being read * Reserved register Constantly "" when being read Constantly "" when being read "" when being read *2 * Writing "" to DUTY8 (FF9 D) disables /6 and /32 duty selection using LDUTY (FF D). *2 Reset to "" during one-shot output. 58 EPSON SC8F36 TECHNICAL MANUAL

71 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports) Address Bit FF4 D7 D6 Name FOUT2 Table (c) Output port control bits Function FOUT frequency selection SR Comment "" when being read D5 D4 FOUT FOUT FOUT2 FOUT FOUT Frequency fosc / fosc / 2 fosc / 4 fosc / 8 fosc3 / fosc3 / 2 fosc3 / 4 fosc3 / 8 D3 D2 D D FOUTON WDRST TMRST TMRUN FOUT output control Watchdog timer reset Clock timer reset Clock timer Run/Stop control On Reset Reset Run Off No operation No operation Stop W W Constantly "" when being read High impedance control HZRL, HZRH: FF7H D, D HZRL, HZRH: FF7H D2, D3 HZR2HZR27: FF7H HZR3HZR37: FF72H HZR4L, HZR4H: FF7H D4, D5 * HZR5, HZR5: FF7H D6, D7 Sets the output terminals to a high impedance state. When "" is written: High impedance When "" is written: Complementary Reading: Valid HZRxx is the high impedance control register which correspond as shown in Table to the various output port terminals. When "" is set to the HZRxx register, the corresponding output port terminal becomes high impedance state and when "" is set, it becomes complementary output. At initial reset, this register is set to "" (complementary). * HZR4L and HZR4H is 2-bit reserved register, it can be used as a general purpose register with read/write capabilities. DC output control RDR7D: FF73H RDR7D: FF74H R2DR27D: FF75H R3DR37D: FF76H R4DR47D: FF77H * R5D, R5D: FF78H D, D Sets the data output from the output port terminal Rxx. When "" is written: HIGH level output When "" is written: LOW level output Reading: Valid RxxD is the data register for each output port. When "" is set, the corresponding output port terminal switches to HIGH (VDD) level, and when "" is set, it switches to LOW (VSS) level. At initial reset, R5D is set to "" (LOW level output), all other registers are set to "" (HIGH level output). When R26 and/or R5 are set to the special outputs by mask option, R26D and/or R5D can be used as general-purpose registers that do not affect the output status. The output data registers set for bus signal output can be used as general purpose registers with read/ write capabilities which do not affect the output terminals. * R4DR47D is 8-bit reserved register, it can be used as a general purpose register with read/ write capabilities. SC8F36 TECHNICAL MANUAL EPSON 59

72 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports) Special output control LCCLK: FFH D4 Controls the CL (LCD synchronous) signal output. When "" is written: CL signal output When "" is written: HIGH level (DC) output Reading: Valid LCCLK is the output control register for CL signal. When "" is set, the CL signal is output from the output port terminal R25 and when "" is set, HIGH (VDD) level is output. At this time, "" must always be set for the data register R25D. At initial reset, LCCLK is set to "" (HIGH level output). LCFRM: FFH D3 Controls the FR (LCD frame) signal output. When "" is written: FR signal output When "" is written: HIGH level (DC) output Reading: Valid LCFRM is the output control register for FR signal. When "" is set, the FR signal is output from the output port terminal R26 and when "" is set, HIGH (VDD) level is output. At this time, "" must always be set for the data register R26D. The FR output is not available when the R26 port is not set as the TOUT output port by mask option. At initial reset, LCFRM is set to "" (HIGH level output). PTOUT: FF3H D2 Controls the TOUT (programmable timer output clock) signal output. When "" is written: TOUT signal output ON When "" is written: TOUT signal output OFF Reading: Valid PTOUT is the output control register for TOUT signal. When "" is set to the register, the TOUT (TOUT) signal is output from the output port terminal R27 (R26). When "" is set, the R27 goes HIGH (VDD) and the R26 goes LOW (VSS). To output the TOUT signal, "" must always be set for the data register R27D. The data register R26D does not affect the TOUT output. At initial reset, PTOUT is set to "" (output OFF). The TOUT signal can be output from R26 only when the function is selected by mask option. FOUTON: FF4H D3 Controls the FOUT (fosc/fosc3 dividing clock) signal output. When "" is written: FOUT signal output When "" is written: HIGH level (DC) output Reading: Valid FOUTON is the output control register for FOUT signal. When "" is set, the FOUT signal is output from the output port terminal R34 and when "" is set, HIGH (VDD) level is output. At this time, "" must always be set for the data register R34D. At initial reset, FOUTON is set to "" (HIGH level output). FOUT, FOUT, FOUT2: FF4H D4, D5, D6 FOUT signal frequency is set as shown in Table Table FOUT frequency settings FOUT2 FOUT FOUT FOUT frequency fosc / fosc / 2 fosc / 4 fosc / 8 fosc3 / fosc3 / 2 fosc3 / 4 fosc3 / 8 fosc: OSC oscillation frequency fosc3: OSC3 oscillation frequency At initial reset, this register is set to "" (fosc/). BZON: FF44H D Controls the buzzer (BZ and BZ) signal output. When "" is written: Buzzer signal output ON When "" is written: Buzzer signal output OFF Reading: Valid BZON is the output control register for buzzer signal. When "" is set to the register, the BZ (BZ) signal is output from the output port terminal R5 (R5). When "" is set, the R5 goes LOW (VSS) and the R5 goes HIGH (VDD). To output the BZ signal, "" must always be set for the data register R5D. The data register R5D does not affect the BZ output. At initial reset, BZON is set to "" (output OFF). The BZ signal can be output from R5 only when the function is selected by mask option. 6 EPSON SC8F36 TECHNICAL MANUAL

73 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports) BZSHT: FF45H D5 Controls the one-shot buzzer output. When "" is written: Trigger When "" is written: No operation When "" is read: Busy When "" is read: Ready Writing "" into BZSHT causes the one-shot output circuit to operate. The BZ (BZ) signal is output from the R5 (R5) terminal. The buzzer output is automatically turned OFF after the time set by SHTPW has elapsed. To output the BZ signal, "" must always be set for the data register R5D. The data register R5D does not affect the BZ output. The one-shot output is only valid when the normal buzzer output is OFF (BZON = "") state. The trigger is invalid during ON (BZON = "") state. When a re-trigger is assigned during a one-shot output, the one-shot output time set with SHTPW is measured again from that point. (time extension) The operation status of the one-shot output circuit can be confirmed by reading BZSHT, when the oneshot output is ON, "" is read from BZSHT and when the output is OFF, "" is read. At initial reset, BZSHT is set to "" (ready). The BZ signal can be output from R5 only when the function is selected by mask option. BZSTP: FF45H D6 Forcibly stops the one-shot buzzer output. When "" is written: Forcibly stop When "" is written: No operation Reading: Constantly "" By writing "" into BZSTP, the one-shot buzzer output can be stopped prior to the elapsing of the time set with SHTPW. Writing "" is invalid and writing "" except during one-shot output is also invalid. When "" is written to BZSHT and BZSTP simultaneously, BZSTP takes precedence and one-shot output becomes stop status. Since BZSTP is for writing only, during readout it is constantly set to "" Programming notes () Since the special output signals (CL, FR, TOUT/ TOUT, FOUT and BZ/BZ) are generated asynchronously from the output control registers (LCCLK, LCFRM, PTOUT, FOUTON, BZON, BZSHT and BZSTP), when the signals is turned ON or OFF by the output control register settings, a hazard of a /2 cycle or less is generated. (2) When the FOUT frequency is made "fosc3/n", you must turn on the OSC3 oscillation circuit before outputting FOUT. A time interval of several msec to several msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes, is necessary, due to the oscillation element that is used. Consequently, if an abnormality occurs as the result of an unstable FOUT signal being output externally, you should allow an adequate waiting time after turning ON of the OSC3 oscillation, before turning outputting FOUT. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter, "ELECTRICAL CHAR- ACTERISTICS".) At initial reset, OSC3 oscillation circuit is set to OFF state. (3) The SLP instruction has executed when the special output signals (TOUT/TOUT, FOUT and BZ/BZ) are in the enable status, an unstable clock is output for the special output at the time of return from the SLEEP state. Consequently, when shifting to the SLEEP state, you should set the special output signal to the disable status prior to executing the SLP instruction. SC8F36 TECHNICAL MANUAL EPSON 6

74 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports) 5.7 I/O Ports (P ports) 5.7. Configuration of I/O ports The SC8F36 is equipped with 6 bits of I/O ports (PP7, PP7). The configuration of these I/O ports will vary according to the bus mode as shown below. Table Configuration of I/O ports Terminal Bus mode Single chip Expanded 64K Expanded 52K P P P2 P3 P4 P5 P6 P7 I/O port P I/O port P I/O port P2 I/O port P3 I/O port P4 I/O port P5 I/O port P6 I/O port P7 Data bus D Data bus D Data bus D2 Data bus D3 Data bus D4 Data bus D5 Data bus D6 Data bus D7 P P P2 P3 P4 P5 P6 P7 I/O port P (SIN) I/O port P (SOUT) I/O port P2 (SCLK) I/O port P3 (SRDY) I/O port P4 (CMPP/AD4) I/O port P5 (CMPM/AD5) I/O port P6 (CMPP/AD6) I/O port P7 (CMPM/AD7) With respect to the data bus, see "5.2 System Controller and Bus Control". Figure shows the structure of an I/O port. Data bus * *2 I/O control register Data register Input control *: During output mode *2: During input mode *3: P4P7 have no pull-up resistor VSS Fig Structure of I/O port *3 VDD Pxx Note: If an output of this IC is used to drive an external component that consumes a large amount of current such as a bipolar transistor, design the pattern of traces on the printed circuit board so that the operation of the external component does not affect the IC power supply. Refer to <Output Terminals> in Section 8.4, "Precautions on Mounting", for more information. I/O port can be set for input or output mode in one bit unit. These settings are performed by writing data to the I/O control registers. I/O port terminals PP3 and P4P7 are shared with serial interface input/output terminal and analog comparator/ad input terminals, respectively. The function of each terminals is switchable in software. With respect to serial interface, analog comparator and A/D converter, see "5.8 Serial Interface", "5.4 Analog Comparator" and "5.5 A/D Converter", respectively. The data registers and I/O control registers of I/O ports set for data bus and serial interface output terminals use are usable as general purpose registers with read/write capabilities which do not affect I/O activities of the terminal. The same as above, the I/O control register of I/O port set for serial interface input terminal use is usable as general purpose register. I/O ports PP7 and PP3 are equipped with a pull-up resistor which goes ON in the input mode. When changing the port terminal from LOW level to HIGH with the built-in pull-up resistor, a delay in the waveform rise time will occur depending on the time constant of the pull-up resistor and the load capacitance of the terminal. It is necessary to set an appropriate wait time for introduction of an I/O port. Make this wait time the amount of time or more calculated by the following expression. Wait time = RIN x (CIN + load capacitance on the board) x.6 [sec] RIN: Pull up resistance Max. value CIN: Terminal capacitance Max. value Mask option In the SC8F36, the pull-up option for the PP7 and PP3 ports is fixed at "with pull-up resistor". The P4P7 ports have no pull-up resistor. 62 EPSON SC8F36 TECHNICAL MANUAL

75 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports) I/O control registers and I/O mode I/O ports PP7 and PP7 are set either to input or output modes by writing data to the I/O control registers IOCIOC7 and IOCIOC7 which correspond to each bit. To set an I/O port to input mode, write "" to the I/O control register. An I/O port which is set to input mode will shift to a high impedance state and functions as an input port. Readout in input mode consists simply of a direct readout of the input terminal state: the data being "" when the input terminal is at HIGH (VDD) level and "" when it is at LOW (VSS) level. Even in input mode, data can be written to the data registers without affecting the terminal state. To set an I/O port to output mode, write "" to the I/O control register. An I/O port which is set to output mode functions as an output port. When port output data is "", a HIGH (VDD) level is output and when it is "", a LOW (VSS) level is output. Readout in output mode consists of the contents of the data register. At initial reset, I/O control registers are set to "" (I/O ports are set to input mode) Control of I/O ports Table shows the I/O port control bits. Table I/O port control bits Address Bit Name Function FF6 D7 IOC7 P7 I/O control register D6 IOC6 P6 I/O control register D5 IOC5 P5 I/O control register D4 IOC4 P4 I/O control register D3 IOC3 P3 I/O control register Output Input D2 IOC2 P2 I/O control register D IOC P I/O control register D IOC P I/O control register FF6 D7 D6 D5 IOC7 IOC6 IOC5 P7 I/O control register P6 I/O control register P5 I/O control register D4 IOC4 P4 I/O control register D3 IOC3 P3 I/O control register Output Input D2 D D IOC2 IOC IOC P2 I/O control register P I/O control register P I/O control register FF62 D7 P7D P7 I/O port data D6 P6D P6 I/O port data D5 P5D P5 I/O port data D4 P4D P4 I/O port data D3 P3D P3 I/O port data High Low D2 P2D P2 I/O port data D PD P I/O port data D PD P I/O port data FF63 D7 P7D P7 I/O port data D6 P6D P6 I/O port data D5 P5D P5 I/O port data D4 P4D P4 I/O port data D3 P3D P3 I/O port data High Low D2 P2D P2 I/O port data D PD P I/O port data D PD P I/O port data SR Comment SC8F36 TECHNICAL MANUAL EPSON 63

76 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports) PDP7D: FF62H PDP7D: FF63H How I/O port terminal Pxx data readout and output data settings are performed. When writing data: When "" is written: HIGH level When "" is written: LOW level When the I/O port is set to output mode, the data written is output as is to the I/O port terminal. In terms of port data, when "" is written, the port terminal goes to HIGH (VDD) level and when "" is written to a LOW (VSS) level. Even when the port is in input mode, data can still be written in. When reading out data: When "" is read: HIGH level ("") When "" is read: LOW level ("") When an I/O port is in input mode, the voltage level being input to the port terminal is read out. When terminal voltage is HIGH (VDD), it is read as a "", and when it is LOW (VSS), it is read as a "". Furthermore, in output mode, the contents of the data register are read out. At initial reset, this register is set to "" (HIGH level). Note: The data registers of I/O ports set for the data bus and output terminal of serial interface can be used as general purpose registers with read/write capabilities which do not affect I/O activities of the terminals. IOCIOC7: FF6H IOCIOC7: FF6H Sets the I/O ports to input or output mode. When "" is written: Output mode When "" is written: Input mode Reading: Valid IOCxx is the I/O control register which correspond to each I/O port in a bit unit. Writing "" to the IOCxx register will switch the corresponding I/O port Pxx to output mode, and writing "" will switch it to input mode. When the analog comparator or A/D converter is used, "" must always be set for the I/O control registers (IOC4IOC7) of I/O ports which will become input terminals. At initial reset, this register is set to "" (input mode). Note: The data registers of I/O ports set for the data bus and input terminal of serial interface can be used as general purpose registers with read/write capabilities which do not affect I/O activities of the terminals Programming notes () When changing the port terminal from LOW level to HIGH with the built-in pull-up resistor, a delay in the waveform rise time will occur depending on the time constant of the pull-up resistor and the load capacitance of the terminal. It is necessary to set an appropriate wait time for introduction of an I/O port. Make this wait time the amount of time or more calculated by the following expression. Wait time = RIN x (CIN + load capacitance on the board) x.6 [sec] RIN: Pull up resistance Max. value CIN: Terminal capacitance Max. value (2) When the analog comparator or A/D converter is used, "" must always be set for the I/O control registers (IOC4IOC7) of I/O ports which will become input terminals. 64 EPSON SC8F36 TECHNICAL MANUAL

77 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) 5.8 Serial Interface 5.8. Configuration of serial interface The SC8F36 incorporates a full duplex serial interface (when asynchronous system is selected) that allows the user to select either clock synchronous system or asynchronous system. The data transfer method can be selected in software. When the clock synchronous system is selected, 8- bit data transfer is possible. When the asynchronous system is selected, either 7- bit or 8-bit data transfer is possible, and a parity check of received data and the addition of a parity bit for transmitting data can automatically be done by selecting in software. Figure shows the configuration of the serial interface. Serial interface input/output terminals, SIN, SOUT, SCLK and SRDY are shared with I/O ports PP3. In order to utilize these terminals for the serial interface input/output terminals, proper settings have to be made with registers ESIF, SMD and SMD. (At initial reset, these terminals are set as I/O port terminals.) The direction of I/O port terminals set for serial interface input/output terminals are determined by the signal and transfer mode for each terminal. Furthermore, the settings for the corresponding I/O control registers for the I/O ports become invalid. Table Configuration of input/output terminals Terminal When serial interface is selected P SIN P SOUT P2 SCLK P3 SRDY * The terminals used may vary depending on the transfer mode. SIN and SOUT are serial data input and output terminals which function identically in clock synchronous system and asynchronous system. SCLK is exclusively for use with clock synchronous system and functions as a synchronous clock input/ output terminal. SRDY is exclusively for use in clock synchronous slave mode and functions as a sendreceive ready signal output terminal. When asynchronous system is selected, since SCLK and SRDY are superfluous, the I/O port terminals P2 and P3 can be used as I/O ports. In the same way, when clock synchronous master mode is selected, since SRDY is superfluous, the I/O port terminal P3 can be used as I/O port. Data bus Serial I/O control & status register Received data buffer Error detection circuit Interrupt control circuit Interrupt request SIN(P) Serial input control circuit Received data shift register Transmitting data shift register Serial output control circuit SOUT(P) SCLK(P2) Start bit detection circuit Clock control circuit fosc3 READY output control circuit OSC3 oscillation circuit Programmable timer underflow signal SRDY(P3) Fig Configuration of serial interface SC8F36 TECHNICAL MANUAL EPSON 65

78 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Mask option Since the input/output terminals of the serial interface is shared with the I/O ports (PP3), the terminal specification of the I/O port is also applied to the serial interface. In the SC8F36, the I/O ports (PP3) specification is fixed at "with pull-up resistor". Therefore, a pull-up resistor is provided for the SIN terminal and the SCLK terminal (in slave mode) that are used as input terminals Transfer modes There are four transfer modes for the serial interface and mode selection is made by setting the two bits of the mode selection registers SMD and SMD as shown in the table below. Table Transfer modes SMD SMD Mode Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master Table Terminal settings corresponding to each transfer mode Mode SIN SOUT SCLK SRDY Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master Input Input Input Input Output Output Output Output P2 P2 Input Output P3 P3 Output P3 At initial reset, transfer mode is set to clock synchronous master mode. Clock synchronous master mode In this mode, the internal clock is utilized as a synchronous clock for the built-in shift registers, and clock synchronous 8-bit serial transfers can be performed with this serial interface as the master. The synchronous clock is also output from the SCLK terminal which enables control of the external (slave side) serial I/O device. Since the SRDY terminal is not utilized in this mode, it can be used as an I/O port. Figure (a) shows the connection example of input/output terminals in the clock synchronous master mode. Clock synchronous slave mode In this mode, a synchronous clock from the external (master side) serial input/output device is utilized and clock synchronous 8-bit serial transfers can be performed with this serial interface as the slave. The synchronous clock is input to the SCLK terminal and is utilized by this interface as the synchronous clock. Furthermore, the SRDY signal indicating the transmit-receive ready status is output from the SRDY terminal in accordance with the serial interface operating status. In the slave mode, the settings for registers SCS and SCS used to select the clock source are invalid. Figure (b) shows the connection example of input/output terminals in the clock synchronous slave mode. Asynchronous 7-bit mode In this mode, asynchronous 7-bit transfer can be performed. Parity check during data reception and addition of parity bit (odd/even/none) during transmitting can be specified and data processed in 7 bits with or without parity. Since this mode employs the internal clock, the SCLK terminal is not used. Furthermore, since the SRDY terminal is not utilized either, both of these terminals can be used as I/O ports. Figure (c) shows the connection example of input/output terminals in the asynchronous mode. Asynchronous 8-bit mode In this mode, asynchronous 8-bit transfer can be performed. Parity check during data reception and addition of parity bit (odd/even/none) during transmitting can be specified and data processed in 8 bits with or without parity. Since this mode employs the internal clock, the SCLK terminal is not used. Furthermore, since the SRDY terminal is not utilized either, both of these terminals can be used as I/O ports. Figure (c) shows the connection example of input/output terminals in the asynchronous mode. 66 EPSON SC8F36 TECHNICAL MANUAL

79 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) SC8F36 SIN(P) SOUT(P) SCLK(P2) Input port(kxx) SC8F36 SIN(P) SOUT(P) SCLK(P2) SRDY(P3) External serial device Data input Data output CLOCK input READY output (a) Clock synchronous master mode External serial device Data input Data output CLOCK output READY input (b) Clock synchronous slave mode SC8F36 SIN(P) SOUT(P) (c) Asynchronous 7-bit/8-bit mode Fig Connection examples of serial interface I/O terminals Clock source External serial device Data input Data output There are four clock sources and selection is made by setting the two bits of the clock source selection register SCS and SCS as shown in table below. Table Clock source SCS SCS Clock source Programmable timer fosc3 / 4 fosc3 / 8 fosc3 / 6 This register setting is invalid in clock synchronous slave mode and the external clock input from the SCLK terminal is used. When the "programmable timer" is selected, the programmable timer underflow signal is divided by /2 and this signal used as the clock source. With respect to the transfer rate setting, see "5. Programmable Timer". At initial reset, the synchronous clock is set to "fosc3/6". Whichever clock is selected, the signal is further divided by /6 and then used as the synchronous clock. Furthermore, external clock input is used as is for SCLK in clock synchronous slave mode. Table shows an examples of transfer rates and OSC3 oscillation frequencies when the clock source is set to programmable timer. When the demultiplied signal of the OSC3 oscillation circuit is made the clock source, it is necessary to turn the OSC3 oscillation ON, prior to using the serial interface. A time interval of several msec to several msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes, is necessary, due to the oscillation element that is used. Consequently, you should allow an adequate waiting time after turning ON of the OSC3 oscillation, before starting transmitting/receiving of serial interface. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter, "ELECTRICAL CHARACTERISTICS".) At initial reset, the OSC3 oscillation circuit is set to OFF status. Fig Division of the synchronous clock OSC3 oscillation circuit fosc3 /4 /8 Divider /6 Selector /6 Selector Programmable timer /2 underflow signal (Clock synchronous slave mode) SCLK Synchronous clock Table OSC3 oscillation frequencies and transfer rates Transfer rate (bps) 9,6 4,8 2,4, OSC3 oscillation frequency / Programmable timer settings fosc3 = 3.72 MHz fosc3 = 4.68 MHz fosc3 = MHz PSCx (/) (/) (/) (/) (/) (/4) (/4) RLDXx 9H 3H 27H 4FH 9FH 4FH 9FH PSCx (/) (/) (/) (/) (/) (/4) (/4) RLDx EH DH 3BH 77H EFH 77H EFH PSCx (/) (/) (/) (/) (/) (/4) (/4) RLDx FH FH 3FH 7FH FFH 7FH FFH SC8F36 TECHNICAL MANUAL EPSON 67

80 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Transmit-receive control Below is a description of the registers which handle transmit-receive control. With respect to transmitreceive control procedures and operations, please refer to the following sections in which these are discussed on a mode by mode basis. Shift register and received data buffer Exclusive shift registers for transmitting and receiving are installed in this serial interface. Consequently, duplex communication simultaneous transmit and receive is possible when the asynchronous system is selected. Data being transmitted are written to TRXD TRXD7 and converted to serial through the shift register and is output from the SOUT terminal. In the reception section, a received data buffer is installed separate from the shift register. Data being received are input to the SIN terminal and is converted to parallel through the shift register and written to the received data buffer. Since the received data buffer can be read even during serial input operation, the continuous data is received efficiently. However, since buffer functions are not used in clock synchronous mode, be sure to read out data before the next data reception begins. Transmit enable register and transmit control bit For transmitting control, use the transmit enable register TXEN and transmit control bit TXTRG. The transmit enable register TXEN is used to set the transmitting enable/disable status. When "" is written to this register to set the transmitting enable status, clock input to the shift register is enabled and the system is ready to transmit data. In the clock synchronous mode, synchronous clock input/ output from the SCLK terminal is also enabled. The transmit control bit TXTRG is used as the trigger to start transmitting data. Data to be transmitted is written to the transmit data shift register, and when transmitting preparations a recomplete, "" is written to TXTRG whereupon data transmitting begins. When interrupt has been enabled, an interrupt is generated when the transmission is completed. If there is subsequent data to be transmitted it can be sent using this interrupt. In addition, TXTRG can be read as the status. When set to "", it indicates transmitting operation, and "" indicates transmitting stop. For details on timing, see the timing chart which gives the timing for each mode. When not transmitting, set TXEN to "" to disable transmitting status. Receive enable register, receive control bit For receiving control, use the receive enable register RXEN and receive control bit RXTRG. Receive enable register RXEN is used to set receiving enable/disable status. When "" is written into this register to set the receiving enable status, clock input to the shift register is enabled and the system is ready to receive data. In the clock synchronous mode, synchronous clock input/output from the SCLK terminal is also enabled. With the above setting, receiving begins and serial data input from the SIN terminal goes to the shift register. The operation of the receive control bit RXTRG is slightly different depending on whether a clock synchronous system or an asynchronous system is being used. In the clock synchronous system, the receive control bit RXTRG is used as the trigger to start receiving data. When received data has been read and the preparation for next data receiving is completed, write "" into RXTRG to start receiving. (When "" is written to RXTRG in slave mode, SRDY switches to "".) In an asynchronous system, RXTRG is used to prepare for next data receiving. After reading the received data from the received data buffer, write "" into RXTRG to signify that the received data buffer is empty. If "" is not written into RXTRG, the overrun error flag OER will be set to "" when the next receiving operation is completed. (An overrun error will be generated when receiving is completed between reading the received data and the writing of "" to RXTRG.) In addition, RXTRG can be read as the status. In either clock synchronous mode or asynchronous mode, when RXTRG is set to "", it indicates receiving operation and when set to "", it indicates that receiving has stopped. For details on timing, see the timing chart which gives the timing for each mode. When you do not receive, set RXEN to "" to disable receiving status. 68 EPSON SC8F36 TECHNICAL MANUAL

81 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Operation of clock synchronous transfer Clock synchronous transfer involves the transfer of 8-bit data by synchronizing it to eight clocks. The same synchronous clock is used by both the transmitting and receiving sides. When the serial interface is used in the master mode, the clock signal selected using SCS and SCS is further divided by /6 and employed as the synchronous clock. This signal is then sent via the SCLK terminal to the slave side (external serial I/O device). When used in the slave mode, the clock input to the SCLK terminal from the master side (external serial input/output device) is used as the synchronous clock. In the clock synchronous mode, since one clock line (SCLK) is shared for both transmitting and receiving, transmitting and receiving cannot be performed simultaneously. (Half duplex only is possible in clock synchronous mode.) Transfer data is fixed at 8 bits and both transmitting and receiving are conducted with the LSB (bit ) coming first. SCLK Data LSB MSB D D D2 D3 D4 D5 D6 D7 Fig Transfer data configuration using clock synchronous mode Below is a description of initialization when performing clock synchronous transfer, transmitreceive control procedures and operations. With respect to serial interface interrupt, see "5.8.8 Interrupt function". Initialization of serial interface When performing clock synchronous transfer, the following initial settings must be made. () Setting of transmitting/receiving disable To set the serial interface into a status in which both transmitting and receiving are disabled, "" must be written to both the transmit enable register TXEN and the receive enable register RXEN. Fix these two registers to a disable status until data transfer actually begins. (2) Port selection Because serial interface input/output ports SIN, SOUT, SCLK and SRDY are set as I/O port terminals PP3 at initial reset, "" must be written to the serial interface enable register ESIF in order to set these terminals for serial interface use. (3) Setting of transfer mode Select the clock synchronous mode by writing the data as indicated below to the two bits of the mode selection registers SMD and SMD. Master mode: SMD = "", SMD = "" Slave mode: SMD = "", SMD = "" (4) Clock source selection In the master mode, select the synchronous clock source by writing data to the two bits of the clock source selection registers SCS and SCS. (See Table ) This selection is not necessary in the slave mode. Since all the registers mentioned in (2)(4) are assigned to the same address, it's possible to set them all with one instruction. The parity enable register EPR is also assigned to this address, however, since parity is not necessary in the clock synchronous mode, parity check will not take place regardless of how they are set. (5) Clock source control When the master mode is selected and programmable timer for the clock source is selected, set transfer rate on the programmable timer side. (See "5. Programmable Timer".) When the divided signal of OSC3 oscillation circuit is selected for the clock source, be sure that the OSC3 oscillation circuit is turned ON prior to commencing data transfer. (See "5.4 Oscillation Circuits and Operating Mode".) SC8F36 TECHNICAL MANUAL EPSON 69

82 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Data transmit procedure The control procedure and operation during transmitting is as follows. () Write "" in the transmit enable register TXEN and the receive enable register RXEN to reset the serial interface. (2) Write "" in the transmit enable register TXEN to set into the transmitting enable status. (3) Write the transmitting data into TRXD TRXD7. (4) In case of the master mode, confirm the receive ready status on the slave side (external serial input/output device), if necessary. Wait until it reaches the receive ready status. (5) Write "" in the transmit control bit TXTRG and start transmitting. In the master mode, this control causes the synchronous clock to change to enable and to be provided to the shift register for transmitting and output from the SCLK terminal. In the slave mode, it waits for the synchronous clock to be input from the SCLK terminal. The transmitting data of the shift register shifts one bit at a time at each falling edge of the synchronous clock and is output from the SOUT terminal. When the final bit (MSB) is output, the SOUT terminal is maintained at that level, until the next transmitting begins. The transmitting complete interrupt factor flag FSTRA is set to "" at the point where the data transmitting of the shift register is completed. When interrupt has been enabled, a transmitting complete interrupt is generated at this point. Set the following transmitting data using this interrupt. (6) Repeat steps (3) to (5) for the number of bytes of transmitting data, and then set the transmit disable status by writing "" to the transmit enable register TXEN, when the transmitting is completed. Data transmitting TXEN, RXEN TXEN Set transmitting data to TRXDTRXD7 No Receiver ready? In case of master mode Yes TXTRG No FSTRA =? Yes No Transmit complete? Yes TXEN End Fig Transmit procedure in clock synchronous mode 7 EPSON SC8F36 TECHNICAL MANUAL

83 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Data receive procedure The control procedure and operation during receiving is as follows. () Write "" in the receive enable register RXEN and transmit enable register TXEN to reset the serial interface. (2) Write "" in the receive enable register RXEN to set into the receiving enable status. (3) In case of the master mode, confirm the transmit ready status on the slave side (external serial input/output device), if necessary. Wait until it reaches the transmit ready status. (4) Write "" in the receive control bit RXTRG and start receiving. In the master mode, this control causes the synchronous clock to change to enable and is provided to the shift register for receiving and output from the SCLK terminal. In the slave mode, it waits for the synchronous clock to be input from the SCLK terminal. The received data input from the SIN terminal is successively incorporated into the shift register in synchronization with the rising edge of the synchronous clock. At the point where the data of the 8th bit has been incorporated at the final (8th) rising edge of the synchronous clock, the content of the shift register is sent to the received data buffer and the receiving complete interrupt factor flag FSREC is set to "". When interrupt has been enabled, a receiving complete interrupt is generated at this point. (5) Read the received data from TRXDTRXD7 using receiving complete interrupt. (6) Repeat steps (3) to (5) for the number of bytes of receiving data, and then set the receive disable status by writing "" to the receive enable register RXEN, when the receiving is completed. Data receiving RXEN, TXEN RXEN No Transmitter ready? In case of master mode Yes RXTRG No FSREC =? Yes Received data reading from TRXDTRXD7 No Receiving complete? Yes RXEN End Fig Receiving procedure in clock synchronous mode SC8F36 TECHNICAL MANUAL EPSON 7

84 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Transmit/receive ready (SRDY) signal When this serial interface is used in the clock synchronous slave mode (external clock input), an SRDY signal is output to indicate whether or not this serial interface can transmit/receive to the master side (external serial input/output device). This signal is output from the SRDY terminal and when this interface enters the transmit or receive enable (READY) status, it becomes "" (LOW level) and becomes "" (HIGH level) when there is a BUSY status, such as during transmit/receive operation. The SRDY signal changes the "" to "," immediately after writing "" into the transmit control bit TXTRG or the receive control bit RXTRG and returns from "" to "", at the point where the first synchronous clock has been input (falling edge). When you have set in the master mode, control the transfer by inputting the same signal from the slave side using the input port or I/O port. At this time, since the SRDY terminal is not set and instead P3 functions as the I/O port, you can apply this port for said control. Timing chart The timing chart for the clock synchronous system transmission is shown in Figure RXEN TXEN TXTRG (RD) TXTRG (WR) SCLK RXTRG (RD) RXTRG (WR) SCLK SIN D D D2 D3 D4 D5 D6 D7 SOUT Interrupt D D D2 D3 D4 D5 D6 D7 (a) Transmit timing for master mode TRXD 7F st data Interrupt (c) Receive timing for master mode TXEN TXTRG (RD) TXTRG (WR) SCLK RXEN RXTRG (RD) RXTRG (WR) SCLK SIN D D D2 D3 D4 D5 D6 D7 SOUT D D D2 D3 D4 D5 D6 D7 TRXD 7F st data 7F SRDY SRDY Interrupt Interrupt (b) Transmit timing for slave mode (d) Receive timing for slave mode Fig Timing chart (clock synchronous system transmission) 72 EPSON SC8F36 TECHNICAL MANUAL

85 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Operation of asynchronous transfer Asynchronous transfer is a mode that transfers by adding a start bit and a stop bit to the front and the back of each piece of serial converted data. In this mode, there is no need to use a clock that is fully synchronized clock on the transmit side and the receive side, but rather transmission is done while adopting the synchronization at the start/stop bits that have attached before and after each piece of data. The RS-232C interface functions can be easily realized by selecting this transfer mode. This interface has separate transmit and receive shift registers and is designed to permit full duplex transmission to be done simultaneously for transmitting and receiving. For transfer data in the asynchronous 7-bit mode, either 7 bits data (no parity) or 7 bits data + parity bit can be selected. In the asynchronous 8-bit mode, either 8 bits data (no parity) or 8 bits data + parity bit can be selected. Parity can be even or odd, and parity checking of received data and adding a party bit to transmitting data will be done automatically. Thereafter, it is not necessary to be conscious of parity itself in the program. The start bit and stop bit are respectively fixed at one bit and data is transmitted and received by placing the LSB (bit ) at the front. Sampling clock 7bit data 7bit data +parity 8bit data 8bit data +parity s s s D D D2 D3 D4 D5 D6 D D D2 D3 D4 D5 D6 D D D2 D3 D4 D5 D6 D7 p s2 s2 s D D D2 D3 D4 D5 D6 D7 p s2 s : Start bit (Low level, bit) s2 : Stop bit (High level, bit) p : Parity bit s2 Fig Transfer data configuration for asynchronous system Here following, we will explain the control sequence and operation for initialization and transmitting /receiving in case of asynchronous data transfer. See "5.8.8 Interrupt function" for the serial interface interrupts. Initialization of serial interface The below initialization must be done in cases of asynchronous system transfer. () Setting of transmitting/receiving disable To set the serial interface into a status in which both transmitting and receiving are disabled, "" must be written to both the transmit enable register TXEN and the receive enable register RXEN. Fix these two registers to a disable status until data transfer actually begins. (2) Port selection Because serial interface input/output terminals SIN and SOUT are set as I/O port terminals P and P at initial reset, "" must be written to the serial interface enable register ESIF in order to set these terminals for serial interface use. SCLK and SRDY terminals set in the clock synchronous mode are not used in the asynchronous mode. These terminals function as I/O port terminals P2 and P3. (3) Setting of transfer mode Select the asynchronous mode by writing the data as indicated below to the two bits of the mode selection registers SMD and SMD. 7-bit mode: SMD = "", SMD = "" 8-bit mode: SMD = "", SMD = "" (4) Parity bit selection When checking and adding parity bits, write "" into the parity enable register EPR to set to "with parity check". As a result of this setting, in the asynchronous 7-bit mode, it has a 7 bits data + parity bit configuration and in the asynchronous 8-bit mode it has an 8 bits data + parity bit configuration. In this case, parity checking for receiving and adding a party bit for transmitting is done automatically in hardware. Moreover, when "with parity check" has been selected, "odd" or "even" parity must be further selected in the parity mode selection register PMD. When "" is written to the EPR register to select "without parity check" in the asynchronous 7-bit mode, data configuration is set to 7 bits data (no parity) and in the asynchronous 8-bit mode (no parity) it is set to 8 bits data (no parity) and parity checking and parity bit adding will not be done. (5) Clock source selection Select the clock source by writing data to the two bits of the clock source selection registers SCS and SCS. (See Table ) Since all the registers mentioned in (2)(5) are assigned to the same address, it's possible to set them all with one instruction. SC8F36 TECHNICAL MANUAL EPSON 73

86 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) (6) Clock source control When the programmable timer is selected for the clock source, set transfer rate on the programmable timer side. (See "5. Programmable Timer".) When the divided signal of OSC3 oscillation circuit is selected for the clock source, be sure that the OSC3 oscillation circuit is turned ON prior to commencing data transfer. (See "5.4 Oscillation Circuits and Operating Mode".) Data transmit procedure The control procedure and operation during transmitting is as follows. () Write "" in the transmit enable register TXEN to reset the serial interface. (2) Write "" in the transmit enable register TXEN to set into the transmitting enable status. (3) Write the transmitting data into TRXDTRXD7. Also, when 7-bit data is selected, the TRXD7 data becomes invalid. (4) Write "" in the transmit control bit TXTRG and start transmitting. This control causes the shift clock to change to enable and a start bit (LOW) is output to the SOUT terminal in synchronize to its falling edge. The transmitting data set to the shift register is shifted one bit at a time at each falling edge of the clock thereafter and is output from the SOUT terminal. After the data output, it outputs a stop bit (HIGH) and HIGH level is maintained until the next start bit is output. The transmitting complete interrupt factor flag FSTRA is set to "" at the point where the data transmitting is completed. When interrupt has been enabled, a transmitting complete interrupt is generated at this point. Set the following transmitting data using this interrupt. (5) Repeat steps (3) to (4) for the number of bytes of transmitting data, and then set the transmit disable status by writing "" to the transmit enable register TXEN, when the transmitting is completed. Data transmitting TXEN TXEN Set transmitting data to TRXDTRXD7 TXTRG No FSTRA =? Yes No Transmit complete? Yes TXEN End Fig Transmit procedure in asynchronous mode 74 EPSON SC8F36 TECHNICAL MANUAL

87 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Data receive procedure The control procedure and operation during receiving is as follows. () Write "" in the receive enable register RXEN to set the receiving disable status and to reset the respective PER, OER, FER flags that indicate parity, overrun and framing errors. (2) Write "" in the receive enable register RXEN to set into the receiving enable status. (3) The shift clock will change to enable from the point where the start bit (LOW) has been input from the SIN terminal and the receive data will be synchronized to the rising edge following the second clock, and will thus be successively incorporated into the shift register. After data bits have been incorporated, the stop bit is checked and, if it is not HIGH, it becomes a framing error and the error interrupt factor flag FSERR is set to "". When interrupt has been enabled, an error interrupt is generated at this point. When receiving is completed, data in the shift register is transferred to the received data buffer and the receiving complete interrupt flag FSREC is set to "". When interrupt has been enabled, a receiving complete interrupt is generated at this point. (When an overrun error is generated, the interrupt factor flag FSREC is not set to "" and a receiving complete interrupt is not generated.) If "with parity check" has been selected, a parity check is executed when data is transferred into the received data buffer from the shift register and if a parity error is detected, the error interrupt factor flag is set to "". When the interrupt has been enabled, an error interrupt is generated at this point just as in the framing error mentioned above. (4) Read the received data from TRXDTRXD7 using receiving complete interrupt. (5) Write "" to the receive control bit RXTRG to inform that the receive data has been read out. When the following data is received prior to writing "" to RXTRG, it is recognized as an overrun error and the error interrupt factor flag is set to "". When the interrupt has been enabled, an error interrupt is generated at this point just as in the framing error and parity error mentioned above. (6) Repeat steps (3) to (5) for the number of bytes of receiving data, and then set the receive disable status by writing "" to the receive enable register RXEN, when the receiving is completed. Data receiving RXEN Resets error flags PER, OER and FER RXEN Yes Error generated? No No Receiving interrupt? Yes Received data reading Error processing from TRXDTRXD7 RXTRG No Receiving complete? Yes RXEN End Fig Receiving procedure in asynchronous mode SC8F36 TECHNICAL MANUAL EPSON 75

88 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Receive error During receiving the following three types of errors can be detected by an interrupt. () Parity error When writing "" to the EPR register to select "with parity check", a parity check (vertical parity check) is executed during receiving. After each data bit is sent a parity check bit is sent. The parity check bit is a "" or a "". Even parity checking will cause the sum of the parity bit and the other bits to be even. Odd parity causes the sum to be odd. This is checked on the receiving side. The parity check is performed when data received in the shift register is transferred to the received data buffer. It checks whether the parity check bit is a "" or a "" (the sum of the bits including the parity bit) and the parity set in the PMD register match. When it does not match, it is recognized as an parity error and the parity error flag PER and the error interrupt factor flag FSERR are set to "". When interrupt has been enabled, an error interrupt is generated at this point. The PER flag is reset to "" by writing "". Even when this error has been generated, the received data corresponding to the error is transferred in the received data buffer and the receive operation also continues. The received data at this point cannot assured because of the parity error. (2) Framing error In asynchronous transfer, synchronization is adopted for each character at the start bit ("") and the stop bit (""). When receiving has been done with the stop bit set at "", the serial interface judges the synchronization to be off and a framing error is generated. When this error is generated, the framing error flag FER and the error interrupt factor flag FSERR are set to "". When interrupt has been enabled, an error interrupt is generated at this point. The FER flag is reset to "" by writing "". Even when this error has been generated, the received data corresponding to the error is transferred in the received data buffer and the receive operation also continues. However, even when it does not become a framing error with the following data receiving, such data cannot be assured. (3) Overrun error When the next data is received before "" is written to RXTRG, an overrun error will be generated, because the previous receive data will be overwritten. When this error is generated, the overrun error flag OER and the error interrupt factor flag FSERR are set to "". When interrupt has been enabled, an error interrupt is generated at this point. The OER flag is reset to "" by writing "" into it. Even when this error has been generated, the received data corresponding to the error is transferred in the received data buffer and the receive operation also continues. Furthermore, when the timing for writing "" to RXTRG and the timing for the received data transfer to the received data buffer overlap, it will be recognized as an overrun error. Timing chart Figure show the asynchronous transfer timing chart. 76 EPSON SC8F36 TECHNICAL MANUAL

89 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) TXEN TXTRG(RD) TXTRG(WR) Sampling clock SOUT (In 8-bit mode/non parity) Interrupt (a) Transmit timing D D D2 D3 D4 D5 D6 D7 RXEN RXTRG(RD) RXTRG(WR) Sampling clock SIN D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 (In 8-bit mode/non parity) TRXD st data 2nd data OER control signal OER Interrupt (b) Receive timing Fig Timing chart (asynchronous transfer) Interrupt function This serial interface includes a function that generates the below indicated three types of interrupts. Transmitting complete interrupt Receiving complete interrupt Error interrupt The interrupt factor flag FSxxx and the interrupt enable register ESxxx for the respective interrupt factors are provided and then the interrupt enable/ disable can be selected by the software. In addition, a priority level of the serial interface interrupt for the CPU can be optionally set at levels to 3 by the interrupt priority registers PSIF and PSIF. For details on the above mentioned interrupt control register and the operation following generation of an interrupt, see "5.7 Interrupt and Standby Status". Figure shows the configuration of the serial interface interrupt circuit. Transmitting complete interrupt This interrupt factor is generated at the point where the sending of the data written into the shift register has been completed and sets the interrupt factor flag FSTRA to "". When set in this manner, if the corresponding interrupt enable register ESTRA is set to "" and the corresponding interrupt priority registers PSIF and PSIF are set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. When "" has been written into the interrupt enable register ESTRA and interrupt has been disabled, an interrupt is not generated to the CPU. Even in this case, the interrupt factor flag FSTRA is set to "". The interrupt factor flag FSTRA is reset to "" by writing "". The following transmitting data can be set and the transmitting start (writing "" to TXTRG) can be controlled by generation of this interrupt factor. The exception processing vector address for this interrupt factor is set at 4H. SC8F36 TECHNICAL MANUAL EPSON 77

90 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Address Interrupt priority register PSIF, PSIF Error generation Address Interrupt factor flag FSERR Address Interrupt enable register ESERR Data bus Receive completion Address Address Interrupt factor flag FSREC Interrupt enable register ESREC Interrupt priority level judgment circuit Interrupt request Transmit completion Address Interrupt factor flag FSTRA Address Interrupt enable register ESTRA Fig Configuration of serial interface interrupt circuit Receiving complete interrupt This interrupt factor is generated at the point where receiving has been completed and the receive data incorporated into the shift register has been transferred into the received data buffer and it sets the interrupt factor flag FSREC to "". When set in this manner, if the corresponding interrupt enable register ESREC is set to "" and the corresponding interrupt priority registers PSIF and PSIF are set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. When "" has been written into the interrupt enable register ESREC and interrupt has been disabled, an interrupt is not generated to the CPU. Even in this case, the interrupt factor flag FSREC is set to "". The interrupt factor flag FSREC is reset to "" by writing "". The generation of this interrupt factor permits the received data to be read. Also, the interrupt factor flag is set to "" when a parity error or framing error is generated. The exception processing vector address for this interrupt factor is set at 2H. Error interrupt This interrupt factor is generated at the point where a parity error, framing error or overrun error is detected during receiving and it sets the interrupt factor flag FSERR to "". When set in this manner, if the corresponding interrupt enable register ESERR is set to "" and the corresponding interrupt priority registers PSIF and PSIF are set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. When "" has been written in the interrupt enable register ESERR and interrupt has been disabled, an interrupt is not generated to the CPU. Even in this case, the interrupt factor flag FSERR is set to "". The interrupt factor flag FSERR is reset to "" by writing "". Since all three types of errors result in the same interrupt factor, you should identify the error that has been generated by the error flags PER (parity error), OER (overrun error) and FER (framing error). The exception processing vector address for this interrupt factor is set at H. 78 EPSON SC8F36 TECHNICAL MANUAL

91 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Control of serial interface Table show the serial interface control bits. Table (a) Serial interface control bits Address Bit Name Function SR Comment FF48 D7 "" when being read D6 EPR Parity enable register With parity Non parity Only for D5 PMD Parity mode selection Odd Even asynchronous mode D4 SCS Clock source selection SCS SCS Clock source In the clock synchro- Programmable timer nous slave mode, D3 SCS fosc3 / 4 external clock is fosc3 / 8 selected. fosc3 / 6 D2 SMD Serial I/F mode selection SMD SMD Mode Asynchronous 8-bit D SMD Asynchronous 7-bit Clock synchronous slave Clock synchronous master D ESIF Serial I/F enable register Serial I/F I/O port FF49 D7 "" when being read D6 FER Framing error flag R Error No error W Reset () No operation D5 PER Parity error flag R Error No error Only for W Reset () No operation asynchronous mode D4 OER Overrun error flag R Error No error W Reset () No operation D3 RXTRG Receive trigger/status R Run Stop W Trigger No operation D2 RXEN Receive enable Enable Disable D TXTRG Transmit trigger/status R Run Stop W Trigger No operation D TXEN Transmit enable Enable Disable FF4A D7 TRXD7 Transmit/Receive data D7 (MSB) D6 TRXD6 Transmit/Receive data D6 D5 TRXD5 Transmit/Receive data D5 D4 D3 TRXD4 TRXD3 Transmit/Receive data D4 Transmit/Receive data D3 High Low X D2 TRXD2 Transmit/Receive data D2 D TRXD Transmit/Receive data D D FF2 D7 D6 D5 D4 D3 D2 D D TRXD PK PK PSIF PSIF PSW PSW PTM PTM Transmit/Receive data D (LSB) KK7 interrupt priority register Serial interface interrupt priority register Stopwatch timer interrupt priority register Clock timer interrupt priority register PK PK PSIF PSIF PSW PSW PTM PTM Priority level Level 3 Level 2 Level Level SC8F36 TECHNICAL MANUAL EPSON 79

92 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) Table (b) Serial interface control bits Address Bit Name Function SR FF23 D7 EPT Programmable timer interrupt enable register D6 EPT Programmable timer interrupt enable register D5 EK K and K interrupt enable register D4 EKH K4K7 interrupt enable register Interrupt Interrupt D3 EKL KK3 interrupt enable register enable disable D2 ESERR Serial I/F (error) interrupt enable register D ESREC Serial I/F (receiving) interrupt enable register D ESTRA Serial I/F (transmitting) interrupt enable register FF25 D7 FPT Programmable timer interrupt factor flag (R) (R) D6 FPT Programmable timer interrupt factor flag Interrupt No interrupt D5 FK K and K interrupt factor flag factor is factor is D4 FKH K4K7 interrupt factor flag generated generated D3 FKL KK3 interrupt factor flag D2 FSERR Serial I/F (error) interrupt factor flag (W) (W) D FSREC Serial I/F (receiving) interrupt factor flag Reset No operation D FSTRA Serial I/F (transmitting) interrupt factor flag Comment ESIF: FF48H D Sets the serial interface terminals (PP3). When "" is written: Serial input/output terminal When "" is written: I/O port terminal Reading: Valid The ESIF is the serial interface enable register and PP3 terminals become serial input/output terminals (SIN, SOUT, SCLK, SRDY) when "" is written, and they become I/O port terminals when "" is written. Also, see Table for the terminal settings according to the transfer modes. At initial reset, ESIF is set to "" (I/O port). SMD, SMD: FF48H D, D2 Set the transfer modes according to Table Table Transfer mode settings SMD SMD Mode Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master SMD and SMD can also read out. At initial reset, this register is set to "" (clock synchronous master mode). SCS, SCS: FF48H D3, D4 Select the clock source according to Table Table Clock source selection SCS SCS Clock source Programmable timer fosc3 / 4 fosc3 / 8 fosc3 / 6 SCS and SCS can also be read out. In the clock synchronous slave mode, setting of this register is invalid. At initial reset, this register is set to "" (fosc3/6). EPR: FF48H D6 Selects the parity function. When "" is written: With parity When "" is written: Non parity Reading: Valid Selects whether or not to check parity of the received data and to add a parity bit to the transmitting data. When "" is written to EPR, the most significant bit of the received data is considered to be the parity bit and a parity check is executed. A parity bit is added to the transmitting data. When "" is written, neither checking is done nor is a parity bit added. Parity is valid only in asynchronous mode and the EPR setting becomes invalid in the clock synchronous mode. At initial reset, EPR is set to "" (non parity). 8 EPSON SC8F36 TECHNICAL MANUAL

93 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) PMD: FF48H D5 Selects odd parity/even parity. When "" is written: Odd parity When "" is written: Even parity Reading: Valid When "" is written to PMD, odd parity is selected and even parity is selected when "" is written. The parity check and addition of a parity bit is only valid when "" has been written to EPR. When "" has been written to EPR, the parity setting by PMD becomes invalid. At initial reset, PMD is set to "" (even parity). TXEN: FF49H D Sets the serial interface to the transmitting enable status. When "" is written: Transmitting enable When "" is written: Transmitting disable Reading: Valid When "" is written to TXEN, the serial interface shifts to the transmitting enable status and shifts to the transmitting disable status when "" is written. Set TXEN to "" when making the initial settings of the serial interface and similar operations. At initial reset, TXEN is set to "" (transmitting disable). TXTRG: FF49H D Functions as the transmitting start trigger and the operation status indicator (transmitting/stop status). When "" is read: During transmitting When "" is read: During stop When "" is written: Transmitting start When "" is written: Invalid Starts the transmitting when "" is written to TXTRG after writing the transmitting data. TXTRG can be read as the status. When set to "", it indicates transmitting operation, and "" indicates transmitting stop. At initial reset, TXTRG is set to "" (during stop). RXEN: FF49H D2 Sets the serial interface to the receiving enable status. When "" is written: Receiving enable When "" is written: Receiving disable Reading: Valid When "" is written to RXEN, the serial interface shifts to the receiving enable status and shifts to the receiving disable status when "" is written. Set RXEN to "" when making the initial settings of the serial interface and similar operations. At initial reset, RXEN is set to "" (receiving disable). RXTRG: FF49H D3 Functions as the receiving start trigger or preparation for the following data receiving and the operation status indicator (during receiving/during stop). When "" is read: During receiving When "" is read: During stop When "" is written: Receiving start/following data receiving preparation When "" is written: Invalid RXTRG has a slightly different operation in the clock synchronous system and the asynchronous system. The RXTRG in the clock synchronous system, is used as the trigger for the receiving start. Writes "" into RXTRG to start receiving at the point where the receive data has been read and the following receive preparation has been done. (In the slave mode, SRDY becomes "" at the point where "" has been written into into the RXTRG.) RXTRG is used in the asynchronous system for preparation of the following data receiving. Reads the received data located in the received data buffer and writes "" into RXTRG to inform that the received data buffer has shifted to empty. When "" has not been written to RXTRG, the overrun error flag OER is set to "" at the point where the following receiving has been completed. (When the receiving has been completed between the operation to read the received data and the operation to write "" into RXTRG, an overrun error occurs.) In addition, RXTRG can be read as the status. In either clock synchronous mode or asynchronous mode, when RXTRG is set to "", it indicates receiving operation and when set to "", it indicates that receiving has stopped. At initial reset, RXTRG is set to "" (during stop). SC8F36 TECHNICAL MANUAL EPSON 8

94 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) TRXDTRXD7: FF4AH During transmitting Write the transmitting data into the transmit shift register. When "" is written: HIGH level When "" is written: LOW level Write the transmitting data prior to starting transmitting. In the case of continuous transmitting, wait for the transmitting complete interrupt, then write the data. The TRXD7 becomes invalid for the asynchronous 7-bit mode. Converted serial data for which the bits set at "" as HIGH (VDD) level and for which the bits set at "" as LOW (VSS) level are output from the SOUT terminal. During receiving Read the received data. When "" is read: HIGH level When "" is read: LOW level The data from the received data buffer can be read out. Since the sift register is provided separately from this buffer, reading can be done during the receive operation in the asynchronous mode. (The buffer function is not used in the clock synchronous mode.) Read the data after waiting for the receiving complete interrupt. When performing parity check in the asynchronous 7-bit mode, "" is loaded into the 8th bit (TRXD7) that corresponds to the parity bit. The serial data input from the SIN terminal is level converted, making the HIGH (VDD) level bit "" and the LOW (VSS) level bit "" and is then loaded into this buffer. At initial reset, the buffer content is undefined. OER: FF49H D4 Indicates the generation of an overrun error. When "" is read: Error When "" is read: No error When "" is written: Reset to "" When "" is written: Invalid OER is an error flag that indicates the generation of an overrun error and becomes "" when an error has been generated. An overrun error is generated when the receiving of data has been completed prior to the writing of "" to RXTRG in the asynchronous mode. OER is reset to "" by writing "". At initial reset and when RXEN is "", OER is set to "" (no error). PER: FF49H D5 Indicates the generation of a parity error. When "" is read: Error When "" is read: No error When "" is written: Reset to "" When "" is written: Invalid PER is an error flag that indicates the generation of a parity error and becomes "" when an error has been generated. When a parity check is performed in the asynchronous mode, if data that does not match the parity is received, a parity error is generated. PER is reset to "" by writing "". At initial reset and when RXEN is "", PER is set to "" (no error). FER: FF49H D6 Indicates the generation of a framing error. When "" is read: Error When "" is read: No error When "" is written: Reset to "" When "" is written: Invalid FER is an error flag that indicates the generation of a framing error and becomes "" when an error has been generated. When the stop bit for the receiving of the asynchronous mode has become "", a framing error is generated. FER is reset to "" by writing "". At initial reset and when RXEN is "", FER is set to "" (no error). PSIF, PSIF: FF2H D4, D5 Sets the priority level of the serial interface interrupt. The two bits PSIF and PSIF are the interrupt priority register corresponding to the serial interface interrupt. Table shows the interrupt priority level which can be set by this register. Table Interrupt priority level settings PSIF PSIF Interrupt priority level Level 3 (IRQ3) Level 2 (IRQ2) Level (IRQ) Level (None) At initial reset, this register is set to "" (level ). 82 EPSON SC8F36 TECHNICAL MANUAL

95 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface) ESTRA, ESREC, ESERR: FF23H D, D, D2 Enables or disables the generation of an interrupt for the CPU. When "" is written: Interrupt enabled When "" is written: Interrupt disabled Reading: Valid ESTRA, ESREC and ESERR are interrupt enable registers that respectively correspond to the interrupt factors for transmitting complete, receiving complete and receiving error. Interrupts set to "" are enabled and interrupts set to "" are disabled. At initial reset, this register is set to "" (interrupt disabled). FSTRA, FSREC, FSERR: FF25H D, D, D2 Indicates the serial interface interrupt generation status. When "" is read: Interrupt factor present When "" is read: Interrupt factor not present When "" is written: Resets factor flag When "" is written: Invalid FSTRA, FSREC and FSERR are interrupt factor flags that respectively correspond to the interrupts for transmitting complete, receiving complete and receiving error and are set to "" by generation of each factor. Transmitting complete interrupt factor is generated at the point where the data transmitting of the shift register has been completed. Receiving complete interrupt factor is generated at the point where the received data has been transferred into the received data buffer. Receive error interrupt factor is generated when a parity error, framing error or overrun error has been detected during data receiving. When set in this manner, if the corresponding interrupt enable register is set to "" and the corresponding interrupt priority register is set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag will be set to "" by the occurrence of an interrupt generation condition. To accept the subsequent interrupt after interrupt generation, re-setting of the interrupt flags (set interrupt flag to lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and interrupt factor flag reset are necessary. The interrupt factor flag is reset to "" by writing "". At initial reset, this flag is reset to "" Programming notes () Be sure to initialize the serial interface mode in the transmitting/receiving disable status (TXEN = RXEN = ""). (2) Do not perform double trigger (writing "") to TXTRG (RXTRG) when the serial interface is in the transmitting (receiving) operation. Furthermore, do not execute the SLP instruction. (When executing the SLP instruction, set TXEN = RXEN = "".) (3) In the clock synchronous mode, since one clock line (SCLK) is shared for both transmitting and receiving, transmitting and receiving cannot be performed simultaneously. (Half duplex only is possible in clock synchronous mode.) Consequently, be sure not to write "" to RXTRG (TXTRG) when TXTRG (RXTRG) is "". (4) When a parity error or framing error is generated during receiving in the asynchronous mode, the receiving error interrupt factor flag FSERR is set to "" prior to the receiving complete interrupt factor flag FSREC for the time indicated in Table Consequently, when an error is generated, you should reset the receiving complete interrupt factor flag FSREC to "" by providing a wait time in error processing routines and similar routines. When an overrun error is generated, the receiving complete interrupt factor flag FSREC is not set to "" and a receiving complete interrupt is not generated. Table Time difference between FSERR and FSREC on error generation Clock source Time difference fosc3 / n /2 cycles of fosc3 / n Programmable timer cycle of timer underflow (5) When the demultiplied signal of the OSC3 oscillation circuit is made the clock source, it is necessary to turn the OSC3 oscillation ON, prior to using the serial interface. A time interval of several msec to several msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes, is necessary, due to the oscillation element that is used. Consequently, you should allow an adequate waiting time after turning ON of the OSC3 oscillation, before starting transmitting/receiving of serial interface. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter, "ELECTRICAL CHARACTERISTICS".) At initial reset, the OSC3 oscillation circuit is set to OFF status. SC8F36 TECHNICAL MANUAL EPSON 83

96 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Clock Timer) 5.9 Clock Timer 5.9. Configuration of clock timer The SC8F36 has built in a clock timer that uses the OSC oscillation circuit as clock source. The clock timer is composed of an 8-bit binary counter that uses the 256 Hz signal dividing fosc as its input clock and can read the data of each bit (28 Hz) by software. Normally, this clock timer is used for various timing functions such as clocks. The configuration of the clock timer is shown in Figure Interrupt function The clock timer can generate an interrupt by each of the 32 Hz, 8 Hz, 2 Hz and Hz signals. The configuration of the clock timer interrupt circuit is shown in Figure Interrupts are generated by respectively setting the corresponding interrupt factor flags FTM32, FTM8, FTM2 and FTM at the falling edge of the 32 Hz, 8 Hz, 2 Hz and Hz signals to "". Interrupt can be prohibited by the setting the interrupt enable registers ETM32, ETM8, ETM2 and ETM corresponding to each interrupt factor flag. In addition, a priority level of the clock timer interrupt for the CPU can be optionally set at levels to 3 by the interrupt priority registers PTM and PTM. For details on the above mentioned interrupt control register and the operation following generation of an interrupt, see "5.7 Interrupt and Standby Status". The exception processing vector addresses for each interrupt factor are respectively set as shown below. 32 Hz interrupt: CH 8 Hz interrupt: EH 2 Hz interrupt: 2H Hz interrupt: 22H Figure shows the timing chart for the clock timer. Data bus OSC oscillation circuit fosc Divider 256 Hz Clock timer 28 Hz 64 Hz 32 Hz 6 Hz 8 Hz TMDTMD7 4 Hz 2 Hz Hz TMRST TMRUN Clock timer reset Clock timer Run/Stop Interrupt control circuit Interrupt request Fig Configuration of clock timer 84 EPSON SC8F36 TECHNICAL MANUAL

97 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Clock Timer) Address Interrupt priority register PTM, PTM 32 Hz falling edge Address Interrupt factor flag FTM32 Address Interrupt enable register ETM32 8 Hz falling edge Address Interrupt factor flag FTM8 Data bus Address 2 Hz falling edge Address Interrupt enable register ETM8 Interrupt factor flag FTM2 Interrupt priority level judgment circuit Interrupt request Address Interrupt enable register ETM2 Hz falling edge Address Interrupt factor flag FTM Address Interrupt enable register ETM Fig Configuration of clock timer interrupt circuit OSC/ Hz TMD 28 Hz TMD 64 Hz TMD2 32 Hz TMD3 6 Hz TMD4 8 Hz TMD5 4 Hz TMD6 2 Hz TMD7 Hz 32 Hz interrupt 8 Hz interrupt 2 Hz interrupt Hz interrupt Fig Timing chart of clock timer SC8F36 TECHNICAL MANUAL EPSON 85

98 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Clock Timer) Control of clock timer Table shows the clock timer control bits. Table Clock timer control bits Address Bit Name Function SR Comment FF4 D7 D6 FOUT2 FOUT frequency selection "" when being read D5 D4 FOUT FOUT FOUT2 FOUT FOUT Frequency fosc / fosc / 2 fosc / 4 fosc / 8 fosc3 / fosc3 / 2 fosc3 / 4 fosc3 / 8 D3 D2 D D FF4 D7 D6 D5 D4 D3 D2 D D FF2 D7 D6 D5 D4 D3 D2 D D FF22 D7 D6 D5 D4 D3 D2 D D FF24 D7 D6 D5 D4 D3 D2 D D FOUTON FOUT output control WDRST TMRST TMRUN Watchdog timer reset Clock timer reset Clock timer Run/Stop control TMD7 Clock timer data Hz TMD6 Clock timer data 2 Hz TMD5 Clock timer data 4 Hz TMD4 Clock timer data 8 Hz TMD3 Clock timer data 6 Hz TMD2 Clock timer data 32 Hz TMD Clock timer data 64 Hz TMD Clock timer data 28 Hz PK KK7 interrupt priority register PK PSIF Serial interface interrupt priority register PSIF PSW Stopwatch timer interrupt priority register PSW PTM Clock timer interrupt priority register PTM ESW Stopwatch timer Hz interrupt enable register ESW Stopwatch timer Hz interrupt enable register ESW Stopwatch timer Hz interrupt enable register ETM32 Clock timer 32 Hz interrupt enable register ETM8 Clock timer 8 Hz interrupt enable register ETM2 Clock timer 2 Hz interrupt enable register ETM Clock timer Hz interrupt enable register FSW Stopwatch timer Hz interrupt factor flag FSW FSW FTM32 FTM8 FTM2 FTM Stopwatch timer Hz interrupt factor flag Stopwatch timer Hz interrupt factor flag Clock timer 32 Hz interrupt factor flag Clock timer 8 Hz interrupt factor flag Clock timer 2 Hz interrupt factor flag Clock timer Hz interrupt factor flag On Reset Reset Run High PK PSIF PSW PTM Interrupt enable PK PSIF PSW PTM (R) Interrupt factor is generated (W) Reset Off No operation No operation Stop Low Priority level Level 3 Level 2 Level Level Interrupt disable (R) No interrupt factor is generated (W) No operation W W R Constantly "" when being read "" when being read "" when being read 86 EPSON SC8F36 TECHNICAL MANUAL

99 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Clock Timer) TMDTMD7: FF4H The clock timer data can be read out. Each bit of TMDTMD7 and frequency correspondence are as follows: TMD: 28Hz TMD4: 8Hz TMD: 64Hz TMD5: 4Hz TMD2: 32Hz TMD6: 2Hz TMD3: 6Hz TMD7: Hz Since the TMDTMD7 is exclusively for reading, the write operation is invalid. At initial reset, the timer data is set to "H". TMRST: FF4H D Resets the clock timer. When "" is written: Clock timer reset When "" is written: No operation Reading: Always "" The clock timer is reset by writing "" to the TMRST. When the clock timer is reset in the RUN status, it restarts immediately after resetting. In the case of the STOP status, the reset data "H" is maintained. No operation results when "" is written to the TMRST. Since the TMRST is exclusively for writing, it always becomes "" during reading. TMRUN: FF4H D Controls RUN/STOP of the clock timer. When "" is written: RUN When "" is written: STOP Reading: Valid The clock timer starts up-counting by writing "" to the TMRUN and stops by writing "". In the STOP status, the count data is maintained until it is reset or set in the next RUN status. Also, when the STOP status changes to the RUN status, the data that was maintained can be used for resuming the count. At initial reset, the TMRUN is set to "" (STOP). PTM, PTM: FF2H D, D Sets the priority level of the clock timer interrupt. The two bits PTM and PTM are the interrupt priority register corresponding to the clock timer interrupt. Table shows the interrupt priority level which can be set by this register. Table Interrupt priority level settings PTM PTM Interrupt priority level Level 3 (IRQ3) Level 2 (IRQ2) Level (IRQ) Level (None) At initial reset, this register is set to "" (level ). ETM, ETM2, ETM8, ETM32: FF22H DD3 Enables or disables the generation of an interrupt for the CPU. When "" is written: Interrupt enabled When "" is written: Interrupt disabled Reading: Valid The ETM, ETM2, ETM8 and ETM32 are interrupt enable registers that respectively correspond to the interrupt factors for Hz, 2 Hz, 8 Hz and 32 Hz. Interrupts set to "" are enabled and interrupts set to "" are disabled. At initial reset, this register is set to "" (interrupt disabled). FTM, FTM2, FTM8, FTM32: FF24H DD3 Indicates the clock timer interrupt generation status. When "" is read: When "" is read: Interrupt factor present Interrupt factor not present When "" is written: Resets factor flag When "" is written: Invalid The FTM, FTM2, FTM8 and FTM32 are interrupt factor flags that respectively correspond to the interrupts for Hz, 2 Hz, 8 Hz and 32 Hz and are set to "" at the falling edge of each signal. When set in this manner, if the corresponding interrupt enable register is set to "" and the corresponding interrupt priority register is set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag will be set to "" by the occurrence of an interrupt generation condition. To accept the subsequent interrupt after interrupt generation, re-setting of the interrupt flags (set interrupt flag to lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and interrupt factor flag reset are necessary. The interrupt factor flag is reset to "" by writing "". At initial reset, this flag is reset to "". SC8F36 TECHNICAL MANUAL EPSON 87

100 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Clock Timer) Programming notes () The clock timer is actually made to RUN/STOP in synchronization with the falling edge of the 256 Hz signal after writing to the TMRUN register. Consequently, when "" is written to the TMRUN, the timer shifts to STOP status when the counter is incremented "". The TMRUN maintains "" for reading until the timer actually shifts to STOP status. Figure shows the timing chart of the RUN/STOP control. 256 Hz TMRUN(RD) TMRUN(WR) TMDx 57H 58H 59H 5AH 5BH 5CH Fig Timing chart of RUN/STOP control (2) The SLP instruction is executed when the clock timer is in the RUN status (TMRUN = ""). The clock timer operation will become unstable when returning from SLEEP status. Therefore, when shifting to SLEEP status, set the clock timer to STOP status (TMRUN = "") prior to executing the SLP instruction. 88 EPSON SC8F36 TECHNICAL MANUAL

101 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Stopwatch Timer) 5. Stopwatch Timer 5.. Configuration of stopwatch timer The SC8F36 has a built-in / sec and / sec stopwatch timer. The stopwatch timer is composed of a 4-bit 2 stage BCD counter (/ sec units and / sec units) that makes the 256 Hz signal that divides the fosc the input clock and it can read the count data by software. Figure 5... shows the configuration of the stopwatch timer. The stopwatch timer can be used as a timer different from the clock timer and can easily realize stopwatch and other such functions by software Count up pattern The stopwatch timer is respectively composed of the 4-bit BCD counters SWDSWD3 and SWD4SWD7. Figure shows the count up pattern of the stopwatch timer. The feedback dividing circuit generates an approximate Hz signal at 2/256 sec and 3/256 sec intervals from a 256 Hz signal divided from fosc. The / sec counter (SWDSWD3) generates an approximate Hz signal at 25/256 sec and 26/256 sec intervals by counting the approximate Hz signal generated by the feedback dividing circuit in 2/256 sec and 3/256 sec intervals. The count-up is made approximately / sec counting by the 2/ 256 sec and 3/256 sec intervals. The / sec counter (SWD4SWD7) generates a Hz signal by counting the approximate Hz signal generated by the / sec counter at 25/256 sec and 26/256 sec intervals in 4:6 ratios. The count-up is made approximately / sec counting by 25/256 sec and 26/256 sec intervals. Data bus Stopwatch timer SWDSWD7 OSC oscillation circuit SWRST SWRUN fosc Divider 256 Hz Stopwatch timer reset Stopwatch timer Run/Stop Feedback dividing circuit /sec 4-bit BCD counter /sec 4-bit BCD counter Approximate Hz Approximate Hz Hz Interrupt control circuit Fig Configuration of stopwatch timer Interrupt request / sec counter count-up pattern Hz signal Count value Count clock (Approximate Hz signal) Count time (sec) x x 4 = sec / sec counter count-up pattern Approximate Hz signal Count value Count clock (256 Hz) Count time (sec) sec / sec counter count-up pattern 2 Approximate Hz signal Fig Count-up pattern of stopwatch timer Count value Count clock (256 Hz) Count time (sec) sec SC8F36 TECHNICAL MANUAL EPSON 89

102 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Stopwatch Timer) 5..3 Interrupt function The stopwatch timer can generate an interrupt by each of the Hz (approximately Hz), Hz (approximately Hz) and Hz signals. Figure shows the configuration of the stopwatch timer interrupt circuit The corresponding factor flags FSW, FSW and FSW are respectively set to "" at the falling edge of the Hz, Hz and Hz signal and an interrupt is generated. Interrupt can be prohibited by the setting of the interrupt enable registers ESW, ESW and ESW corresponding to each interrupt factor flag. In addition, a priority level of the stopwatch timer interrupt for the CPU can be optionally set at levels to 3 by the interrupt priority registers PSW and PSW. For details on the above mentioned interrupt control registers and the operation following generation of an interrupt, see "5.7 Interrupt and Standby Status". The exception processing vector addresses of each interrupt factor are respectively set as shown below. Hz interrupt: 6H Hz interrupt: 8H Hz interrupt: AH Figure shows the timing chart for the stopwatch timer. Address Interrupt priority register PSW, PSW Hz falling edge Address Interrupt factor flag FSW Address Interrupt enable register ESW Data bus Hz falling edge Address Address Interrupt factor flag FSW Interrupt enable register ESW Interrupt priority level judgment circuit Interrupt request Hz falling edge Address Address Interrupt factor flag FSW Interrupt enable register ESW Fig Configuration of the stopwatch timer interrupt circuit SWD / sec SWD counter SWD2 BCD data SWD3 Hz interrupt Hz interrupt SWD4 / sec SWD5 counter SWD6 BCD data SWD7 Hz interrupt Fig Stopwatch timer timing chart 9 EPSON SC8F36 TECHNICAL MANUAL

103 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Stopwatch Timer) 5..4 Control of stopwatch timer Table shows the stopwatch timer control bits. Table Stopwatch timer control bits Address Bit Name Function FF42 D7 D6 D5 D4 D3 D2 D D SWRST SWRUN Stopwatch timer reset Stopwatch timer Run/Stop control Reset Run FF43 D7 SWD7 Stopwatch timer data D6 SWD6 D5 SWD5 BCD (/ sec) D4 SWD4 D3 SWD3 Stopwatch timer data D2 SWD2 D SWD BCD (/ sec) D SWD FF2 D7 D5 D3 D PK PSIF PSW PTM D6 D4 D2 D PK PSIF PSW PTM KK7 interrupt priority register Serial interface interrupt priority register Stopwatch timer interrupt priority register Clock timer interrupt priority register FF22 D7 D6 ESW Stopwatch timer Hz interrupt enable register D5 ESW Stopwatch timer Hz interrupt enable register D4 ESW Stopwatch timer Hz interrupt enable register D3 ETM32 Clock timer 32 Hz interrupt enable register D2 ETM8 Clock timer 8 Hz interrupt enable register D ETM2 Clock timer 2 Hz interrupt enable register D ETM Clock timer Hz interrupt enable register FF24 D7 D6 FSW Stopwatch timer Hz interrupt factor flag D5 FSW Stopwatch timer Hz interrupt factor flag D4 FSW Stopwatch timer Hz interrupt factor flag D3 FTM32 Clock timer 32 Hz interrupt factor flag D2 FTM8 Clock timer 8 Hz interrupt factor flag D FTM2 Clock timer 2 Hz interrupt factor flag D FTM Clock timer Hz interrupt factor flag PK PSIF PSW PTM Interrupt enable PK PSIF PSW PTM (R) Interrupt factor is generated (W) Reset No operation Stop Priority level Level 3 Level 2 Level Level Interrupt disable (R) No interrupt factor is generated (W) No operation SR W R Comment Constantly "" when being read "" when being read "" when being read SC8F36 TECHNICAL MANUAL EPSON 9

104 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Stopwatch Timer) SWDSWD7: FF43H The stopwatch timer data can be read out. Higher and lower nibbles and BCD digit correspondence are as follows: SWDSWD3: BCD (/sec) SWD4SWD7: BCD (/sec) Since SWDSWD7 are exclusively for reading, the write operation is invalid. At initial reset, the timer data is set to "H". SWRST: FF42H D Resets the stopwatch timer. When "" is written: Stopwatch timer reset When "" is written: No operation Reading: Always "" The stopwatch timer is reset by writing "" to the SWRST. When the stopwatch timer is reset in the RUN status, it restarts immediately after resetting. In the case of the STOP status, the reset data "H" is maintained. No operation results when "" is written to the SWRST. Since the SWRST is exclusively for writing, it always becomes "" during reading. SWRUN: FF42H D Controls RUN/STOP of the stopwatch timer. When "" is written: RUN When "" is written: STOP Reading: Valid The stopwatch timer starts up-counting by writing "" to the SWRUN and stops by writing "". In the STOP status, the timer data is maintained until it is reset or set in the next RUN status. Also, when the STOP status changes to the RUN status, the data that was maintained can be used for resuming the count. At initial reset, the SWRUN is set at "" (STOP). PSW, PSW: FF2H D2, D3 Sets the priority level of the stopwatch timer interrupt. The two bits PSW and PSW are the interrupt priority register corresponding to the stopwatch timer interrupt. Table shows the interrupt priority level which can be set by this register. Table Interrupt priority level settings PSW PSW Interrupt priority level Level 3 (IRQ3) Level 2 (IRQ2) Level (IRQ) Level (None) At initial reset, this register is set to "" (level ). ESW, ESW, ESW: FF22H D4, D5, D6 Enables or disables the generation of an interrupt for the CPU. When "" is written: Interrupt enabled When "" is written: Interrupt disabled Reading: Valid The ESW, ESW and ESW are interrupt enable registers that respectively correspond to the interrupt factors for Hz, Hz and Hz. Interrupts set to "" are enabled and interrupts set to "" are disabled. At initial reset, this register is set to "" (interrupt disabled). FSW, FSW, FSW: FF24H D4, D5, D6 Indicates the stopwatch timer interrupt generation status. When "" is read: Interrupt factor present When "" is read: Interrupt factor not present When "" is written: Resets factor flag When "" is written: Invalid The FSW, FSW and FSW are interrupt factor flags that respectively correspond to the interrupts for Hz, Hz and Hz and are set to "" in synchronization with the falling edge of each signal. When set in this manner, if the corresponding interrupt enable register is set to "" and the corresponding interrupt priority register is set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag will be set to "" by the occurrence of an interrupt generation condition. To accept the subsequent interrupt after interrupt generation, re-setting of the interrupt flags (set interrupt flag to lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and interrupt factor flag reset are necessary. The interrupt factor flag is reset to "" by writing "". At initial reset, this flag is reset to "". 92 EPSON SC8F36 TECHNICAL MANUAL

105 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Stopwatch Timer) 5..5 Programming notes () The stopwatch timer is actually made to RUN/ STOP in synchronization with the falling edge of the 256 Hz signal after writing to the SWRUN register. Consequently, when "" is written to the SWRUN, the timer shifts to STOP status when the counter is incremented "". The SWRUN maintains "" for reading until the timer actually shifts to STOP status. Figure shows the timing chart of the RUN/STOP control. 256 Hz SWRUN(RD) SWRUN(WR) SWDx Fig Timing chart of RUN/STOP control (2) The SLP instruction is executed when the stopwatch timer is in the RUN status (SWRUN = ""). The stopwatch timer operation will become unstable when returning from SLEEP status. Therefore, when shifting to SLEEP status, set the clock timer to STOP status (SWRUN = "") prior to executing the SLP instruction. SC8F36 TECHNICAL MANUAL EPSON 93

106 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) 5. Programmable Timer 5.. Configuration of programmable timer The SC8F36 has two built-in 8-bit programmable timer systems (timer and timer ). Timer and timer are composed of 8-bit presettable down counters and they can be used as 8-bit 2 channels or 6-bit channel programmable timer. They also have an event counter function and a pulse width measurement function using the K input port terminal. Figure 5... shows the configuration of the programmable timer. Programmable setting of the transfer rate is possible, due to the fact that the programmable timer underflow signal can be used as a synchronous clock for the serial interface. Furthermore, this halved underflow signal (TOUT) can also be output externally from the R27 output port terminal. Furthermore, the R26 output port terminal can be used to output the TOUT signal (TOUT inverted signal) by mask option. Note: If the TOUT terminal is used to drive an external component that consumes a large amount of current such as a bipolar transistor, design the pattern of traces on the printed circuit board so that the operation of the external component does not affect the IC power supply. Refer to <Output Terminals> in Section 8.4, "Precautions on Mounting", for more information Count operation and setting basic mode Here we will explain the basic operation and setting of the programmable timer. Setting of initial value and counting down The timers and each have a down counter and reload data register. The reload data registers RLDRLD7 (timer ) and RLDRLD7 (timer ) are registers that set the initial value of the counter. By writing "" to the preset control bit PSET (timer ) or PSET (timer ), the down counter loads the initial value set in the reload register RLD. Therefore, down-counting is executed from the stored initial value according to the input clock. The registers PRUN (timer ) and PRUN (timer ) are provided to control the RUN/STOP for timers and. After the reload data has been preset into the counter, down-counting is begun by writing "" to this register. When "" is written, the clock input is prohibited and the count stops. Programmable timer EVIN (K) Input port K PSET RLMD Reload controller Reload signal Reload data register RLDRLD7 OSC oscillation circuit OSC3 oscillation circuit fosc fosc3 Timer Run/Stop PRUN Selector CKSEL Timer Run/Stop PRUN Selector CKSEL Prescaler Prescaler setting 2,48 Hz PSC Divider PSC Timer function setting FCSEL PLPOL Pulse polarity setting Clock controller 8-bit down counter Data buffer PTDPTD7 EVCNT Event counter mode setting Underflow signal Data bus Interrupt request Interrupt control circuit Programmable timer PSET RLMD Reload controller Reload signal Reload data register RLDRLD7 TOUT (R27) TOUT (R26)* Output port R27, R26 Available when selected by mask option Serial interface /2 PTOUT Selector CHSEL Prescaler Prescaler setting PSC PSC Clock controller MODE6 8/6-bit mode setting Fig Configuration of programmable timer 8-bit down counter Data buffer PTDPTD7 Underflow signal 94 EPSON SC8F36 TECHNICAL MANUAL

107 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) The control of this RUN/STOP has no affect on the counter data. The counter data is maintained even during the stoppage of the counter and it can start the count, continuing from that data. The reading of the counter data can be done through the data buffers PTDPTD7 (timer ) and PTDPTD7 (timer ) with optional timing. When the down-counting has progressed and an underflow is generated, the counter reloads the initial value set in the reload data register. This underflow signal controls an interrupt generation, pulse (TOUT signal) output and serial interface clocking, in addition to reloading the counter. Continuous/one-shot mode setting By writing "" to the continuous/one-shot mode selection registers CONT (timer ) and CONT (timer ), the programmable timer is set to the continuous mode. In the continuous mode, the initial counter value is automatically loaded when an underflow is generated, and counting is continued. This mode is suitable when programmable intervals are necessary (such as an interrupt and a synchronous clock for the serial interface). On the other hand, when writing "" to the registers CONT (timer ) and CONT (timer ), the programmable timer is set to the one-shot mode. The counter loads an initial value and stops when an underflow is generated. At this time, the RUN/ STOP control register PRUN (timer ) and PRUN (timer ) are automatically reset to "". After the counter stops, a one-shot count can be performed once again by writing "" to registers PRUN (timer ) and PRUN (timer ). This mode is suitable for single time measurement, for example. Count data Input clock Continuous mode One-shot mode 3H 2H H H A5H A4H A6H 3H 2H H H A6H Underflow Reload When "A6H" is set into reload data register RLD. Fig Continuous mode and one-shot mode PRUN() PSET() RLD7(7) Input clock PTD7(7) PTD6(6) PTD5(5) PTD4(4) PTD3(3) PTD2(2) PTD() PTD() Preset A6H Fig Basic operation timing of the counter F3H Reload Underflow interrupt generation Note: The programmable timer counts down at the falling edge of the input clock and at the same time it generates an interrupt if the counter underflows. Then it starts loading the reload data to the counter and the counter data is determined at the next rising edge of the input clock (period shown in as in the figure). To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter data is determined including the reloading period. Be especially careful when using the OSC (low-speed clock) as the clock source of the programmable timer and the CPU is operating with the OSC3 (high-speed clock). SC8F36 TECHNICAL MANUAL EPSON 95

108 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) 8/6-bit mode setting By writing "" to the 8/6-bit mode selection register MODE6, timer and timer are set as independent timers in 8-bit 2 channels. In this mode, timer and timer can be controlled individually and each of them operates independently. On the other hand, when writing "" to the register MODE6, timer and timer are set as channel 6-bit timer. This is done by setting timer to the lower 8 bits, and timer to the upper 8 bits. The timer is controlled by timer 's registers. In this case, the control registers for timer are invalid. (PRUN is fixed at "".) Timer input clock Timer input clock [8-bit mode] 8-bit data Timer Timer Interrupt request Interrupt request Timer input clock Timer underflow signal 8-bit data High-order 8-bit data Fig /6-bit mode setting and counter configuration 5..3 Setting of input clock [6-bit mode] Low-order 8-bit data Timer Timer Interrupt request Prescalers have been provided for timers and. The prescalers generate the input clock for each by dividing the source clock signal from the OSC or OSC3 oscillation circuit. The source clock and the dividing ratio of the prescaler can be selected individually for timer and timer in software. The input clocks are set by the below sequence. () Selection of source clock Select the source clock (OSC or OSC3) for each prescaler. This is done with the source clock selection registers CKSEL (timer ) and CKSEL (timer ): when "" is written, OSC is selected and when "" is written, OSC3 is selected. When the 6-bit mode is selected, the source clock is selected by register CKSEL, and the register CKSEL setting becomes invalid. When the OSC3 oscillation circuit is made the clock source, it is necessary to turn the OSC3 oscillation ON, prior to using the programmable timer. From the time the OSC3 oscillation circuit is turning ON until oscillation stabilizes, an interval of several msec to several msec is necessary. Consequently, you should allow an adequate waiting time after turning the OSC3 oscillation circuit ON before starting the count of the programmable timer. (The oscillation start time will vary somewhat depending on the oscillator and on external parts. Refer to the oscillation start time example indicated in Chapter, "ELECTRICAL CHARACTERIS- TICS".) At initial reset, OSC3 oscillation circuit is set to OFF status. (2) Selection of prescaler dividing ratio Select the dividing ratio of each prescaler from among 4 types. This selection is done by the prescaler dividing ratio selection registers PSC/PSC (timer ) and PSC/PSC (timer ). Setting value and dividing ratio correspondence are shown in Table Table Selection of prescaler dividing ratio PSC PSC PSC PSC Prescaler dividing ratio Source clock / 64 Source clock / 6 Source clock / 4 Source clock / By writing "" to the register PRUN (timer ) and PRUN (timer ), the source clock is input to the prescaler. Therefore, the clock with selected dividing ratio is input to the timer and the timer starts counting down. When the 6-bit mode has been selected, the dividing ratio for the source clock is selected by register PSC/PSC and the setting of register PSC/PSC becomes invalid Timer mode The timer mode counts down using the prescaler output as an input clock. In this mode, the programmable timer operates as a timer that obtains fixed cycles using the OSC or OSC3 oscillation circuit as a clock source. See "5..2 Count operation and setting basic mode" for basic operation and control, and "5..3 Setting of input clock" for the clock source and setting of the prescaler. 96 EPSON SC8F36 TECHNICAL MANUAL

109 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) 5..5 Event counter mode Timer includes an even counter function that counts by inputting an external clock (EVIN) to input port K. This function is selected by writing "" to the timer counter mode selection register EVCNT. When the event counter mode is selected, timer operates as an event counter and timer operates as a normal timer in 8-bit mode. In the 6-bit mode, timer and timer operate as channel 6-bit event counter. In the event counter mode, since the timer is clocked externally, the settings of registers PSC/PSC become invalid. Count down timing can be controlled by either the falling edge or rising edge selected by the timer pulse polarity selection register PLPOL. When "" is written to the register PLPOL, the falling edge is selected, and when "" is written, the rising edge is selected. The timing is shown in Figure EVCNT PRUN PLPOL EVIN input (K) Count data n n- n-2 n-3 n-4 n-5 n-6 Fig Timing chart for event counter mode The event counter also includes a noise rejector to eliminate noise such as chattering for the external clock (EVIN). This function is selected by writing "" to the timer function selection register FCSEL. For a reliable count when "with noise rejector" is selected, you must allow.98 msec or more pulse width for both LOW and HIGH levels. (The noise rejector allows clocking counter at the second falling edge of the internal 2,48 Hz signal after changing the input level of the K input port terminal. Consequently, the pulse width that can reliably be rejected is.48 msec.) Figure shows the count down timing with the noise rejector selected. 2,48 Hz EVIN input (K) Input clock to counter Count data n n- n-2 n-3 When "" is set into register PLPOL. Fig Count down timing with noise rejector The event counter mode is the same as the timer mode except that the clock is external (EVIN). See "5..2 Count operation and setting basic mode" for the basic operation and control Pulse width measurement timer mode Timer includes a pulse width measurement function that measures the width of the input signal to the K input port terminal. This function is selected by writing "" to the timer function selection register FCSEL when in the timer mode (EVCNT = ""). When the pulse width measurement mode is selected, timer operates as an pulse width measurement and timer operates as a normal timer in 8-bit mode. In the 6-bit mode, timer and timer operate as channel 6-bit pulse width measurement. The level of the input signal (EVIN) for measurement can be changed either a LOW or HIGH level by the timer pulse polarity selection register PLPOL. When "" is written to register PLPOL, a LOW level width is measured and when "" is written, a HIGH level width is measured. The timing is shown in Figure The pulse width measurement timer mode is the same as the timer mode except that the input clock is controlled by the level of the signal (EVIN) input to the K input port terminal. See "5..2 Count operation and setting basic mode" for the basic operation and control. FCSEL PRUN Prescaler output clock PLPOL EVIN input (K) Input clock to timer Count data n n- n-2 n-3 n-4 Fig Timing chart for pulse width measurement timer mode n-5 n-6 n-7 n-8 SC8F36 TECHNICAL MANUAL EPSON 97

110 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) 5..7 Interrupt function The programmable timer can generate an interrupt due to an underflow signal of timer and timer. Figure shows the configuration of the programmable timer interrupt circuit. The respectively corresponding interrupt factor flags FPT and FPT are set to "" and an interrupt is generated by an underflow signal of timers and. Interrupt can also be prohibited by the setting of the interrupt enable registers EPT and EPT corresponding to each interrupt flag. In addition, a priority level of the programmable timer interrupt for the CPU can be optionally set at levels to 3 by the interrupt priority registers PPT and PPT. For details on the above mentioned interrupt control registers and the operation following generation of an interrupt, see "5.7 Interrupt and Standby Status". The exception processing vector addresses of each interrupt factor are respectively set as shown below. Programmable timer interrupt: 6H Programmable timer interrupt: 8H When the 6-bit mode is selected, the interrupt factor flag FPT is not set to "" and a timer interrupt cannot be generated. (In the 6-bit mode, the interrupt factor flag FPT is set to "" by an underflow of the 6-bit counter Setting of TOUT output The programmable timer can generate the TOUT signal due to an underflow of timer or timer. The TOUT signal is generated from the above mentioned underflow signal by halving the frequency. The timer underflow which is to be used can be selected by the TOUT output channel selection register CHSEL. When writing "" to register CHSEL, timer is selected and when "" is written, timer is selected. However, in the 6-bit mode, it is fixed in timer (underflow of the 6-bit timer) and the setting of register CHSEL becomes invalid. Figure shows the TOUT signal waveform when channel switching. CHSEL Timer underflow Timer underflow TOUT output (R27) Fig TOUT signal waveform at channel change The TOUT signal can be output from the R27 output port terminal, and the programmable clock can be supplied to an external device. Furthermore, the R26 output port terminal can be used to output the TOUT signal (TOUT inverted signal) by mask option. The configuration of the output ports R27 and R26 is shown in Figure Register R27D R27 output Register PTOUT TOUT signal R26 output Register R26D Mask option Fig Configuration of R27 and R26 Address Interrupt priority register PPT, PPT Timer underflow Address Interrupt factor flag FPT Data bus Address Timer underflow Address Interrupt enable register EPT Interrupt factor flag FPT Interrupt priority level judgment circuit Interrupt request Address Interrupt enable register EPT Fig Configuration of programmable timer interrupt circuit 98 EPSON SC8F36 TECHNICAL MANUAL

111 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) The output control for the TOUT (TOUT) signal is done by the register PTOUT. When you set "" for the PTOUT, the TOUT (TOUT) signal is output from the R27 (R26) output port terminal. When "" is set, the R27 goes HIGH (VDD) and the R26 goes LOW (VSS). To output the TOUT signal, "" must always be set for the data register R27D. The data register R26D does not affect the TOUT output. Since the TOUT signal is generated asynchronously from the register PTOUT, when the signal is turned ON or OFF by the register setting, a hazard of a /2 cycle or less is generated. Figure shows the output waveform of TOUT signal. PTOUT TOUT output (R27) TOUT output (R26) * when selected by mask option Fig TOUT output waveform 5..9 Transmission rate setting of serial interface The underflow signal of the timer can be used to clock the serial interface. The transmission rate setting in this case is made in registers PSCx and RLDx, and is used to set the count mode to the reload count mode (RLMD = ""). Since the underflow signal of the timer is divided by /32 in the serial interface, the value set in register RLDx which corresponds to the transmission rate is shown in the following expression: RLDx = fosc / (32*bps*4 PSCX ) - fosc: Oscillation frequency (OSC/OSC3) bps: Transmission rate PSCx: Setting value to the register PSCx (3) (H can be set to RLDx) Table shows an example of the transmission rate setting when the OSC3 oscillation circuit is used as a clock source. Table Example of transmission rate setting Transfer rate (bps) 9,6 4,8 2,4, OSC3 oscillation frequency / Programmable timer settings fosc3 = 3.72 MHz fosc3 = 4.68 MHz fosc3 = MHz PSCx (/) (/) (/) (/) (/) (/4) (/4) RLDx 9H 3H 27H 4FH 9FH 4FH 9FH PSCx (/) (/) (/) (/) (/) (/4) (/4) RLDx EH DH 3BH 77H EFH 77H EFH PSCx (/) (/) (/) (/) (/) (/4) (/4) RLDx FH FH 3FH 7FH FFH 7FH FFH SC8F36 TECHNICAL MANUAL EPSON 99

112 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) 5.. Control of programmable timer Table 5... shows the programmable timer control bits. Table 5...(a) Programmable timer control bits Address Bit Name Function SR FF3 D7 D6 D5 D4 D3 D2 MODE6 CHSEL PTOUT 8/6-bit mode selection TOUT output channel selection TOUT output control 6-bit x Timer On 8-bit x 2 Timer Off D D CKSEL Prescaler source clock selection CKSEL Prescaler source clock selection fosc3 fosc3 fosc fosc FF3 D7 EVCNT Timer counter mode selection Event counter Timer D6 FCSEL Timer In timer mode Pulse width Normal function selection measurement mode In event counter mode With Without noise rejector noise rejector D5 PLPOL Timer Down count timing Rising edge Falling edge pulse polarity in event counter mode of K input of K input selection In pulse width High level Low level measurement measurement measurement mode for K input for K input D4 PSC Timer prescaler dividing ratio selection PSC PSC Prescaler dividing ratio Source clock / 64 D3 PSC Source clock / 6 Source clock / 4 Source clock / D2 CONT Timer continuous/one-shot mode selection Continuous One-shot D PSET Timer preset Preset No operation D PRUN Timer Run/Stop control Run Stop FF32 D7 D6 D5 D4 PSC Timer prescaler dividing ratio selection PSC PSC Prescaler dividing ratio Source clock / 64 D3 PSC Source clock / 6 Source clock / 4 Source clock / D2 D D CONT PSET PRUN FF33 D7 RLD7 D6 RLD6 D5 RLD5 D4 RLD4 D3 RLD3 D2 RLD2 D RLD D RLD Timer continuous/one-shot mode selection Timer preset Timer Run/Stop control Timer reload data D7 (MSB) Timer reload data D6 Timer reload data D5 Timer reload data D4 Timer reload data D3 Timer reload data D2 Timer reload data D Timer reload data D (LSB) Continuous One-shot Preset No operation Run Stop High Low W W Comment Constantly "" when being read "" when being read Constantly "" when being read "" when being read EPSON SC8F36 TECHNICAL MANUAL

113 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) Table 5...(b) Programmable timer control bits Address Bit Name Function SR FF34 D7 D6 D5 D4 D3 D2 D D RLD7 RLD6 RLD5 RLD4 RLD3 RLD2 RLD RLD FF35 D7 D6 D5 D4 D3 D2 D D PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD PTD FF36 D7 D6 D5 D4 D3 D2 D D PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD PTD FF2 D7 D6 D5 D4 D3 D2 D D PPT PPT PK PK FF23 D7 EPT D6 EPT D5 EK D4 EKH D3 EKL D2 ESERR D ESREC D ESTRA FF25 D7 FPT D6 FPT D5 FK D4 FKH D3 FKL D2 FSERR D FSREC D FSTRA Timer reload data D7 (MSB) Timer reload data D6 Timer reload data D5 Timer reload data D4 Timer reload data D3 Timer reload data D2 Timer reload data D Timer reload data D (LSB) Timer counter data D7 (MSB) Timer counter data D6 Timer counter data D5 Timer counter data D4 Timer counter data D3 Timer counter data D2 Timer counter data D Timer counter data D (LSB) Timer counter data D7 (MSB) Timer counter data D6 Timer counter data D5 Timer counter data D4 Timer counter data D3 Timer counter data D2 Timer counter data D Timer counter data D (LSB) Programmable timer interrupt priority register K and K interrupt priority register Programmable timer interrupt enable register Programmable timer interrupt enable register K and K interrupt enable register K4K7 interrupt enable register KK3 interrupt enable register Serial I/F (error) interrupt enable register Serial I/F (receiving) interrupt enable register Serial I/F (transmitting) interrupt enable register Programmable timer interrupt factor flag Programmable timer interrupt factor flag K and K interrupt factor flag K4K7 interrupt factor flag KK3 interrupt factor flag Serial I/F (error) interrupt factor flag Serial I/F (receiving) interrupt factor flag Serial I/F (transmitting) interrupt factor flag High High High PPT PK Interrupt enable PPT PK (R) Interrupt factor is generated (W) Reset Low Low Low Priority level Level 3 Level 2 Level Level Interrupt disable (R) No interrupt factor is generated (W) No operation R R Comment Constantly "" when being read SC8F36 TECHNICAL MANUAL EPSON

114 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) MODE6: FF3H D4 Selects the 8/6-bit mode. When "" is written: 6 bits channel When "" is written: 8 bits 2 channels Reading: Valid Select whether timer and timer will be used as 2 channel independent 8-bit timers or as a channel combined 6-bit timer. When "" is written to MODE6, 8-bit 2 channels is selected and when "" is written, 6-bit channel is selected. At initial reset, MODE6 is set to "" (8-bit 2 channels). CKSEL, CKSEL: FF3H D, D Select the source clock of the prescaler. When "" is written: OSC3 clock When "" is written: OSC clock Reading: Valid Select whether the source clock of prescaler will be set to OSC or OSC3. When "" is written to CKSEL, OSC is selected and when "" is written, OSC3 is selected. In the same way, the source clock of prescaler is selected by CKSEL. When event counter mode has been selected, the setting of the CKSEL becomes invalid. In the same way, the CKSEL setting becomes invalid when 6- bit mode has been selected. At initial reset, this register is set to "" (OSC clock). PSC, PSC: FF3H D3, D4 PSC, PSC: FF32H D3, D4 Select the dividing ratio of the prescaler. Two-bit PSC and PSC is the prescaler dividing ratio selection registers for timer, and the two-bit PSC and PSC correspond to timer. The prescaler dividing ratios that can be set by these registers are shown in Table Table Selection of prescaler dividing ratio PSC PSC PSC PSC Prescaler dividing ratio Source clock / 64 Source clock / 6 Source clock / 4 Source clock / When event counter mode has been selected, the setting of the PSC and PSC becomes invalid. In the same way, the PSC and PSC setting becomes invalid when 6-bit mode has been selected. At initial reset, this register is set to "" (input clock/). EVCNT: FF3H D7 Selects the counter mode for the timer. When "" is written: Event counter mode When "" is written: Timer mode Reading: Valid Select whether timer will be used as an event counter or a timer. When "" is written to EVCNT, the event counter mode is selected and when "" is written, the timer mode is selected. At initial reset, EVCNT is set to "" (timer mode). FCSEL: FF3H D6 Selects the function for each counter mode of timer. In timer mode When "" is written: Pulse width measurement timer mode When "" is written: Normal mode Reading: Valid In the timer mode, select whether timer will be used as a pulse width measurement timer or a normal timer. When "" is written to FCSEL, the pulse width measurement mode is selected and the counting is done according to the level of the signal (EVIN) input to the K input port terminal. When "" is written to FCSEL, the normal mode is selected and the counting is not affected by the K input port terminal. In event counter mode When "" is written: With noise rejector When "" is written: Without noise rejector Reading: Valid In the event counter mode, select whether the noise rejector for the K input port terminal will be selected or not. When "" is written to FCSEL, the noise rejector is selected and counting is done by an external clock (EVIN) with.98 msec or more pulse width. (The noise rejector allows clocking counter at the second falling edge of the internal 2,48 Hz signal after changing the input level of the K input port terminal. Consequently, the pulse width that can reliably be rejected is.48 msec.) When "" is written to FCSEL, the noise rejector is not selected and the counting is done directly by an external clock (EVIN) input to the K input port terminal. At initial reset, FCSEL is set to "". 2 EPSON SC8F36 TECHNICAL MANUAL

115 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) PLPOL: FF3H D5 Selects the pulse polarity for the K input port terminal. In event counter mode When "" is written: Rising edge When "" is written: Falling edge Reading: Valid In the event counter mode, select whether the count timing will be set at the falling edge of the external clock (EVIN) input to the K input port terminal or at the rising edge. When "" is written to PLPOL, the falling edge is selected and when "" is written, the rising edge is selected. In pulse width measurement mode When "" is written: HIGH level pulse width measurement When "" is written: LOW level pulse width measurement Reading: Valid In the pulse width measurement mode, select whether the LOW level width of the signal (EVIN) input to the K input port terminal will be measured or the HIGH level will be measured. When "" is written to PLPOL, the LOW level width measurement is selected and when "" is written, the HIGH level width measurement is selected. In the normal mode (EVCNT = FCSEL = ""), the setting of PLPOL becomes invalid. At initial reset, PLPOL is set to "". CONT, CONT: FF3H D2, FF32H D2 Select the continuous/one-shot mode. When "" is written: Continuous mode When "" is written: One-shot mode Reading: Valid Select whether timer will be used in the continuous mode or in the one-shot mode. By writing "" to CONT, the programmable timer is set to the continuous mode. In the continuous mode, the initial counter value is automatically loaded when an underflow is generated, and counting is continued. On the other hand, when writing "" to CONT, the programmable timer is set to the oneshot mode. The counter loads an initial value and stops when an underflow is generated. At this time, PRUN is automatically reset to "". In the same way, the continuous/one-shot mode for timer is selected by CONT. (In the one-shot mode for timer, PRUN is automatically reset to "" when the counter underflow is generated.) At initial reset, this register is set to "" (one-shot mode). RLDRLD7: FF33H RLDRLD7: FF34H Sets the initial value for the counter. RLDRLD7: Reload data for Timer RLDRLD7: Reload data for Timer The reload data set in this register is loaded into the respective counters and is counted down with that as the initial value. Reload data is loaded to the counter under two conditions, when "" is written to PSET or PSET and when the counter underflow automatically loads. At initial reset, this register is set to "FFH". PTDPTD7: FF35H PTDPTD7: FF36H Data of the programmable timer can be read out. PTDPTD7: Timer counter data PTDPTD7: Timer counter data These bits act as a buffer to maintain the counter data during readout, and the data can be read as optional timing. However, in the 6-bit mode, to avoid a read error, (data error when a borrow from timer to timer is generated in the middle of reading PTDPTD7 and PTDPTD7), PTDPTD7 latches the timer counter data according to the reading of PTDPTD7. The latched status of PTDPTD7 is canceled according to the readout of PTDPTD7 or when msec (depends on the readout timing) has elapsed. Therefore, in 6-bit mode, be sure to read the counter data of PTDPTD7 and PTD PTD7 in order. Since these bits are exclusively for reading, the write operation is invalid. At initial reset, these bits are set to "FFH". PSET, PSET: FF3H D, FF32H D Presets the reload data to the counter. When "" is written: Preset When "" is written: No operation Reading: Always "" By writing "" to PSET, the reload data in PLD PLD7 is preset to the counter of timer. When the counter of timer is preset in the RUN status, it restarts immediately after presetting. In the case of STOP status, the reload data that has been preset is maintained. No operation results when "" is written. In the same way, the reload data in PLDPLD7 is preset to the counter of timer by PSET. When the 6-bit mode is selected, writing "" to PSET is invalid. This bit is exclusively for writing, it always becomes "" during reading. SC8F36 TECHNICAL MANUAL EPSON 3

116 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) PRUN, PRUN: FF3H D, FF32H D Controls the RUN/STOP of the counter. When "" is written: RUN When "" is written: STOP Reading: Valid The counter of timer starts down-counting by writing "" to PRUN and stops by writing "". In the STOP status, the counter data is maintained until it is preset or set in the next RUN status. Also, when the STOP status changes to the RUN status, the data that was maintained can be used for resuming the count. In the same way, the RUN/STOP of the timer counter is controlled by PRUN. When the 6-bit mode is selected, PRUN is fixed at "". At initial reset and when an underflow is generated in the one-shot mode, this register is set to "" (STOP). CHSEL: FF3H D3 Selects a channel for generating the TOUT signal. When "" is written: Timer underflow When "" is written: Timer underflow Reading: Valid Select whether the timer underflow will be used for the TOUT signal or the timer underflow will be used. When "" is written to CHSEL, timer is selected and when "" is written, timer is selected. When the 6-bit mode has been selected, it is fixed to timer (underflow of the 6-bit timer), and setting of CHSEL becomes invalid. At initial reset, CHSEL is set to "" (timer underflow). PTOUT: FF3H D2 Controls the TOUT (programmable timer output clock) signal output. When "" is written: TOUT signal output ON When "" is written: TOUT signal output OFF Reading: Valid PTOUT is the output control register for TOUT (TOUT) signal. When "" is set to the register, the TOUT signal is output from the output port terminal R27 (R26). When "" is set, the R27 goes HIGH (VDD) and the R26 goes LOW (VSS). To output the TOUT signal, "" must always be set for the data register R27D. The data register R26D does not affect the TOUT output. At initial reset, PTOUT is set to "" (DC output). The TOUT signal can be output from R26 only when the function is selected by mask option. PPT, PPT: FF2H D2, D3 Sets the priority level of the programmable timer interrupt. The two bits PPT and PPT are the interrupt priority register corresponding to the programmable timer interrupt. Table shows the interrupt priority level which can be set by this register. Table Interrupt priority level settings PPT PPT Interrupt priority level Level 3 (IRQ3) Level 2 (IRQ2) Level (IRQ) Level (None) At initial reset, this register is set to "" (level ). EPT, EPT: FF23H D6, D7 Enables or disables the generation of an interrupt for the CPU. When "" is written: Interrupt enabled When "" is written: Interrupt disabled Reading: Valid The EPT and EPT are interrupt enable registers that respectively correspond to the interrupt factors for timer and timer. Interrupts set to "" are enabled and interrupts set to "" are disabled. When the 6-bit mode is selected, setting of EPT becomes invalid. At initial reset, this register is set to "" (interrupt disabled). FPT, FPT: FF25H D6, D7 Indicates the programmable timer interrupt generation status. When "" is read: Interrupt factor present When "" is read: Interrupt factor not present When "" is written: Resets factor flag When "" is written: Invalid The FPT and FPT are interrupt factor flags that respectively correspond to the interrupts for timer and timer and are set to "" in synchronization with the underflow of each counter. When set in this manner, if the corresponding interrupt enable register is set to "" and the corresponding interrupt priority register is set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag will be set to "" by the occurrence of an interrupt generation condition. 4 EPSON SC8F36 TECHNICAL MANUAL

117 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer) To accept the subsequent interrupt after interrupt generation, re-setting of the interrupt flags (set interrupt flag to lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and interrupt factor flag reset are necessary. The interrupt factor flag is reset to "" by writing "". When the 6-bit mode is selected, the interrupt factor flag FPT is not set to "" and a timer interrupt cannot be generated. (In the 6-bit mode, the interrupt factor flag FPT is set to "" by an underflow of the 6-bit counter.) At initial reset, this flag is reset to "". 5.. Programming notes () The programmable timer is actually made to RUN/STOP in synchronization with the falling edge of the input clock after writing to the PRUN() register. Consequently, when "" is written to the PRUN(), the timer shifts to STOP status when the counter is decremented "". The PRUN() maintains "" for reading until the timer actually shifts to STOP status. Figure 5... shows the timing chart of the RUN/STOP control. Input clock PRUN/PRUN(RD) PRUN/PRUN(WR) PTDx/PTDx 42H 4H 4H 3FH 3EH 3DH Fig Timing chart of RUN/STOP control The event counter mode is excluded from the above note. (2) The SLP instruction is executed when the programmable timer is in the RUN status (PRUN() = ""). The programmable timer operation will become unstable when returning from SLEEP status. Therefore, when shifting to SLEEP status, set the clock timer to STOP status (PRUN() = "") prior to executing the SLP instruction. In the same way, disable the TOUT signal output (PTOUT = "") to avoid an unstable clock output to the R27 (R26) output port terminal. (3) Since the TOUT signal is generated asynchronously from the register PTOUT, when the signal is turned ON or OFF by the register setting, a hazard of a /2 cycle or less is generated. (4) When the OSC3 oscillation circuit is made the clock source, it is necessary to turn the OSC3 oscillation ON, prior to using the programmable timer. From the time the OSC3 oscillation circuit is turning ON until oscillation stabilizes, an interval of several msec to several msec is necessary. Consequently, you should allow an adequate waiting time after turning the OSC3 oscillation circuit ON before starting the count of the programmable timer. (The oscillation start time will vary somewhat depending on the oscillator and on external parts. Refer to the oscillation start time example indicated in Chapter, "ELECTRICAL CHARACTERIS- TICS".) At initial reset, OSC3 oscillation circuit is set to OFF status. (5) When the 6-bit mode has been selected, be sure to read the counter data in the order of PTD PTD7 and PTDPTD7. Moreover, the time interval between reading PTDPTD7 and PTDPTD7 should be.73 msec or less. (6) For the reason below, pay attention to the reload data write timing when changing the interval of the programmable timer interrupts while the programmable timer is running. The programmable timer counts down at the falling edge of the input clock and at the same time it generates an interrupt if the counter underflows. Then it starts loading the reload data to the counter and the counter data is determined at the next rising edge of the input clock (period shown in as ➀ in the figure). (Reload data = 25H) Input clock Counter data (continuous mode) 3H 2H H H 25H 24H Underflow (interrupt is generated) Counter data is determined by reloading Fig Reload timing for programmable timer To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter data is determined including the reloading period ➀. Be especially careful when using the OSC (low-speed clock) as the clock source of the programmable timer and the CPU is operating with the OSC3 (high-speed clock). ➀ SC8F36 TECHNICAL MANUAL EPSON 5

118 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Controller) 5.2 LCD Controller 5.2. Configuration of LCD controller The SC8F36 has a built-in dot matrix LCD driver. The SC8F36 allows an LCD panel with a maximum of,632 dots (5 segments 32 commons). It also has an LCD controller for an external LCD driver. Figure shows the configuration of the LCD controller and the drive power supply. Note: It is necessary to connect a load resistance between terminals VSSVC Mask option The SC8F36 generates the LCD drive voltage using the internal power supply circuit. There is no mask option for selecting an external power supply Switching drive duty The SC8F36 supports three types of LCD drive duty settings, /8, /6 and /32, and it can be switched using the LDUTY and DUTY8 registers. When "" is written to the drive duty selection register LDUTY, /32 duty is selected and when "" is written, /6 duty is selected. When "" is written to DUTY8, the drive duty is fixed at /8 and setting of LDUTY becomes invalid LCD power supply The LCD system drive voltages VCVC5 are generated by the internal voltage regulator and voltage booster circuits. The internal power supply can generate two types of reference voltage; TYPE A (4.5 V) and TYPE B (5.5 V), and either one can be selected according to the panel characteristics using the LCDAJ register LCD driver The maximum number of dots changes according to the drive duty selection. When /32 duty is selected, the combined common/ segment output terminal is switched to the common terminal. An LCD panel with 5 segments 32 commons (maximum,632 dots) can be driven in the SC8F36. When /6 duty is selected, the combined common/segment output terminal is switched to the segment terminal. An LCD panel with 67 segments 6 commons (maximum,72 dots) in the SC8F36 can be driven. When /8 duty is selected, the combined common/segment output terminal is switched to the segment terminal as when /6 duty is selected. An LCD panel with 67 segments 8 commons (maximum 536 dots) in the SC8F36 can be driven. Furthermore, when /8 duty is selected, terminals COM8COM5 become invalid, in that they always output an OFF signal. Table shows the correspondence between the drive duty and the maximum number of displaying dots. The drive bias is /5 (five potentials, VCVC5) for any one of the /32, /6 and / 8 duties. The respective drive waveforms are shown in Figures CL (R25) FR (R26) Output port R25, R26 CL FR LCD synchronous signal generator LCCLK LCFRM VC VC2 LCD system voltage regulator LCD contrast adjustment circuit LC3 LC2 LC LC VC3 VC4 LCDAJ LCDC LCDC Note: Do not use VCVC5 for driving the expanded LCD driver. VC5 CA CB CC CD CE LCD system voltage booster VC, VC2 VC3VC5 LCD driver DTFNT LDUTY DUTY8 COMCOM5 COM6COM3/SEG66SEG5 SEGSEG5 VSS DSPAR Display memory Fig Configuration of LCD controller and drive power supply Table Correspondence between drive duty and maximum number of displaying dots DUTY8 LDUTY Duty Common terminal Segment terminal Maximum number of display dots /32 COMCOM3 SEGSEG5,632 dots /6 COMCOM5 SEGSEG66,72 dots /8 COMCOM7 SEGSEG dots 6 EPSON SC8F36 TECHNICAL MANUAL

119 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Controller) 32 Hz COM SEG FR COM COM COM2 SEG SEG COMSEG VDD VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC V SS (GND) -VC -VC2 -VC3 -VC4 -VC5 COMSEG VC5 VC4 VC3 VC2 VC V SS (GND) -VC -VC2 -VC3 -VC4 -VC5 Fig Drive waveform for /32 duty SC8F36 TECHNICAL MANUAL EPSON 7

120 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Controller) 32 Hz COM SEG FR COM COM COM2 SEG VDD VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC VSS SEG VC5 VC4 VC3 VC2 VC VSS COMSEG VC5 VC4 VC3 VC2 VC V SS (GND) -VC -VC2 -VC3 -VC4 -VC5 COMSEG VC5 VC4 VC3 VC2 VC V SS (GND) -VC -VC2 -VC3 -VC4 -VC5 Fig Drive waveform for /6 duty 8 EPSON SC8F36 TECHNICAL MANUAL

121 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Controller) 64 Hz COM SEG FR COM COM VDD VSS VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC VSS COM2 VC5 VC4 VC3 VC2 VC VSS SEG VC5 VC4 VC3 VC2 VC VSS SEG VC5 VC4 VC3 VC2 VC VSS COMSEG VC5 VC4 VC3 VC2 VC V SS (GND) -VC -VC2 -VC3 -VC4 -VC5 Fig Drive waveform for /8 duty COMSEG VC5 VC4 VC3 VC2 VC V SS (GND) -VC -VC2 -VC3 -VC4 -VC Display memory The SC8F36 has a built-in 42-byte display memory. The display memory is allocated to address FxHFx42H (x = 8DH) and the correspondence between the memory bits and common/ segment terminal is changed according to the selection status of the following items. () Drive duty (/32, /6 or /8 duty) (2) Dot font (5 8 or 5 5 dots) When /6 or /8 duty is selected for drive duty, two-screen memory can be secured, and the two screens can be switched by the display memory area selection register DSPAR. When "" is written to DSPAR, display area is selected and when "" is written, display area is selected. Furthermore, memory allocation for 5 8 dots and 5 5 dots can be selected in order to easily display 5 5-dot font characters on the LCD panel. This selection can be done by the dot font selection register DTFNT: when "" is written to DTFNT, 5 8 dots is selected and when "" is written, 5 5 dots is selected. The correspondence between the display memory bits set according to the drive duty and font size, and the common/segment terminals are shown in Figures When "" is written to the display memory bit corresponding to the dot on the LCD panel, the dot goes ON and when "" is written, it goes OFF. Since display memory is designed to permit reading/ writing, it can be controlled in bit units by logical operation instructions and other means (read, modify and write instructions). The display area bits which have not been assigned within the 42-byte display memory can be used as general purpose RAM with read/write capabilities. Even when external memory has expanded into the display memory area, this area is not released to external memory. Access to this area is always via display memory. SC8F36 TECHNICAL MANUAL EPSON 9

122 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Controller) Address/Data bit F8H F842H F9H F942H FAH FA42H FBH FB42H FCH FC42H FDH FD42H D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 SEG A B C D E F A B C D E F A B C D E F A B C D E F 2 Display area Display area Display area Display area COM Fig /32 duty and 5 8 dots display memory map EPSON SC8F36 TECHNICAL MANUAL

123 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Controller) Address/Data bit F8H F842H F9H F942H FAH FA42H FBH FB42H FCH FC42H FDH FD42H D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 SEG A B C D E F A B C D E F A B C D E F A B C D E F 2 Display area Display area Display area Display area Display area Display area COM Fig /32 duty and 5 5 dots display memory map SC8F36 TECHNICAL MANUAL EPSON

124 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Controller) Address/Data bit F8H F842H F9H F942H FAH FA42H FBH FB42H FCH FC42H FDH FD42H D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 SEG A B C D E F A B C D E F A B C D E F A B C D E F 2 Display area (when "" is set into DSPAR) Display area (when "" is set into DSPAR) Display area (when "" is set into DSPAR) Display area (when "" is set into DSPAR) COM Fig /6 duty and 5 8 dots display memory map 2 EPSON SC8F36 TECHNICAL MANUAL

125 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Controller) Address/Data bit F8H F842H F9H F942H FAH FA42H FBH FB42H FCH FC42H FDH FD42H D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 SEG A B C D E F A B C D E F A B C D E F A B C D E F 2 Display area (when "" is set into DSPAR) Display area (when "" is set into DSPAR) Display area (when "" is set into DSPAR) Display area (when "" is set into DSPAR) Display area (when "" is set into DSPAR) Display area (when "" is set into DSPAR) COM Fig /6 duty and 5 5 dots display memory map SC8F36 TECHNICAL MANUAL EPSON 3

126 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Controller) Address/Data bit F8H F842H F9H F942H FAH FA42H FBH FB42H FCH FC42H FDH FD42H D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 SEG A B C D E F A B C D E F A B C D E F A B C D E F 2 Display area (when "" is set into DSPAR) Display area (when "" is set into DSPAR) COM Fig /8 duty and 5 8 dots display memory map 4 EPSON SC8F36 TECHNICAL MANUAL

127 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Controller) Address/Data bit D D D2 D3 D4 D5 D A B C D E F A B C D E F A B C D E F A B C D E F 2 Display area (when "" is set into DSPAR) Display area (when "" is set into DSPAR) Display area (when "" is set into DSPAR) Display area (when "" is set into DSPAR) COM F8H F842H D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 SEG F9H F942H FAH FA42H FBH FB42H FCH FC42H FDH FD42H Fig /8 duty and 5 5 dots display memory map SC8F36 TECHNICAL MANUAL EPSON 5

128 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Controller) Display control The display status of the built-in LCD driver and the contrast adjustment can be controlled with the built-in LCD controller. The LCD display status can be selected by display control registers LCDC and LCDC. Setting the value and display status are shown in Table Table LCD display control LCDC LCDC LCD display All LCDs lit (Static) All LCDs out (Dynamic) Normal display Drive OFF All the dots in the LCD display can be turned on or off directly by the drive waveform output from the LCD driver, and data in the display memory is not changed. Also, since the common terminal at this time is set to static drive when all the dots are on and is set to dynamic drive when they are off, this function can be used as follows: () Since all dots on is binary output (VC5 and VSS) with static drive, the common/segment terminal can be used as a monitor terminal for the OSC oscillation frequency adjustment. (2) Since all dots off is dynamic drive, you can brink the entire LCD display without changing display memory data. Selecting LCD drive OFF turns the LCD drive power circuit OFF and all the VCVC5 terminals go to VSS level. However, if external power supply has been selected by the mask option, the VCVC5 shift to floating status when drive is turned OFF. Furthermore, when the SLP instruction is executed, registers LCDC and LCDC are automatically reset to "" (set to drive off) by hardware. The LCD contrast can be adjusted in 6 stages. This adjustment is done by the contrast adjustment register LCLC3, and the setting values correspond to the contrast as shown in Table However, if external power supply has been selected by the mask option, the contrast adjustment register LCLC3 is ineffective and contrast adjustment cannot be done. Table LCD contrast adjustment LC3 LC2 LC LC Contrast : : : : Dark Light CL and FR outputs In order for the SC8F36 to handle connection to an externally expanded LCD driver, output ports R25 and R26 can be used to output a CL signal (LCD synchronous signal) and FR signal (LCD frame signal), respectively. The configuration of output ports R25 and R26 are shown in Figure Register LCCLK Register R25D CL signal Register LCFRM Register R26D FR signal R25 output R26 output Fig Configuration of R25 and R26 The output control for the CL signal is done by the register LCCLK. When you set "" for the LCCLK, the CL signal is output from the output port terminal R25, when "" is set, the HIGH (VDD) level is output. At this time, "" must always be set for the data register R25D. The output control for the FR signal is done by the register LCFRM. When you set "" for the LCFRM, the FR signal is output from the output port terminal R26, when "" is set, the HIGH (VDD) level is output. At this time, "" must always be set for the data register R26D. The frequencies of each signal are changed as shown in Table according to the drive duty selection. Table Frequencies of CL and FR signals Drive duty /32 /6 /8 CL signal (Hz) 2,48,24,24 FR signal (Hz) Since the signals are generated asynchronously from the registers LCCLK and LCFRM, when the signals are turned ON or OFF by the register settings, a hazard of a /2 cycle or less is generated. Figure shows the output waveforms of the CL and FR signals. LCCLK/LCFRM CL output (R25) FR output (R26) Fig Output waveforms of CL and FR signals (when /6 duty is selected) Note: The CL and FR outputs are provided for supporting the SC883xx. When the TOUT output (mask option for the SC888xx) is selected for R26, the CL and FR signals cannot be output. 6 EPSON SC8F36 TECHNICAL MANUAL

129 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Controller) Control of LCD controller Table shows the LCD controller control bits. Table LCD controller control bits Address Bit Name Function SR Comment FF9 D7 D6 Constantly "" when D5 being read D4 D3 D2 LCDB Reserved D LCDAJ Power TYPE A (4.5V)/B (5.5V) switch TYPE A TYPE B D DUTY8 LCD drive duty switch /8 duty /6, /32 * FF D7 Constantly "" when D6 being read D5 D4 D3 D2 D D LCCLK LCFRM DTFNT LDUTY SGOUT CL output control for expanded LCD driver FR output control for expanded LCD driver LCD dot font selection LCD drive duty selection register On On 5 x 5 dots /6 duty Off Off 5 x 8 dots /32 duty * Reserved register FF D7 "" when being read D6 D5 DSPAR LCDC LCD display memory area selection LCD display control Display area Display area LCDC LCDC LCD display These bits are reset All LCDs lit to (, ) when D4 LCDC All LCDs out SLP instruction Normal display is executed. Drive off D3 LC3 LCD contrast adjustment D2 LC2 LC3 LC2 LC LC Contrast Dark D LC : : : : : : D LC Light * Writing "" to DUTY8 (FF9 D) disables /6 and /32 duty selection using LDUTY (FF D). SC8F36 TECHNICAL MANUAL EPSON 7

130 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Controller) LCDAJ: FF9H D Switches the internal power supply. When "" is written: TYPE A When "" is written: TYPE B Reading: Valid LCDAJ is the LCD power switching register. When "" is written, the LCD power supply is set for TYPE A (4.5 V) and when "" is written the LCD power supply is set for TYPE B (5.5 V). At initial reset, LCDAJ is set to "" (TYPE B). DUTY8: FF9H D Switches the drive duty. When "" is written: /8 duty When "" is written: /6 or /32 duty Reading: Valid DUTY8 is the drive duty switching register. When "" is written, /8 duty is selected and when "" is written, /6 or /32 duty is selected. When "" is written to DUTY8, switching between /6 duty and /32 duty using LDUTY becomes invalid. At initial reset, DUTY8 is set to "" (/6 or /32 duty). LDUTY: FFH D Selects the drive duty. When "" is written: /6 duty When "" is written: /32 duty Reading: Valid When "" is written to LDUTY, /32 duty is selected and the combined common/segment output terminal is switched to the common terminal. When "" is written to LDUTY, /6 duty is selected and the combined common/segment output terminal is switched to the segment terminal. When "" is written to DUTY8, the combined common/segment terminals are fixed to the segment terminals and the setting of LDUTY becomes invalid. The correspondence between the display memory bits set according to the drive duty, and the common/segment terminals are shown in Figures At initial reset, LDUTY is set to "" (/32 duty). DTFNT: FFH D2 Selects the dot font. When "" is written: 5 5 dots When "" is written: 5 8 dots Reading: Valid Select 5 8 dots or 5 5 dots type for the display memory area. When "" is written to DTFNT, 5 8 dots is selected and when "" is written, 5 5 dots is selected. The correspondence between the display memory bits set according to the dot font, and the common/ segment terminals are shown in Figures At initial reset, DTFNT is set to "" (5 8 dots). DSPAR: FFH D6 Selects the display area. When "" is written: Display area When "" is written: Display area Reading: Valid Selects which display area is secured for two screens in the display memory, will be displayed when /6 or /8 duty is selected. When "" is written to DSPAR, display area is selected and when "" is written, display area is selected. When /32 duty is selected, since the display area is only for one screen, the setting of DSPAR becomes invalid. The correspondence between the display memory bits set according to the display area, and the common/segment terminals are shown in Figures At initial reset, DSPAR is set to "" (display area ). LCDC, LCDC: FFH D4, D5 Controls the LCD display. Table LCD display control LCDC LCDC LCD display All LCDs lit (Static) All LCDs out (Dynamic) Normal display Drive OFF The four settings mentioned above can be made without changing the display memory data. At initial reset and in the SLEEP status, this register is set to "" (drive off). 8 EPSON SC8F36 TECHNICAL MANUAL

131 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Controller) LCLC3: FFH DD3 Adjusts the LCD contrast. Table LCD contract adjustment LC3 LC2 LC LC Contrast Dark Light 5.2. Programming notes () Since the CL and FR signals are generated asynchronously from the output control registers LCCLK and LCFRM, when the signals is turned ON or OFF by setting of the registers LCCLK and LCFRM, a hazard of a /2 cycle or less is generated. (2) When the SLP instruction is executed, display control registers LCDC and LCDC are automatically reset to "" by hardware. Furthermore, in the SLEEP status, HIGH (VDD) level is output for the CL and FR signals. (When registers R25D and R26D are set to "".) The contrast can be adjusted in 6 stages as mentioned above. This adjustment changes the drive voltage on terminals VCVC5. At initial reset, this register is set to "". LCCLK: FFH D4 Controls the CL signal output. When "" is written: CL signal output When "" is written: HIGH level (DC) output Reading: Valid LCCLK is the output control register for CL signal. When "" is set, the CL signal is output from the output port terminal R25 and when "" is set, HIGH (VDD) level is output. At this time, "" must always be set for the data register R25D. At initial reset, LCCLK is set to "" (HIGH level output). LCFRM: FFH D3 Controls the FR signal output. When "" is written: FR signal output When "" is written: HIGH level (DC) output Reading: Valid LCFRM is the output control register for FR signal. When "" is set, the FR signal is output from the output port terminal R26 and when "" is set, HIGH (VDD) level is output. At this time, "" must always be set for the data register R26D. At initial reset, LCFRM is set to "" (HIGH level output). SC8F36 TECHNICAL MANUAL EPSON 9

132 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Sound Generator) 5.3 Sound Generator 5.3. Configuration of sound generator The SC8F36 has a built-in sound generator for generating the buzzer (BZ and BZ) signal. The BZ signal generated from the sound generator can be output from the R5 output port terminal. Furthermore, the R5 terminal can be set as the BZ signal (BZ inverted signal) output by mask option. Aside permitting the respective setting of the buzzer signal frequency and sound level (duty adjustment) to 8 stages, it permits the adding of a digital envelope by means of duty ratio control. It also has a one-shot output function for outputting key operated sounds. Figure shows the configuration of the sound generator. OSC oscillation circuit fosc BZFQBZFQ2 Programmable dividing circuit ENRST ENRTM Control of buzzer output The BZ signal can be output from the R5 output port terminal. Furthermore, the R5 output port terminal can be used to output the BZ signal (BZ inverted signal) by mask option. The configuration of the output ports R5 and R5 is shown in Figure The output control for the buzzer signal generated by the sound generator is done by the buzzer output control register BZON, one-shot buzzer trigger bit BZSHT and one-shot buzzer forced stop bit BZSTP. When "" is set to BZON or BZSTP, the R5 goes LOW (VSS) and the R5 goes HIGH (VDD). To output the buzzer signal, "" must always be set for the data register R5D. The data register R5D does not affect the BZ output. Figure shows the output waveform of the buzzer signal. Note: Since the buzzer signal is generated asynchronously from the registers BZON, BZSHT and BZSTP, when the signal is turned ON or OFF by the register settings, a hazard of a / 2 cycle or less is generated. Dividing circuit 256 Hz Envelope addition circuit Duty ratio control circuit DUTYDUTY2 ENON BZSHT One-shot buzzer control circuit Buzzer output control circuit Output port R5, R5 BZ (R5) BZ (R5)* Note: BZSTP SHTPW BZON Fig Configuration of sound generator If the BZ terminal is used to drive an external component that consumes a large amount of current such as a bipolar transistor, design the pattern of traces on the printed circuit board so that the operation of the external component does not affect the IC power supply. Refer to <Output Terminals> in Section 8.4, "Precautions on Mounting", for more information. Register BZSHT Register BZSTP One-shot time up Register BZON Available when selected by mask option Register R5D BZ signal Register R5D S R Q Mask option Fig Configuration of R5 and R5 R5 output R5 output BZON/BZSHT BZ output (R5) BZ output (R5) * when selected by mask option Fig Buzzer output waveform 2 EPSON SC8F36 TECHNICAL MANUAL

133 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Sound Generator) Setting of buzzer frequency and sound level The buzzer signal is divided signal using the OSC oscillation circuit ( khz) as the clock source and 8 frequencies can be selected. This selection is done by the buzzer frequency selection register BZFQBZFQ2. The setting value and buzzer frequency correspondence is shown in Table By selecting the duty ratio of the buzzer signal from among 8 types, the buzzer sound level can be adjusted. This selection is made in the duty ratio selection register DUTYDUTY2. The setting value and duty ratio correspondence is shown in Table Level Level (Max) Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 (Min) DUTY2 Table Buzzer signal frequency settings BZFQ2 BZFQ BZFQ Buzzer frequency (Hz) Table Duty ratio settings Duty ratio by buzzer frequencies (Hz) DUTY DUTY /6 8/2 2/24 2/28 7/6 7/2 /24 /28 6/6 6/2 /24 /28 5/6 5/2 9/24 9/28 4/6 4/2 8/24 8/28 3/6 3/2 7/24 7/28 2/6 2/2 6/24 6/28 /6 /2 5/24 5/28 Duty ratio refers to the ratio of pulse width to the pulse cycle; given that HIGH level output time is TH, and low level output time is TL the BZ signal duty ratio becomes TH/(TH+TL) and the BZ signal duty ratio becomes TL/(TH+TL). When DUTYDUTY2 have all been set to "", the duty ratio becomes maximum and the sound level also becomes maximum. Conversely, when DUTYDUTY2 have all been set to "", the duty ratio becomes minimum and the sound level also becomes minimum. Note that the duty ratio setting differ depending on frequency. See Table Note: When using the digital envelope, the DUTYDUTY2 setting becomes invalid. Level (MAX) Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 (MIN) TH TL TL TH Level (MAX) Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 (MIN) (a) BZ signal (b) BZ signal Fig Duty ratio of buzzer signal waveform SC8F36 TECHNICAL MANUAL EPSON 2

134 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Sound Generator) Digital envelope A digital envelope with duty control can be added to the buzzer signal. The envelope can be realized by staged changing of the same duty ratio as detailed in Table in the preceding section from level (maximum) to level 8 (minimum). The addition of an envelope to the buzzer signal can be done by writing "" to the envelope control register ENON. When "" is written, the duty ratio is set at the level selected in DUTYDUTY2. BZFQ2 By writing "" to ENON to turn the buzzer output ON (writing "" to BZON), the buzzer signal with a level duty ratio is output, and then the duty ratio can be attenuated in stages to level 8. The attenuated envelope can be returned to level by writing "" to the envelope reset bit ENRST. When attenuated to level 8, the duty level remains at level 8 until the buzzer output is turned OFF (writing "" to BZON) or writing "" to ENRST. The stage changing time for the envelope level can be selected either 25 msec or 62.5 msec by the envelope attenuation time selection register ENRTM. Figure shows the timing chart of the digital envelope. No change of duty level ENON ENRST ENRTM BZON BZ signal duty ratio level (MAX) (MIN) t t2t3t4 t5 t6t7 t t t2 t3 t4 t5 t6 t7 + + t = msec t = 25 4 msec t27 = 62.5 msec t27 = 25 msec Fig Timing chart of digital envelope One-shot output The sound generator has a built-in one-shot output function for outputting a short duration buzzer signal for key operation sounds and similar effects. Either 25 msec or 3.25 msec can be selected by the one-shot buzzer duration selection register SHTPW for buzzer signal output time. The output control of the one-shot buzzer is done by writing "" to the one-shot buzzer trigger BZSHT, then the buzzer signal is output in synchronization with the internal 256 Hz signal from the output port terminal. Thereafter, when the set time has elapsed, the buzzer signal in synchronization with the 256 Hz signal automatically goes OFF in the same manner. The BZSHT can be read to determine status. When BZSHT is "", it indicates a BUSY status (during one-shot output) and when BZSHT is "", it indicates a READY status (during stop). When you want to turn the buzzer signal OFF prior to the elapse of the set time, the buzzer signal can be immediately stopped (goes OFF in asynchronization with 256 Hz signal) by writing "" to the one-shot forced stop bit BZSTP. Since the one-shot output has a short duration, an envelope cannot be added. (When "" is written to BZSHT, ENON is automatically reset to "".) Consequently, only the frequency and sound level can be set for one-shot output. The control for the one-shot output is invalid during normal buzzer output. Figure shows the timing chart of the oneshot output. 256 Hz SHTPW BZSHT(W) BZSHT(R) BZSTP BZ output (R5) BZ output (R5) * when selected by mask option Fig Timing chart of one-shot output 22 EPSON SC8F36 TECHNICAL MANUAL

135 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Sound Generator) Control of sound generator Table shows the sound generator control bits. Table Sound generator control bits Address Bit Name Function SR FF44 D7 D6 BZSTP One-shot buzzer forcibly stop Forcibly stop No operation W D5 BZSHT One-shot buzzer trigger/status R Busy Ready W Trigger No operation D4 SHTPW One-shot buzzer duration width selection 25 msec 3.25 msec D3 ENRTM Envelope attenuation time sec.5 sec D2 ENRST Envelope reset Reset No operation W D ENON Envelope On/Off control On Off D BZON Buzzer output control On Off FF45 D7 D6 DUTY2 Buzzer signal duty ratio selection DUTY2 2 D5 DUTY D4 DUTY D3 D2 BZFQ2 D BZFQ D BZFQ Buzzer frequency selection BZFQ2 Buzzer frequency (Hz) /6 7/6 6/6 5/6 4/6 3/6 2/6 /6 8/2 7/2 6/2 5/2 4/2 3/2 2/2 /2 2/24 /24 /24 9/24 8/24 7/24 6/24 5/24 2/28 /28 /28 9/28 8/28 7/28 6/28 5/28 BZFQ BZFQ Frequency (Hz) Comment Constantly "" when being read "" when being read * "" when being read "" when being read * Reset to "" during one-shot output. BZON: FF44H D Controls the buzzer (BZ and BZ) signal output. When "" is written: Buzzer signal output ON When "" is written: Buzzer signal output OFF Reading: Valid BZON is the output control register for buzzer signal. When "" is set to the register, the BZ (BZ) signal is output from the output port terminal R5 (R5). When "" is set, the R5 goes LOW (VSS) and the R5 goes HIGH (VDD). To output the BZ signal, "" must always be set for the data register R5D. The data register R5D does not affect the BZ output. At initial reset, BZON is set to "" (output OFF). The BZ signal can be output from R5 only when the function is selected by mask option. BZFQBZFQ2: FF45H DD2 Selects the buzzer signal frequency. Table Buzzer frequency settings BZFQ2 BZFQ BZFQ Buzzer frequency (Hz) The buzzer frequency can be selected from among the above 8 types that have divided the OSC clock. At initial reset, this register is set at "" (496. Hz). SC8F36 TECHNICAL MANUAL EPSON 23

136 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Sound Generator) DUTYDUTY2: FF45H D4D6 Selects the duty ratio of the buzzer signal. Table Duty ratio settings Level Level (Max) Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 (Min) DUTY2 DUTY DUTY Duty ratio by buzzer frequencies (Hz) /6 7/6 6/6 5/6 4/6 3/6 2/6 /6 8/2 7/2 6/2 5/2 4/2 3/2 2/2 /2 2/24 /24 /24 9/24 8/24 7/24 6/24 5/24 2/28 /28 /28 9/28 8/28 7/28 6/28 5/28 The buzzer sound level can be adjusted by selecting the duty ratio from among the above 8 types. However, when the envelope has been set to ON (ENON = ""), this setting becomes invalid. At initial reset, this register is set to "" (level ). ENRST: FF44H D2 Resets the envelope. When "" is written: Reset When "" is written: No operation Reading: Always "" The envelope is reset by writing "" to ENRST and the duty ratio returns to level (maximum). Writing "" to ENRST and writing "" when an envelope has not been added become invalid. Since ENRST is exclusively for writing, it always becomes "" during reading. ENON: FF44H D Controls the addition of an envelope to the buzzer signal. When "" is written: ON When "" is written: OFF Reading: Valid By writing "" to ENON, an envelope can be added to buzzer signal output. When "" is written, an envelope is not added and the buzzer signal is fixed at the duty ratio selected in DUTYDUTY2. At initial reset and when "" is written to BZSHT, ENON is set to "" (OFF). ENRTM: FF44H D3 Selects the envelope attenuation time that is added to the buzzer signal. When "" is written:. sec (25 msec 7 = 875 msec) When "" is written:.5 sec (62.5 msec 7 = msec) Reading: Valid The attenuation time of the digital envelope is determined by the time for changing the duty ratio. The duty ratio is changed in 25 msec (8 Hz) units when "" is written to ENRTM and in 62.5 msec (6 Hz) units, when "" is written. This setting becomes invalid when an envelope has been set to OFF (ENON = ""). At initial reset, ENRTM is set to "" (.5 sec). SHTPW: FF44H D4 Selects the output duration width of the one-shot buzzer. When "" is written: 25 msec When "" is written: 3.25 msec Reading: Valid The one-shot buzzer output duration width is set to 25 msec when "" is written to SHTPW and 62.5 msec, when "" is written. At initial reset, SHTPW is set to "" (3.25 msec). 24 EPSON SC8F36 TECHNICAL MANUAL

137 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Sound Generator) BZSHT: FF44H D5 Controls the one-shot buzzer output. When "" is written: Trigger When "" is written: No operation When "" is read: Busy When "" is read: Ready Writing "" into BZSHT causes the one-shot output circuit to operate. The BZ (BZ) signal is output from the R5 (R5) terminal. The buzzer output is automatically turned OFF after the time set by SHTPW has elapsed. To output the BZ signal, "" must always be set for the data register R5D. The data register R5D does not affect the BZ output. The one-shot output is only valid when the normal buzzer output is OFF (BZON = "") state. The trigger is invalid during ON (BZON = "") state. When a re-trigger is assigned during a one-shot output, the one-shot output time set with SHTPW is measured again from that point. (time extension) The operation status of the one-shot output circuit can be confirmed by reading BZSHT, when the oneshot output is ON, "" is read from BZSHTand when the output is OFF, "" is read. At initial reset, BZSHT is set to "" (ready). The BZ signal can be output from R5 only when the function is selected by mask option. BZSTP: FF44H D6 Forcibly stops the one-shot buzzer output. When "" is written: Forcibly stop When "" is written: No operation Reading: Constantly "" By writing "" into BZSTP, the one-shot buzzer output can be stopped prior to the elapsing of the time set with SHTPW. Writing "" is invalid and writing "" except during one-shot output is also invalid. When "" is written to BZSHT and BZSTP simultaneously, BZSTP takes precedence and one-shot output becomes stop status. Since BZSTP is for writing only, during readout it is constantly set to "" Programming notes () Since the buzzer signal is generated asynchronously from the register BZON, when the signal is turned ON or OFF by the register setting, a hazard of a /2 cycle or less is generated. (2) The SLP instruction has executed when the buzzer signal output is in the enable status (BZON = "" or BZSHT = ""), unstable clock is output from the output terminal at the time of return from the SLEEP status. Consequently, when shifting to the SLEEP status, you should set the buzzer signal output to the disable status (BZON = BZSHT = "") prior to executing the SLP instruction. (3) The one-shot output is only valid when the normal buzzer output is OFF (BZON = "") status. The trigger is invalid during ON (BZON = "") status. SC8F36 TECHNICAL MANUAL EPSON 25

138 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Analog Comparator) 5.4 Analog Comparator 5.4. Configuration of analog comparator The SC8F36 has an MOS input analog comparator built into two channels. The respective analog comparators have two differential input terminals (inverted input terminal CMPMx and non-inverted input terminal CMPPx) that are available for general purpose use. Figure shows the configuration of the analog comparator. CMPP (P4) CMPM (P5) CMPP (P6) CMPM (P7) + + VDD VSS VDD VSS <Channel > Latch <Channel > Latch CMPDT CMPON CMPDT CMPON Fig Configuration of analog comparator Since the input terminals of the analog comparator CMPP, CMPM, CMPP and CMPM are common to I/O ports P4P7, when using as the input terminal for the analog comparator, "" (input mode) must be written to I/O control registers IOC4IOC7. Table Input terminal configuration Terminal When analog comparator is used P4 CMPP P5 CMPM P6 CMPP P7 CMPM Data bus Mask option The input terminals of the analog comparator are shared with the I/O port terminals P4P7. Therefore, the terminal specification of the analog comparator is decided by setting the I/O port mask option. In the SC8F36, the P4P7 port specification is fixed at "without pull-up resistor" Analog comparator operation By writing "" to the analog comparator control register CMPxON, the analog comparator goes ON, and the analog comparator starts comparing the external voltages that have been input to the two differential input terminals CMPPx and CMPMx. The result can be read from the comparator comparison result detection bit CMPxDT through the latch and when CMPPx (+) > CMPMx (-), it is "" and when CMPPx (+) < CMPMx (-), it is "". After the analog comparator has been turned ON, a maximum time of 3 msec is necessary until output stabilizes. Consequently, you should allow an adequate waiting time after turning the analog comparator ON, before reading the comparison result. When the analog comparator is turned OFF, the comparison result at that point will be latched and the concerned data can be read thereafter, until the analog comparator is turned ON. You should turn the analog comparator OFF, when it is not necessary, so as to reduce current consumption. See Chapter, "ELECTRICAL CHARACTERISTICS" for the input voltage range. Note: Since the input terminals of the analog comparator are shared with the I/O ports, the I/O control registers (IOC4IOC7) corresponding to the channel to be used must be set to the input mode. Note: The P4P7 terminals are shared with the A/D converter input ports. Therefore, do not run the A/D converter when the analog comparator is used. 26 EPSON SC8F36 TECHNICAL MANUAL

139 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Analog Comparator) Control of analog comparator Table shows the analog comparator control bits. Table Analog comparator control bits Address Bit Name Function SR FF3 D7 D6 D5 D4 D3 D2 CMPON Comparator On/Off control CMPON Comparator On/Off control On On Off Off D D CMPDT CMPDT Comparator data Comparator data + > - + > - + < - + < - R R Comment Constantly "" when being read CMPON, CMPON: FF3H D2, D3 Controls the analog comparator ON/OFF. When "" is written: ON When "" is written: OFF Reading: Valid The analog comparator goes ON by writing "" to CMPON and goes OFF, when "" is written. The analog comparator can be controlled with CMPON in the same way. At initial reset, this register is set "" (OFF). CMPDT, CMPDT: FF3H D, D The comparison result of the analog comparator can be read out. When "" is read: CMPPx (+) > CMPMx (-) When "" is read: CMPPx (+) < CMPMx (-) Writing: Invalid The result of analog comparator can be read from CMPDT. When the status of external voltage input to differential input terminals CMPP and CMPM is CMPP (+) > CMPM (-), CMPDT becomes "" and when it is CMPP (+) < CMPM (-), CMPDT becomes "". As the same way, the comparison result between CMPP and CMPM can be read from CMPDT. When the analog comparator is turned OFF, the latched result immediately prior to going OFF is read out. At initial reset, this bit is set to "" Programming notes () To reduce current consumption, turn the analog comparator OFF (CMPON = CMPON = "") when it is not necessary. (2) After the analog comparator has been turned ON, a maximum time of 3 msec is necessary until output stabilizes. Consequently, you should allow an adequate waiting time after turning the analog comparator ON, before reading the comparison result. (3) Since the input terminals of the analog comparator are common to the I/O ports, the I/O control registers (IOC4IOC7) corresponding to the channel to be used must be set to the input mode. (4) The P4P7 terminals are shared with the A/D converter input ports. Therefore, do not run the A/D converter when the analog comparator is used. SC8F36 TECHNICAL MANUAL EPSON 27

140 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (A/D Converter) 5.5 A/D Converter 5.5. Characteristics and configuration of A/D converter The SC8F36 has a built-in A/D converter with the following characteristics. Conversion formula: Successive-approximation type Resolution: bits Input channel: Conversion time: Maximum 4 channels Minimum 22 µsec (in MHz operation) Setting of analog conversion voltage range is possible with reference voltage terminal (AVREF) A/D conversion result is possible to read from -bit data register Sample & hold circuit built-in A/D conversion completion generates an interrupt Figure shows the configuration of the A/D converter Terminal configuration of A/D converter The terminals used with the A/D converter are as follows: AVDD, AVSS (power supply input terminal) The AVDD and AVSS terminals are power supply terminals for the A/D converter. The voltage should be input as AVDD VDD and AVSS = VSS. AVREF (reference voltage input terminal) The AVREF terminal is the reference voltage terminal of the analog block. Input voltage range of the A/D conversion is decided by this input. The voltage should be input as AVREF AVDD. If the A/D converter is not used, the AVREF terminal should be left open. There is about 2 kω resistor connected between AVREF and AVSS in the chip. Therefore, a current passes if a voltage is applied to the AVREF terminal and power consumption increases according to the input voltage level. AD4AD7 (analog input terminal) The analog input terminals AD4AD7 are shared with the I/O port terminals P4P7. Therefore, it is necessary to set them for the A/D converter by software when using them as analog input terminals. This setting can be done for each terminal. (Refer to Section for setting.) At initial reset, all the terminals are set in the I/O port terminal. Analog voltage value AVIN that can be input is in the range of AVSS AVIN AVREF. Note: Since the P4P7 terminals are shared with the analog comparator, the A/D converter and the analog comparator cannot be used simultaneously. When using the A/D converter, do not run the analog comparator Mask option The input terminals of the A/D converter are shared with the I/O port terminals P4P7. Therefore, the terminal specification of the A/D converter is decided by setting the I/O port mask option. In the SC8F36, the P4P7 port specification is fixed at "Gate direct (no pull-up resistor)". AVDD AVREF AVSS -bit D/A converter Successive conversion register Converted data (ADDR) Comparator + AD4 (P4) AD5 (P5) AD6 (P6) AD7 (P7) Analog multiplexer Sample/hold circuit Control circuit Interrupt circuit Data bus fosc3/fosc3/64, fosc/ OSC3 oscillation circuit fosc3 Prescaler Fig Configuration of A/D converter 28 EPSON SC8F36 TECHNICAL MANUAL

141 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (A/D Converter) A/D conversion Setting the A/D input terminal When using the A/D converter, it is necessary to set up the terminals used for analog input from the P4P7 initialized as the I/O port terminals. Four terminals can all be used as analog input terminals. The PAD (PAD4PAD7) register is used to set analog input terminals. When the PAD register bits are set to "", the corresponding terminals function as the analog input terminals. Table Correspondence between A/D input terminal and PAD register Terminal P4 (AD4) P5 (AD5) P6 (AD6) P7 (AD7) A/D input control register PAD4 PAD5 PAD6 PAD7 Setting the input clock The A/D conversion clock can be selected from eight types shown in Table The selection is done using the PSAD register. Table Input clock selection Selection register PSAD PSAD2 PSAD Division ratio fosc/ fosc3/64 fosc3/32 fosc3/6 fosc3/8 fosc3/4 fosc3/2 fosc3/ Output control PRAD register "": ON "": OFF The selected clock is input to the A/D converter by writing "" to the PRAD register. Note: When the OSC3 oscillation circuit is made the clock source, it is necessary to turn the OSC3 oscillation ON, prior to using the A/D converter. From the time the OSC3 oscillation circuit is turning ON until oscillation stabilizes, an interval of several msec to several msec is necessary. Consequently, you should allow an adequate waiting time after turning the OSC3 oscillation circuit ON before starting the count of the programmable timer. (The oscillation start time will vary somewhat depending on the oscillator and on external parts. Refer to the oscillation start time example indicated in Chapter, "ELECTRICAL CHARAC- TERISTICS".) At initial reset, OSC3 oscillation circuit is set to OFF status. The clock division ratio (see Table ) must be set so that the A/D conversion clock frequency is MHz or less. Furthermore, the A/D conversion clock frequency should be changed according to the voltage to be used. Refer to Chapter, "ELECTRICAL CHARAC- TERISTICS". The input clock should be set when the A/D converter stops. Changing in the A/D converter operation may cause a malfunction. To prevent malfunction, do not start A/D conversion (writing to the CHS register) when the A/D conversion clock is not being output from the prescaler, and do not turn the prescaler output clock off during A/D conversion. Selecting the input signal The analog signals from the AD4 (P4)AD7 (P7) terminals are input to the multiplexer, and the analog input channel for A/D conversion is selected by software. This selection can be done using the CHS register as shown in Table Table Selection of analog input channel CHS CHS Input channel AD7 AD6 AD5 AD4 A/D conversion operation An A/D conversion starts by writing data to the ADRUN register. For example, when performing A/D conversion using AD7 as the analog input, write "" (, ) to the CHS register (CHS, CHS) and then write "" to the ADRUN register. The A/D input channel is selected and the A/D conversion starts. However, it is necessary that the P7 terminal has been set as an analog input terminal. The built-in sample & hold circuit starts sampling of the analog input specified from tad after writing. When the sampling is completed, the held analog input voltage is converted into a -bit digital value in successive-approximation architecture. The conversion result is loaded into the ADDR (ADDRADDR9) register. ADDR is the LSB and ADDR9 is the MSB. SC8F36 TECHNICAL MANUAL EPSON 29

142 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (A/D Converter) Note: If the CHS register selects an input channel which is not included in the analog input terminals set by the PAD register (the PAD register can select several terminals simultaneously), the A/D conversion does not result in a correct converted value. Example) Terminal setting: PAD5 =, PAD7 = PAD6 = PAD4 = (AD5 terminal is used) Selection of input channel: CHS =, CHS = (AD4 is selected) In a setting like this, the A/D conversion result will be invalid because the contents of the settings are not matched. Setting of analog input terminals (PAD) Setting of input clock (PSAD) Turning clock output ON (PRAD) Writing to CHS register =selection of analog input channel Writing to ADRUN register =starting A/D conversion Fig Flowchart for starting A/D conversion Interrupt function The A/D converter can generate an interrupt when an A/D conversion has completed. Figure shows the configuration of the A/D converter interrupt circuit. The A/D converter sets the interrupt factor flag FAD to "" when it stores the conversion. At this time, if the interrupt enable register EAD is "" and the interrupt priority register PADC (2 bits) is set to a higher level than the setting of the interrupt flags (I and I), an interrupt is generated to the CPU. By setting the EAD register to "", the interrupt to the CPU can also be disabled. However, the interrupt factor flag is set to "" when an A/D conversion has completed regardless of the interrupt enable register and interrupt priority register settings. The interrupt factor flag set in "" is reset to "" by writing "". Refer to Section 5.7, "Interrupt and Standby Status", for details of the interrupt control registers and operations subsequent to interrupt generation. The exception processing vector address for the A/D conversion completion interrupt has been set in 24H. An A/D conversion is completed when the conversion result is loaded into the ADDR register. At that point, the A/D converter generates an interrupt (explained in the next section). Figure shows the timing chart of A/D conversion. Writing to ADRUN register Input sampling Successive conversion ADDR register Conversion result Interrupt request tad Sampling time 8tCLK A/D conversion time 2tCLK+tAD tad: tclk: to tclk Input clock cycle Fig Timing chart of A/D conversion Data bus A/D conversion completion Address Address Interrupt factor flag FAD Interrupt enable register EAD Interrupt priority level judgment circuit Interrupt request Interrupt priority register PADC, PADC Address Fig Configuration of A/D converter interrupt circuit 3 EPSON SC8F36 TECHNICAL MANUAL

143 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (A/D Converter) Control of A/D converter Table shows the A/D converter control bits. Table (a) A/D converter control bits Address Bit Name Function SR FF8 D7 D6 D5 D4 D3 PRAD A/D converter clock control On Off D2 PSAD2 A/D converter division ratio D PSAD D PSAD PSAD2 PSAD PSAD Division ratio fosc / fosc3 / 64 fosc3 / 32 fosc3 / 6 fosc3 / 8 fosc3 / 4 fosc3 / 2 fosc3 / Comment Constantly "" when being read FF8 D7 D6 D5 D4 D3 D2 D D FF82 D7 D6 D5 D4 D3 D2 D D FF83 D7 D6 D5 D4 D3 D2 D D FF84 D7 D6 D5 D4 D3 D2 D D PAD7 PAD6 PAD5 PAD4 ADRUN CHS CHS ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR ADDR P7 A/D converter input control P6 A/D converter input control P5 A/D converter input control P4 A/D converter input control A/D conversion start control register Analog input channel selection CHS CHS Input channel AD7 AD6 AD5 AD4 A/D conversion result D9 (MSB) A/D conversion result D8 A/D conversion result D7 A/D conversion result D6 A/D conversion result D5 A/D conversion result D4 A/D conversion result D3 A/D conversion result D2 A/D conversion result D A/D conversion result D (LSB) A/D converter input Start I/O port Invalid W R R Constantly "" when being read Constantly "" when being read Constantly "" when being read SC8F36 TECHNICAL MANUAL EPSON 3

144 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (A/D Converter) D5 D4 D3 D2 D D FF2A D7 EAD D6 D5 D4 D3 D2 D D FF2C D7 FAD Table (b) A/D converter control bits Address Bit Name Function SR FF28 D7 PADC A/D converter interrupt priority register PADC PADC Priority Level 3 D6 PADC Level 2 D6 D5 D4 D3 D2 D D Reserved Reserved A/D converter interrupt enable register Reserved A/D converter interrupt factor flag Reserved R) W) Prohibited Prohibited Enable Generated Reset Level Level Disable Not generated No operation Comment Do not write "". Constantly "" when being read Constantly "" when being read Constantly "" when being read PAD4PAD7: FF8H D4D7 Sets the P4P7 terminals as the analog input terminals for the A/D converter. When "" is written: A/D converter input When "" is written: I/O port Reading: Valid When "" is written to PADn, the Pn terminal is set to the analog input terminal ADn. (n=47) When "" is written, the terminal is used with the I/ O port. At initial reset, this register is set to "" (I/O port). PSADPSAD2: FF8H DD2 Selects the clock for the A/D converter. Table Input clock selection Selection register PSAD2 PSAD PSAD Division ratio fosc/ fosc3/64 fosc3/32 fosc3/6 fosc3/8 fosc3/4 fosc3/2 fosc3/ Output control PRAD register "": ON "": OFF This setting controls the division ratio of the prescaler. At initial reset, this register is set to "" (fosc3/). 32 EPSON SC8F36 TECHNICAL MANUAL

145 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (A/D Converter) PRAD: FF8H D3 Controls the clock supply to the A/D converter. When "" is written: ON When "" is written: OFF Reading: Invalid By writing "" to the PRAD register, the clock selected with the PSAD register is input to the A/D converter. When "" is written, the clock is not input to the A/D converter. At initial reset, this register is set to "" (OFF). ADRUN: FF82H D7 Starts A/D conversion. When "" is written: Start A/D conversion When "" is written: Invalid Reading: Always "" By writing "" to this register, the A/D converter starts A/D conversion of the channel selected by the CHS register, and stores the conversion result to the ADDR register. CHS, CHS: FF82H D, D Selects an analog input channel. Table Selection of analog input channel CHS CHS Input channel AD7 AD6 AD5 AD4 At initial reset, this register is set to "" (AD4). ADDRADDR9: FF84H D, D, FF83H A/D conversion result is stored. ADDR is the LSB and ADDR9 is the MSB. ADDR and ADDR are assigned in D bit and D bit of the address FF84H. D2D7 bits in this address are always "" when being read. At initial reset, data is undefined. PADC, PADC: FF28H D6, D7 Sets the priority level of the A/D conversion completion interrupt. Table shows the interrupt priority level which can be set by the PADC register. Table Interrupt priority level settings PADC PADC Interrupt priority level Level 3 Level 2 Level Level (IRQ3) (IRQ2) (IRQ) (None) At initial reset, this register is set to "" (level ). EAD: FF2AH D7 Enables or disables the A/D conversion completion interrupt generation to the CPU. When "" is written: Interrupt is enabled When "" is written: Interrupt is disabled Reading: Valid The EAD register is the interrupt enable register corresponding to the A/D conversion completion interrupt factor. When this register is set to "", the interrupt is enabled, and when it is set to "", the interrupt is disabled. At initial reset, this register is set to "" (interrupt is disabled). FAD: FF2CH D7 Indicates the generation of A/D conversion completion interrupt factor. When "" is read: Int. factor has generated When "" is read: Int. factor has not generated When "" is written: Factor flag is reset When "" is written: Invalid FAD is the interrupt factor flag corresponding to the A/D conversion completion interrupt. It is set to "" when an A/D conversion is completed. At this point, if the corresponding interrupt enable register is set to "" and the corresponding interrupt priority register is set to a higher level than the setting of the interrupt flags (I and I), an interrupt is generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag is set to "" when the interrupt generation condition is met. To accept the subsequent interrupt after an interrupt generation, it is necessary to re-set the interrupt flags (set the interrupt flag to a lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and to reset the interrupt factor flag. The interrupt factor flag is reset to "" by writing "". At initial reset, the FAD flag is reset to "". SC8F36 TECHNICAL MANUAL EPSON 33

146 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (A/D Converter) Programming notes () When the OSC3 oscillation circuit is made the clock source, it is necessary to turn the OSC3 oscillation ON, prior to using the A/D converter. From the time the OSC3 oscillation circuit is turning ON until oscillation stabilizes, an interval of several msec to several msec is necessary. Consequently, you should allow an adequate waiting time after turning the OSC3 oscillation circuit ON before starting the count of the programmable timer. (The oscillation start time will vary somewhat depending on the oscillator and on external parts. Refer to the oscillation start time example indicated in Chapter, "ELECTRICAL CHARACTERIS- TICS".) At initial reset, OSC3 oscillation circuit is set to OFF status. (2) When SLEEP mode is set during A/D conversion, correct A/D conversion result cannot be obtained because the OSC3 oscillation circuit stops. Do not set in SLEEP mode during A/D conversion. (3) The input clock and analog input terminals should be set when the A/D converter stops. Changing in the A/D converter operation may cause a malfunction. (4) The clock division ratio (see Table ) must be set so that the A/D conversion clock frequency is MHz or less. Furthermore, the A/D conversion clock frequency should be changed according to the voltage to be used. Refer to Chapter, "ELECTRICAL CHARACTERIS- TICS". (5) To prevent malfunction, do not start A/D conversion (writing to the CHS register) when the A/D conversion clock is not being output from the prescaler, and do not turn the prescaler output clock off during A/D conversion. (6) If the CHS register selects an input channel which is not included in the analog input terminals set by the PAD register (the PAD register can select several terminals simultaneously), the A/D conversion does not result in a correct converted value. (7) During A/D conversion, do not operate the Pn terminals which are not used for analog inputs of the A/D converter (for input/output of digital signal and for D/A conversion). It affects the A/D conversion precision. (8) Since the P4P7 terminals are shared with the analog comparator, the A/D converter and the analog comparator cannot be used simultaneously. When using the A/D converter, do not run the analog comparator. (9) Note that writing "" to the A/D converter control bits (FF28H D5, D4) may cause a malfunction. 34 EPSON SC8F36 TECHNICAL MANUAL

147 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (SVD Circuit) 5.6 Supply Voltage Detection (SVD) Circuit 5.6. Configuration of SVD circuit The SC8F36 has a built-in supply voltage detection (SVD) circuit configured with a 4-bit successive approximation A/D converter. The SVD circuit has 6 sampling levels (level level 5) for supply voltage, and this can be controlled by software. Figure shows the configuration of the SVD circuit Mask option In the SC8F36, the optional SVD reset function is not available Operation of SVD circuit Sampling control of the SVD circuit The SVD circuit has two operation modes: continuous sampling and /4 Hz auto-sampling mode. Operation mode selection is done by the SVD control registers SVDON and SVDSP as shown in Table When both bits of SVDON and SVDSP are set to "", continuous sampling is selected. Table Correspondence between control register and operation mode SVDON SVDSP Operating mode SVD circuit OFF /4 Hz auto-sampling ON Continuous sampling ON In both operation modes, reading SVDON can confirm whether the SVD circuit is operating (BUSY) or on standby (READY); "" indicates BUSY and "" indicates READY. When executing an SLP instruction while the SVD circuit is operating, the stop operation of the OSC oscillation circuit is kept waiting until the sampling is completed. The two bits of SVDON and SVDSP are automatically reset to "" by hardware while waiting for completion of sampling. To reduce current consumption, turn the SVD circuit OFF when it is not necessary. Detection result The SVD circuit A/D converts the supply voltage (VDDVSS) by 4-bit resolution and sets the result thereof into the SVDSVD3 register. The data in SVDSVD3 correspond to the detection levels as shown in Table and the detection data is maintained until the next sampling. For the correspondence between the detection level and the supply voltage, see Chapter, "ELECTRI- CAL CHARACTERISTICS". An interval of 7.8 msec (fosc = khz) is required from the start of supply voltage sampling by the SVD circuit to completion by writing the result into SVDSVD3. Therefore, when reading SVDSVD3 before sampling is finished, the previous result will be read. OSC oscillation circuit VDD Reference voltage generation circuit fosc Dividing circuit 4-bit A/D converter 2,48 Hz Sampling control /4 Hz circuit SVD3 SVD2 SVD SVD SVDON SVDSP Fig Configuration of SVD circuit Data bus SC8F36 TECHNICAL MANUAL EPSON 35

148 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (SVD Circuit) Table Supply voltage detection results SVD3 SVD2 SVD SVD Detection level Level 5 Level 4 Level 3 Level 2 Level Level Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 Level Level Timing of sampling Next, we will explain the timing for two operation modes. () Continuous sampling mode This mode is selected when "" is written to SVDON and sampling of the supply voltage is done continuously in 7.8 msec cycles. The SVD circuit starts operation in synchronization with the internal 2,48 Hz signal and performs one sampling in 6 clock cycles. The sampling is done continuously without setting the standby time and the result is latched to SVDSVD3 in every 6 clock cycles. Cancellation of continuous sampling is done by writing "" to SVDON. The SVD circuit maintains ON status until completion of sampling and then goes OFF. After writing "" to SVDON, SVDON reads "" until the SVD circuit actually goes OFF. Figure shows the timing chart of the continuous sampling. (2) /4 Hz auto-sampling mode This mode is selected when "" is written to SVDON and "" is written to SVDSP. In this case, supply voltage sampling is done in every 4 seconds. The sampling time is 7.8 msec as in continuous sampling, and the result in SVDSVD3 is updated every 4 seconds. Cancellation of /4 Hz auto-sampling is done by writing "" to SVDSP. If the SVD circuit is sampling, SVD circuit waits until completion and then turns OFF. In addition, "" is read from SVDON while the SVD circuit is sampling. Figure shows the timing chart of the /4 Hz auto-sampling. 2,48 Hz SVDON(W) SVDON(R) Latch () () SVDSVD3 Sampling (7.8 msec) Fig Timing chart of continuous sampling Hz SVDSP(W) SVDON(R) SVDSVD3 Sampling (7.8 msec) Standby status 4 sec Fig Timing chart of /4 Hz auto-sampling 36 EPSON SC8F36 TECHNICAL MANUAL

149 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (SVD Circuit) Control of SVD circuit Table shows the SVD circuit control bits. Table SVD circuit control bits Address Bit Name Function SR FF2 D7 D6 D5 SVDSP SVD auto-sampling control On Off D4 SVDON SVD continuous sampling control/status D3 SVD3 D2 SVD2 D SVD D SVD SVD detection level SVD3 SVD2 SVD : : : SVD : R W Detection level Level 5 Level 4 : Level Busy On Ready Off * After initial reset, this status is set "" until conclusion of hardware first sampling. *2 Initial values are set according to the supply voltage detected at first sampling by hardware. Until conclusion of first sampling, SVDSVD3 data are undefined. * X R X R X R X R Comment Constantly "" when being read These registers are reset to "" when SLP instruction is executed. *2 SVDON: FF2H D4 Controls the turning ON/OFF of the continuous sampling mode. When "" is written: Continuous sampling ON When "" is written: Continuous sampling OFF When "" is read: BUSY When "" is read: READY The continuous sampling mode goes ON when "" is written to SVDON and goes OFF, when "" is written. In the ON status, sampling of the supply voltage is done continuously in 7.8 msec cycles and the detection result is latched to SVDSVD3. SVDON can be read, and "" indicates SVD circuit operation (BUSY) and "" indicates standby (READY). At initial reset and in the SLEEP status, SVDON is set to "" (continuous sampling OFF/READY). SVDSP: FF2H D5 Controls the turning ON/OFF of the /4 Hz autosampling mode. When "" is written: Auto-sampling ON When "" is written: Auto-sampling OFF Reading: Valid The /4 Hz auto-sampling mode goes ON when "" is written to SVDSP and goes OFF, when "" is written. In the ON status, sampling is done in every 4 seconds and "" is read from SVDON during the actual sampling period (7.8 msec). At initial reset and in the SLEEP status, SVDSP is set to "" (auto-sampling OFF). SVDSVD3: FF2H DD3 The detection result of the SVD is set. The reading data correspond to the detection levels as shown in Table and the data is maintained until the next sampling. Table Supply voltage detection results SVD3 SVD2 SVD SVD Detection level Level 5 Level 4 Level 3 Level 2 Level Level Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 Level Level For the correspondence between the detection level and the supply voltage, see Chapter, "ELECTRI- CAL CHARACTERISTICS". The initial value at initial reset is set according to the supply voltage detected at first sampling by hardware. Data of this bit is undefined until this sampling is completed. SC8F36 TECHNICAL MANUAL EPSON 37

150 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (SVD Circuit) Programming notes () To reduce current consumption, turn the SVD circuit OFF (SVDON = SVDSP = "") when it is not necessary. (2) When executing an SLP instruction while the SVD circuit is operating, the stop operation of the OSC oscillation circuit is kept waiting until the sampling is completed. The two bits of SVDON and SVDSP are automatically reset to "" by hardware while waiting for completion of sampling. 38 EPSON SC8F36 TECHNICAL MANUAL

151 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status) 5.7 Interrupt and Standby Status Types of interrupts 7 systems and 6 types of interrupts have been provided for the SC8F36. External interrupt KK7 input interrupt (2 types) K and K input interrupt ( type) Internal interrupt Clock timer interrupt (4 types) Stopwatch timer interrupt (3 types) Programmable timer interrupt (2 types) Serial interface interrupt (3 types) A/D converter interrupt ( type) An interrupt factor flag that indicates the generation of an interrupt factor and an interrupt enable register that sets enable/disable for interrupt requests have been provided for each interrupt and interrupt generation can be optionally set for each factor. In addition, an interrupt priority register has been provided for each system of interrupts and the priority of interrupt processing can be set to 3 levels in each system. Figure 5.7. shows the configuration of the interrupt circuit. Refer to the explanations of the respective peripheral circuits for details on each interrupt. Interrupt factor flag Interrupt enable register Interrupt priority register Interrupt vector address generation circuit Vector address Data bus Programmable timer Timer Timer K, K FPT EPT FPT EPT FK EK PPT PPT Input port K4K7 KK3 Error FKH EKH FKL EKL FSERR ESERR PK PK PK PK Serial interface Stopwatch timer Receive Transmit Hz Hz Hz FSREC ESREC FSTRA ESTRA FSW ESW FSW ESW FSW ESW PSIF PSIF PSW PSW Interrupt priority level judgment circuit NMI IRQ3 IRQ2 IRQ 32 Hz FTM32 ETM32 Clock timer 8 Hz 2 Hz Hz FTM8 ETM8 FTM2 ETM2 FTM ETM PTM PTM A/D converter A/D conversion completion FAD EAD PADC PADC Fig Configuration of interrupt circuit SC8F36 TECHNICAL MANUAL EPSON 39

152 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status) HALT status By executing the program's HALT instruction, the SC8F36 shifts to the HALT status. Since CPU operation stops in the HALT status, power consumption can be reduced with only peripheral circuit operation. Cancellation of the HALT status is done by initial reset or an optional interrupt request, and the CPU restarts program execution from an exception processing routine. See the "SC88 Core CPU Manual" for the HALT status and reactivation sequence. SLEEP status By executing the program's SLP instruction, the SC8F36 shifts to the SLEEP status. Since the operation of the CPU and peripheral circuits stop completely in the SLEEP status, power consumption can be reduced even more than in the HALT status. Cancellation of the SLEEP status is done by initial reset or an input interrupt from the input port. The CPU reactivates after waiting 8,92/fOSC seconds of oscillation stabilization time. At this time, the CPU restarts program execution from an exception processing routine (input interrupt routine). Note: Since oscillation is unstable for a short time after reactivation from the SLEEP status, the wait time is not always 25 msec even when using the khz crystal oscillator for the OSC oscillation circuit Interrupt generation conditions The interrupt factor flags that indicate the generation of their respective interrupt factors are provided for the previously indicated 7 systems and 6 types of interrupts and they will be set to "" by the generation of a factor. Table Interrupt factors Interrupt factor In addition, interrupt enable registers with a to correspondence to each of the interrupt factor flags are provided. An interrupt is enabled when "" is written and interrupt is disabled when "" is written. The CPU manages the enable/disable of interrupt requests at the interrupt priority level. An interrupt priority register that sets the priority level is provided for each of the interrupts of the 7 systems and the CPU accepts only interrupts above the level that has been indicated with the interrupt flags (I and I). Consequently, the following three conditions are necessary for the CPU to accept the interrupt. () The interrupt factor flag has been set to "" by generation of an interrupt factor. (2) The interrupt enable register corresponding to the above has been set to "". (3) The interrupt priority register corresponding to the above has been set to a priority level higher than the interrupt flag (I and I) setting. The CPU initially samples the interrupt for the first op-code fetch cycle of each instruction. Thereupon, the CPU shifts to the exception processing when the above mentioned conditions have been established. See the "SC88 Core CPU Manual" for the exception processing sequence Interrupt factor flag Programmable timer underflow Programmable timer underflow Non matching of the K and K inputs and the input comparison registers KCP and KCP Non matching of the K4K7 inputs and the input comparison registers KCP4KCP7 Non matching of the KK3 inputs and the input comparison registers KCPKCP3 Serial interface receiving error (in asynchronous mode) Serial interface receiving completion Serial interface transmitting completion Falling edge of the stopwatch timer Hz signal Falling edge of the stopwatch timer Hz signal Falling edge of the stopwatch timer Hz signal Rising edge of the clock timer 32 Hz signal Rising edge of the clock timer 8 Hz signal Rising edge of the clock timer 2 Hz signal Rising edge of the clock timer Hz signal A/D conversion completion Table shows the correspondence between the factors generating an interrupt and the interrupt factor flags. The corresponding interrupt factor flags are set to "" by generation of the respective interrupt factors. The corresponding interrupt factor can be confirmed by reading the flags through software. Interrupt factor flag FPT (FF25 D7) FPT (FF25 D6) FK (FF25 D5) FKH (FF25 D4) FKL (FF25 D3) FSERR (FF25 D2) FSREC (FF25 D) FSTRA (FF25 D) FSW (FF24 D6) FSW (FF24 D5) FSW (FF24 D4) FTM32 (FF24 D3) FTM8 (FF24 D2) FTM2 (FF24 D) FTM (FF24 D) FAD (FF2C D7) 4 EPSON SC8F36 TECHNICAL MANUAL

153 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status) Interrupt factor flag that has been set to "" is reset to "" by writing "". At initial reset, the interrupt factor flags are reset to "". Note: When executing the RETE instruction without resetting the interrupt factor flag after an interrupt has been generated, the same interrupt will be generated. Consequently, the interrupt factor flag corresponding to that routine must be reset (writing "") in the interrupt processing routine Interrupt enable register The interrupt enable register has a to correspondence with each interrupt factor flag and enable/disable of interrupt requests can be set. When "" is written to the interrupt enable register, an interrupt request is enabled, and is disabled when "" is written. This register also permits reading, thus making it possible to confirm that a status has been set. At initial reset, the interrupt enable registers are set to "" and shifts to the interrupt disable status. Table shows the correspondence between the interrupt enable registers and the interrupt factor flags Interrupt priority register and interrupt priority level The interrupt priority registers shown in Table are set to each system of interrupts and the interrupt priority levels for the CPU can be set to the optional priority level (3). As a result, it is possible to have multiple interrupts that match the system's interrupt processing priority levels. The interrupt priority level between each system can optionally be set to three levels by the interrupt priority register. However, when more than one system is set to the same priority level, they are processed according to the default priority level. Table Setting of interrupt priority level P* P* Interrupt priority level Level 3 (IRQ3) Level 2 (IRQ2) Level (IRQ) Level (non) Table Interrupt enable registers and interrupt factor flags Interrupt Interrupt factor flag Interrupt enable register Programmable timer FPT (FF25 D7) EPT (FF23 D7) Programmable timer FPT (FF25 D6) EPT (FF23 D6) K and K input FK (FF25 D5) EK (FF23 D5) K4K7 input FKH (FF25 D4) EKH (FF23 D4) KK3 input FKL (FF25 D3) EKL (FF23 D3) Serial interface receiving error FSERR (FF25 D2) ESERR (FF23 D2) Serial interface receiving completion FSREC (FF25 D) ESREC (FF23 D) Serial interface transmitting completion FSTRA (FF25 D) ESTRA (FF23 D) Stopwatch timer Hz FSW (FF24 D6) ESW (FF22 D6) Stopwatch timer Hz FSW (FF24 D5) ESW (FF22 D5) Stopwatch timer Hz FSW (FF24 D4) ESW (FF22 D4) Clock timer 32 Hz FTM32 (FF24 D3) ETM32 (FF22 D3) Clock timer 8 Hz FTM8 (FF24 D2) ETM8 (FF22 D2) Clock timer 2 Hz FTM2 (FF24 D) ETM2 (FF22 D) Clock timer Hz FTM (FF24 D) ETM (FF22 D) A/D conversion completion FAD (FF2C D7) EAD (FF2A D7) Table Interrupt priority register Interrupt Interrupt priority register Programmable timer interrupt PPT, PPT (FF2 D2, D3) K and K input interrupt PK, PK (FF2 D, D) KK7 input interrupt PK, PK (FF2 D6, D7) Serial interface interrupt PSIF, PSIF (FF2 D4, D5) Stopwatch timer interrupt PSW, PSW (FF2 D2, D3) Clock timer interrupt PTM, PTM (FF2 D, D) A/D converter interrupt PADC, PADC (FF28 D6, D7) SC8F36 TECHNICAL MANUAL EPSON 4

154 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status) At initial reset, the interrupt priority registers are all set to "" and each interrupt is set to level. Furthermore, the priority levels in each system have been previously decided and they cannot be changed. The CPU can mask each interrupt by setting the interrupt flags (I and I). The relation between the interrupt priority level of each system and interrupt flags is shown in Table , and the CPU accepts only interrupts above the level indicated by the interrupt flags. The NMI (watchdog timer) that has level 4 priority, is always accepted regardless of the setting of the interrupt flags. Table Interrupt mask setting of CPU I I Acceptable interrupt Level 4 (NMI) Level 4, Level 3 (IRQ3) Level 4, Level 3, Level 2 (IRQ2) Level 4, Level 3, Level 2, Level (IRQ) After an interrupt has been accepted, the interrupt flags are written to the level of that interrupt. However, interrupt flags after an NMI has been accepted are written to level 3 (I = I = ""). Table Interrupt flags after acceptance of interrupt Accepted interrupt priority level I I Level 4 (NMI) Level 3 (IRQ3) Level 2 (IRQ2) Level (IRQ) The set interrupt flags are reset to their original value on return from the interrupt processing routine. Consequently, multiple interrupts up to 3 levels can be controlled by the initial settings of the interrupt priority registers alone. Additional multiplexing can be realized by rewriting the interrupt flags and interrupt enable register in the interrupt processing routine. Note: Beware. If the interrupt flags have been rewritten (set to lower priority) prior to resetting an interrupt factor flag after an interrupt has been generated, the same interrupt will be generated again Exception processing vectors When the CPU accepts an interrupt request, it starts exception processing following completion of the instruction being executed. In exception processing, the following operations branch the program. () In the minimum mode, the program counter (PC) and system condition flag (SC) are moved to stack and in the maximum mode, the code bank register (CB), PC and SC are moved. (2) The branch destination address is read from the exception processing vector corresponding to each exception processing (interrupt) factor and is placed in the PC. An exception vector is 2 bytes of data in which the top address of each exception (interrupt) processing routine has been stored and the vector addresses correspond to the exception processing factors as shown in Table Table Vector address and exception processing correspondence Vector address Exception processing factor Priority H Reset High 2H Zero division 4H Watchdog timer (NMI) 6H Programmable timer interrupt 8H Programmable timer interrupt AH K, K input interrupt CH K4K7 input interrupt EH KK3 input interrupt H Serial I/F error interrupt 2H Serial I/F receiving complete interrupt 4H Serial I/F transmitting complete interrupt 6H Stopwatch timer Hz interrupt 8H Stopwatch timer Hz interrupt AH Stopwatch timer Hz interrupt CH Clock timer 32 Hz interrupt EH Clock timer 8 Hz interrupt 2H Clock timer 2 Hz interrupt 22H Clock timer Hz interrupt 24H A/D converter interrupt Low 26H System reserved (cannot be used) No 28H priority : Software interrupt rating FEH Note: An exception processing vector is fixed at 2 bytes, so it cannot specify a branch destination bank address. Consequently, to branch from multiple banks to a common exception processing routine, the top portion of an exception processing routine must be described within the common area (H7FFFH). 42 EPSON SC8F36 TECHNICAL MANUAL

155 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status) Control of interrupt Table shows the interrupt control bits. Table (a) Interrupt control bits Address Bit Name Function SR FF2 D7 D5 D3 D PK PSIF PSW PTM D6 D4 D2 D PK PSIF PSW PTM KK7 interrupt priority register Serial interface interrupt priority register Stopwatch timer interrupt priority register Clock timer interrupt priority register FF2 D7 D6 D5 D4 D3 PPT D2 PPT Programmable timer interrupt priority register D PK D PK K and K interrupt priority register FF22 D7 D6 ESW Stopwatch timer Hz interrupt enable register D5 ESW Stopwatch timer Hz interrupt enable register D4 ESW Stopwatch timer Hz interrupt enable register D3 ETM32 Clock timer 32 Hz interrupt enable register D2 ETM8 Clock timer 8 Hz interrupt enable register D ETM2 Clock timer 2 Hz interrupt enable register D ETM Clock timer Hz interrupt enable register FF23 D7 EPT Programmable timer interrupt enable register D6 EPT Programmable timer interrupt enable register D5 EK K and K interrupt enable register D4 EKH K4K7 interrupt enable register D3 EKL KK3 interrupt enable register D2 ESERR Serial I/F (error) interrupt enable register D ESREC Serial I/F (receiving) interrupt enable register D ESTRA Serial I/F (transmitting) interrupt enable register FF24 D7 D6 FSW Stopwatch timer Hz interrupt factor flag D5 FSW Stopwatch timer Hz interrupt factor flag D4 FSW Stopwatch timer Hz interrupt factor flag D3 FTM32 Clock timer 32 Hz interrupt factor flag D2 FTM8 Clock timer 8 Hz interrupt factor flag D FTM2 Clock timer 2 Hz interrupt factor flag D FTM Clock timer Hz interrupt factor flag FF25 D7 FPT Programmable timer interrupt factor flag D6 FPT Programmable timer interrupt factor flag D5 FK K and K interrupt factor flag D4 FKH K4K7 interrupt factor flag D3 FKL KK3 interrupt factor flag D2 FSERR Serial I/F (error) interrupt factor flag D FSREC Serial I/F (receiving) interrupt factor flag D FSTRA Serial I/F (transmitting) interrupt factor flag PK PSIF PSW PTM PPT PK Interrupt enable Interrupt enable PK PSIF PSW PTM PPT PK (R) Interrupt factor is generated (W) Reset (R) Interrupt factor is generated (W) Reset Priority level Level 3 Level 2 Level Level Priority level Level 3 Level 2 Level Level Interrupt disable Interrupt disable (R) No interrupt factor is generated (W) No operation (R) No interrupt factor is generated (W) No operation Comment Constantly "" when being read "" when being read "" when being read SC8F36 TECHNICAL MANUAL EPSON 43

156 5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status) D5 D4 D3 D2 D D FF2A D7 EAD D6 D5 D4 D3 D2 D D FF2C D7 FAD Table (b) Interrupt control bits Address Bit Name Function SR FF28 D7 PADC A/D converter interrupt priority register PADC PADC Priority Level 3 D6 PADC Level 2 D6 D5 D4 D3 D2 D D Reserved Reserved A/D converter interrupt enable register Reserved A/D converter interrupt factor flag Reserved R) W) Prohibited Prohibited Enable Generated Reset Level Level Disable Not generated No operation Comment Do not write "". Constantly "" when being read Constantly "" when being read Constantly "" when being read Refer to the explanations on the respective peripheral circuits for the setting content and control method for each bit Programming notes () When executing the RETE instruction without resetting the interrupt factor flag after an interrupt has been generated, the same interrupt will be generated. Consequently, the interrupt factor flag corresponding to that routine must be reset (writing "") in the interrupt processing routine. (2) Beware. If the interrupt flags (I and I) have been rewritten (set to lower priority) prior to resetting an interrupt factor flag after an interrupt has been generated, the same interrupt will be generated again. (3) An exception processing vector is fixed at 2 bytes, so it cannot specify a branch destination bank address. Consequently, to branch from multiple banks to a common exception processing routine, the front portion of an exception processing routine must be described within the common area (H7FFFH). (4) Do not execute the SLP instruction for 2 msec after a NMI interrupt has occurred (when fosc is khz). 44 EPSON SC8F36 TECHNICAL MANUAL

157 6 PROM PROGRAMMER AND OPERATING MODES 6 PROM PROGRAMMER AND OPERATING MODES The biggest difference between the SC8F36 and the SC88xxx is that the SC8F36 contains Flash EEPROM as the ROM that allows the user to write data to it using the exclusive PROM writer. The SC8F36 also has a built-in PROM programmer that controls writing data to the PROM. The following explains the PROM programmer and the operating modes that are added for the programming operation. 6. Configuration of PROM Programmer Figure 6.. shows the configuration of the PROM programmer. The PROM programmer supports Serial Programming for writing data received in serial transfer and parallel programming that uses a parallel transfer. The programming method will be described later. <Terminals> The PROM programmer uses the following input/ output terminals. The following sections will explain handling the terminals in each operating mode. SPRG: PROM serial programming mode setting terminal RXD: Serial data receive terminal TXD: Serial data transmit terminal SCLK: Serial clock input/output terminal CLKW: Serial programming source clock (3.72 MHz) input terminal The parallel programming mode uses other terminals in addition to the terminals above. However, it is not necessary to switch the lines on the board, because the IC is programed by directly installing it to the exclusive PROM writer. 6.2 Operating Modes Three operating modes are available in the SC8F36: one is for normal operation and the others are for programming. ) Normal operation mode 2) PROM serial programming mode 3) PROM parallel programming mode The operating mode is decided by the SPRG terminal setting at power on or initial reset Normal operation mode In this mode, the SC88 core CPU and the peripheral circuits operate by the programmed PROM. The CPU can enter this mode after the PROM programming has finished. Inspection data is written to the PROM at shipment. Therefore, the IC will not work even if the normal operation mode is set before programming. In the normal operation mode, set the terminals for the PROM programmer as below. The board must be designed so that the terminal settings cannot be changed. SPRG: Fix at a High level. RXD, CLKW: Open or fix at a High level. TXD, SCLK: Open. RXD TXD SCLK PROM programmer Serial transfer controller Sub-address bus Sub-data bus PROM From/to exclusive PROM writer Address signal Data signal Control signal Parallel transfer controller SPRG Programming control circuit CLKW Fig. 6.. Configuration of RROM programmer SC8F36 TECHNICAL MANUAL EPSON 45

158 6 PROM PROGRAMMER AND OPERATING MODES PROM serial programming mode The PROM serial programming mode should be set when writing data to the PROM using a serial transfer from the exclusive PROM writer. This mode will be used for the programming of the chip or package device mounted on the board, because the programming can be done even when the IC has already been mounted on the board. To create data to be written to the PROM, use the SC88 assembler similar to the SC88xxx. Refer to Appendix in this manual for the connection and operation of the PROM writer PROM parallel programming mode In the PROM parallel programming mode, the exclusive PROM writer transfers data in parallel to the IC installed on the PROM writer to write data to it. The terminal setting is done by the PROM writer. Thus there is no precaution on mode setting or board design. Refer to Appendix in this manual for the operation of the PROM writer. To create data to be written to the PROM, use the SC88 assembler the same as the SC88xxx. 46 EPSON SC8F36 TECHNICAL MANUAL

159 7 DIFFERENCES FROM SC883XX/SC888XX 7 DIFFERENCES FROM SC883XX/SC888XX This chapter explains the differences on functions between the SC8F36 and the SC883xx/888xx. 7. Terminal Configuration The SC8F36 has terminals for the PROM programmer in addition to those of the SC883xx/888xx and uses the QFP2-76pin or PFBGA-8pin package. Table 7.. shows the pad configuration and the terminal functions according to the operating mode. Table 7.. Terminal configuration VDD VSS VD VDF VOSC VCVC5 CACE Pin name OSC OSC2 OSC3 OSC4 MCU/MPU KK7 K/EVIN K/BREQ RR7/AA7 RR7/A8A5 R2R22/A6A8 R23/RD R24/WR R25/CL R26/FR R27/TOUT R3R33 /CECE3 R34/FOUT R35R37 R5/BZ R5/BACK PP7/DD7 P/SIN P/SOUT P2/SCLK P3/SRDY P4/CMPP/AD4 P5/CMPM/AD5 P6/CMPP/AD6 P7/CMPM/AD7 COMCOM5 COM6COM3 /SEG66SEG5 SEGSEG5 RESET TEST AVDD AVSS AVREF TXD RXD SCLK CLKW SPRG VEPEXT COMCOM5: QFP , 5 87, , Pin No. PFBGA-8 B6, C2 B4, H4 C3 G3 B3 D2, D3, D4, E, E E2, E3, E4, F, F A3 A2 D C4 B E9, D9, C9, B9, A9, D, C, B A C A4, B4, C4, D4, A3, B3, C3, A2 B2, B, C, C2, D, D2, D3, E E2, E3, E4 F F2 F3 F4 F5 G, G2, G3, G4 G5 H, H2, H3 H5 J D5, C5, B5, A5, E6, D6, C6 C7 B7 A7 E8 D8 C8 B8 A8 2 3 A B2 D7 E7 A6 F2 F4 F3 G G2 G I/O Normal operation mode Function I/O Power supply (+) Power supply (GND) Internal logic voltage regulator output Internal logic and Flash voltage regulator output Oscillation system voltage regulator output LCD drive voltage output I O I O I I I I O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O I I O I I I I I/O Booster capacitor for LCD OSC oscillation input OSC oscillation output OSC3 oscillation input OSC3 oscillation output MCU/MPU mode selection Input port Input port or EVIN input Input port or BREQ input Output port or address bus AA7 Output port or address bus A8A5 Output port or address bus A6A8 Output port or RD output Output port or WR output Output port or CL output Output port or FR output Output port or TOUT output Output port or CECE3 output Output port or FOUT output Output port Output port or BZ output Output port or bus BACK output I/O port or data bus DD7 I/O port or SIN input I/O port or SOUT output I/O port or SCLK input/output I/O port or SRDY output I/O port, CMPP or AD4 input I/O port, CMPM or AD5 input I/O port, CMPP or AD6 input I/O port, CMPM or AD7 input LCD common output terminals LCD common output (/32 duty) or LCD segment output (/6 duty) LCD segment output Initial reset input Test input Analog power supply (+) Analog power supply () Analog reference voltage Unused Unused (High) Unused Unused (High) Unused (High) N.C. Serial programming mode Function Power supply (+) Power supply (GND) Internal logic voltage regulator output Internal logic and Flash voltage regulator output Oscillation system voltage regulator output Unused SC8F36 TECHNICAL MANUAL EPSON 47 I O I O I I I I O O O O O O O O O O O O O I I I I I I I I I O O O I I O I I/O I I I/O Unused OSC oscillation input OSC oscillation output Unused Unused Unused (High or Low) Unused (High or Low) Unused (High or Low) Unused (High or Low) Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused (High or Low) Unused (High or Low) Unused (High or Low) Unused (High or Low) Unused (High or Low) Unused (High or Low) Unused (High or Low) Unused (High or Low) Unused (High or Low) Unused Unused Unused Initial reset input Unused (High) Unused Unused Unused Serial data output for Flash programming Serial data input for Flash programming Serial clock input/output for Flash programming Clock input for Flash programming Flash programming control input Flash test (high-voltage circuit monitor) J2, J3, J4, J5, K, K2, K3, K4, K5, L, L2, L3, L4, M, M2, M3 2 COM6/SEG66COM3/SEG5: G4, H, H, H2, H3, H4, J, J, J2, J3, J4, K, K2, K3, K4, L2 3 SEGSEG5: N, N2, P2, P3, N3, P4, N4, M4, P5, N5, M5, L5, P6, N6, M6, L6, K6, P7, N7, M7, L7, K7, P8, N8, M8, L8, K8, P9, N9, M9, L9, K9, P, N, M, L, K, P, N, M, L, P2, N2, M2, P3, N3, N4, M4, M3, L4, L3 In the parallel programming mode, all the terminals are set to the appropriate status by the exclusive PROM writer.

160 7 DIFFERENCES FROM SC883XX/SC888XX 7.2 Mask Option The following two option combinations are provided for the SC8F36. Table 7.2. Combination of mask options Mask option OSC oscillation circuit OSC3 oscillation circuit Multiple key entry reset SVD reset MPU initial bus mode Input port K pull-up resistor K K2 K3 K4 K5 K6 K7 K K RESET MCU/MPU I/O port P pull-up resistor P P2 P3 P4 P5 P6 P7 P P P2 P3 P4 P5 P6 P7 Output port R output R specification R2 R3 R4 R5 R6 R7 R R R2 R3 R4 R5 R6 R7 LCD drive duty LCD power supply R26 port function R5 port function Set SC8F36D4 * SC8F36F43 *2 For SC883xx/SC888xx Set 2 SC8F36D5 * SC8F36F532 *2 Crystal ( khz) Crystal ( khz) CR Crystal/ceramic Not used Not used Not used Not used Expanded 52K max. Expanded 52K max. With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Software selection Software selection Software selection Software selection R26/FR R26/FR R5 R5 : Product number for bare chip 2: Product number for QFP2-76pin package 48 EPSON SC8F36 TECHNICAL MANUAL

161 7 DIFFERENCES FROM SC883XX/SC888XX 7.3 Power Supply 7.3. Supply voltage range The supply voltage range is different. Table Supply voltage range Model Normal mode High-speed mode (VD = 2.2 V) (VD = 3. V) SC8F36 SC8837 SC88862 SC to 5.5 V 2.4 to 5.5 V 2.4 to 5.5 V 2.4 to 5.5 V 3.5 to 5.5 V 3.5 to 5.5 V 3.5 to 5.5 V 3.5 to 5.5 V Low-power mode (VD =.85 V) 2. to 3.5 V.8 to 3.5 V.8 to 3.5 V.8 to 3.5 V The SC8F36 operation is guaranteed within the above voltage range. Figure shows the configuration of the power supply circuit. External power supply VDD AVDD VD Internal logic system voltage regulator VDD VD Internal voltage setting circuit OSC3 oscillation circuit Internal circuit OSC3, OSC4 VDF Flash block VOSC Oscillation system voltage regulator VOSC OSC oscillation circuit OSC, OSC2 VC VC2 LCD system voltage regulator VC, VC2 VC3 VC4 VC5 CA CB CC CD CE LCD system voltage booster VC3VC5 LCD driver COMCOM5 COM6COM3/SEG66SEG5 SEGSEG5 AVSS A/D converter VSS Fig Configuration of the power supply circuit SC8F36 TECHNICAL MANUAL EPSON 49

162 7 DIFFERENCES FROM SC883XX/SC888XX LCD drive voltage (VCVC5) The LCD drive voltage range is different from that of the SC883xx/888xx. Furthermore, the LCD power supply type (TYPE A or TYPE B) can be selected by software in the SC8F36. Table LCD drive voltage range SC883xx/888xx SC8F36 LCD drive voltage Condition Min. Max. Min. Max. VC VC2 VC3 VC4 VC5 TYPE A (4.5V) VC5 TYPE B (5.5V) LCx = H LCx = H LCx = 2H LCx = 3H LCx = 4H LCx = 5H LCx = 6H LCx = 7H LCx = 8H LCx = 9H LCx = AH LCx = BH LCx = CH LCx = DH LCx = EH LCx = FH LCx = H LCx = H LCx = 2H LCx = 3H LCx = 4H LCx = 5H LCx = 6H LCx = 7H LCx = 8H LCx = 9H LCx = AH LCx = BH LCx = CH LCx = DH LCx = EH LCx = FH : When a MΩ load resistor is connected between VSS and VC 2: When a MΩ load resistor is connected between VSS and VC2 3: When a MΩ load resistor is connected between VSS and VC3 4: When a MΩ load resistor is connected between VSS and VC4 5: When a MΩ load resistor is connected between VSS and VC5.8 VC5.39 VC5.59 VC5.8 VC5 Typ..94 Typ VC5.43 VC5.63 VC5.84 VC5 Typ..6 Typ..6.8 VC5.39 VC5.57 VC5.78 VC5 Typ..94 Typ VC5.43 VC5.62 VC5.83 VC5 Typ..6 Typ..6 (Unit: V) 5 EPSON SC8F36 TECHNICAL MANUAL

163 7.4 Initial Reset When turning the SC8F36 power on, the RESET terminal must be maintained at a Low (VSS) level until the supply voltage goes to 2.4 V or more. VDD RESET Power ON 2.4 V.VDD tpsr.5vdd Fig Initial reset at power-on The SC8F36 uses initial reset as a trigger for setting either the normal operation mode or the programming mode. Therefore, design the reset circuit so that the IC will be reset for sure. When resetting the IC in the normal operation mode, make sure to fix the SPRG terminal at a High level. 7.5 ROM The SC8F36 has employed a Flash EEPROM for the internal ROM. The ROM has a capacity of 6,44 steps 8 bits and is allocated to H EFFFH. The Flash EEPROM can be rewritten up to, times. Rewriting data is done at the user s own risk. 7.6 RAM The built-in RAM has a capacity of 2,48 words 8 bits and is allocated to FHF7FFH. 7 DIFFERENCES FROM SC883XX/SC888XX 7.7 Oscillation Circuit In the SC8F36, a crystal oscillator can only be used for the OSC oscillation circuit and a crystal or ceramic oscillator for the OSC3 oscillation circuit. Furthermore, pay attention to the difference on the oscillation start time according to the supply voltage. Be sure there is enough margin especially for stabilizing the OSC3 oscillation when controlling the peripheral circuit that uses the OSC3 clock. 7.8 LCD Controller In the SC8F36, the LCD power supply type (TYPE A or TYPE B) and LCD drive duty (/8 or / 6 & /32), that are selected by mask option in the SC88xxx, can be selected by software. Address FF9H is added to the I/O map for this selection. 7.9 A/D Converter The SC8F36 has a built-in A/D converter that is not supported by the SC88xxx. However, the A/D converter cannot be used with the analog comparator simultaneously. 7. SVD Circuit Table 7.8. Additional LCD control registers The SC8F36 has a built-in SVD (Supply Voltage Detection) circuit. The mask option for resetting when low voltage is detected (available in the SC88xxx) is not provided in the SC8F36. Therefore, the function cannot be used with the SC8F36. Address Bit Name Function SR Comment FF9 D7 D6 Constantly "" when D5 being read D4 D3 D2 LCDB D LCDAJ D DUTY8 Reserved Power TYPE A (4.5V)/B (5.5V) switch LCD drive duty switch TYPE A /8 duty TYPE B /6, /32 * * Writing "" to DUTY8 (FF9 D) disables /6 and /32 duty selection using LDUTY (FF D). Detection level Level Level Level 2 Level Level 3 Level 2 Level 4 Level 3 Level 5 Level 4 Level 6 Level 5 Level 7 Level 6 Level 8 Level 7 Level 9 Level 8 Level Level 9 Level Level Level 2 Level Level 3 Level 2 Level 4 Level 3 Level 5 Level 4 Table 7.. Supply voltage detection level Min. Typ..92 Typ..88 SC883xx/888xx Typ Max. Typ..8 Typ..2 Min. Typ..92 SC8F36 Typ Max. Typ..8 SC8F36 TECHNICAL MANUAL EPSON 5

164 7 DIFFERENCES FROM SC883XX/SC888XX 7. List of Differences between SC8F36 and Supported Models SC8837 SC88862 SC88832 SC8F36 Package QFP2-76pin QFP8-6pin QFP5-28pi PFBGA-8pin PFBGA-44pin VFBGA-2pin ROM size RAM size Input port Output port I/O port 6KB 2KB KB.5KB KB 5 6KB 2KB 34 6 Chip mode Single chip Extended 64K MCU MPU Extended MCU 52K min. MPU Extended MCU 52K max. MPU Operating Normal (VD = 2.2V) mode High-speed (VD = 3.V) Low-power (VD =.85V) Mask ROM OSC Crystal option select External CR Crystal (with CG) OSC3 Crystal Ceramic CR External I/O (P) port With resistor pull-up Gate direct Input (K) port With resistor pull-up Gate direct Output (R) port Complementary output spec. Nch open drain LCD duty /32 & /6 /8 2 2 LCD power TYPE A (4.5V) TYPE B (5.5V) 2 2 External power source Reset K port combination SVD reset Operating voltage Normal High-speed Low-power 2.4 to 5.5V 3.5 to 5.5V.8 to 3.5V 2. to 3.5V Operating OSC Normal 3k to 5kHz 3k to 8kHz 3k to 5kHz frequency High-speed Low-power 3k to 5kHz 3k to 5kHz 3k to 8kHz 3k to 8kHz 3k to 5kHz 3k to 5kHz OSC3 Normal High-speed 3k to 4.2MHz 3k to 8.2MHz Operating temperature -4 to 85 C -2 to 7 C Power CPU VD supply Peripheral Port OSC PROM VD VDD VD VOSC VD/VDD SVD 6 levels Analog comparator A/D converter R26 output port specification R5 output port specification 2 ch. R26/FR R5/BACK R26/TOUT R5/BZ R26/TOUT R5/BZ 2 ch. 4 ch., bits R26/FR/TOUT R5/BACK/BZ = Available, = Not available : The P4 to P7 ports (usable as analog inputs) have no pull-up resistor. 2: Selectable with software Notes: The pin assignment of the SC8F36 is incompatible with the SC883xx and SC888xx. The table does not contain some different items. Refer to this manual and Technical Manual of the SC88xxx. 52 EPSON SC8F36 TECHNICAL MANUAL

165 8 SUMMARY OF NOTES 8 SUMMARY OF NOTES 8. Notes Related to the PROM () Be sure to erase the PROM before writing data. (2) The PROM data can be rewritten up to, times. (Count up when an erasing and writing is performed.) (3) The circuit board should be designed so that the terminals can switch the input signals that differ between the PROM serial programming mode and the normal operation mode. (4) The terminals for the PROM programmer should be set correctly according to the operating mode and fixed so that they cannot be changed during operation. Especially the SPRG terminal must be fixed at a Low level in the programming mode, while they must be fixed at a High level in the normal operation mode. Changing the voltage level may damage the IC. (5) If the operation of the SC8F36 is unstable even though the writing and verification of the PROM data was completed normally, write and verify the PROM data without erasing the PROM. (6) Rewriting the PROM is done at on the user's own risk. 8.2 Notes on Differences form the SC883xx/SC888xx Be aware of the following notes when using the SC8F36 as a development tool for the SC883xx/ SC888xx. Memory map The SC8F36 has a built-in ROM and RAM larger than most of all the SC883xx and SC888xx. When using the SC8F36 as a development tool of for the SC883xx/SC888xx, pay attention to the memory size. Initial reset Note that the power-on reset time differs from the SC883xx/SC888xx because the power supply is different. Oscillation circuit In the SC8F36, a crystal oscillator can only be used for the OSC oscillation circuit and a crystal or ceramic oscillator for the OSC3 oscillation circuit. Furthermore, pay attention to the difference on the oscillation start time according to the supply voltage. Be sure there is enough margin especially for stabilizing the OSC3 oscillation when controlling the peripheral circuit that uses the OSC3 clock. LCD driver The LCD drive voltage range of the SC8F36 is different from that of the SC883xx/SC888xx. Check the electrical characteristic differences by referring to this manual and the Technical Manual for the SC883xx/SC888xx before designing the LCD unit. Furthermore, the LCD drive duty and built-in LCD power supply type options of the SC883xx/SC888xx are changed to software selectable functions. Mask option In the SC8F36, the specifications selected by the SC883xx/SC888xx mask options are fixed and cannot be selected. Therefore, some optional functions cannot be used in the SC8F36. Check whether the functions are enabled or not in this manual and the Technical Manual for the SC883xx/SC888xx. Other The A/D converter and the analog comparator cannot be used simultaneously. Refer to "Programming notes" in each peripheral section for precautions of each peripheral circuit. Power supply The SC8F36 is operable with a supply voltage within the range of 2. V to 5.5 V. Note, however, that the electrical characteristics are different from those of the SC883xx/SC888xx. Refer to Chapter, "ELECTRICAL CHARACTERISTICS". SC8F36 TECHNICAL MANUAL EPSON 53

166 8 SUMMARY OF NOTES 8.3 Notes for Low Current Consumption The SC8F36 can turn circuits, which consume a large amount of power, ON or OFF by control registers. You can reduce power consumption by creating a program that operates the minimum necessary circuits using these control registers. Next, which circuit systems' operation can be controlled and their control registers (instructions) are explained. You should refer to these when programming. See Chapter, "ELECTRICAL CHARACTERIS- TICS" for the current consumption. Circuit type CPU Oscillation circuit Operating mode LCD controller SVD circuit Analog comparator A/D converter Table 8.3. Circuit systems and control registers Control register (Instruction) Status at time of initial resetting HALT and SLP instructions CLKCHG, OSCC VDC, VDC LCDC, LCDC SVDON, SVDSP CMPON, CMPON PRAD, ADRUN Operation status OSC clock (CLKCHG = "") OSC3 oscillation OFF (OSCC = "") Normal mode (VDC = VDC = "") Drive OFF (LCDC = LCDC = "") OFF status (SVDON = SVDSP = "") OFF status (CMPON = CMPON = "") OFF status (PRAD = ADRUN = "") 54 EPSON SC8F36 TECHNICAL MANUAL

167 8 SUMMARY OF NOTES 8.4 Precautions on Mounting <Oscillation Circuit> Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when a ceramic or crystal oscillator is used, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following points to prevent this: () Components which are connected to the OSC, OSC2, OSC3 and OSC4 terminals, such as oscillators, resistors and capacitors, should be connected in the shortest line. (2) As shown in the right hand figure, make a VSS pattern as large as possible at circumscription of the OSC, OSC2, OSC3 and OSC4 terminals and the components connected to these terminals. Furthermore, do not use this VSS pattern for any purpose other than the oscillation system. Sample VSS pattern (OSC3) OSC4 <Reset Circuit> The power-on reset signal which is input to the RESET terminal changes depending on conditions (power rise time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the RESET terminal in the shortest line. <Power Supply Circuit> Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: () The power supply should be connected to the VDD, VSS, AVDD, AVSS and AVREF terminal with patterns as short and large as possible. In particular, the power supply for AVDD, AVSS and AVREF affects A/D conversion precision. (2) When connecting between the VDD and VSS terminals with a bypass capacitor, the terminals should be connected as short as possible. Bypass capacitor connection example OSC3 VDD VDD VSS VSS VSS In order to prevent unstable operation of the oscillation circuit due to current leak between OSC/OSC3 and VDD, please keep enough distance between OSC/OSC3 and VDD or other signals on the board pattern. (3) Components which are connected to the VD, VCVC5 terminals, such as capacitors and resistors, should be connected in the shortest line. In particular, the VCVC5 voltages affect the display quality. <A/D Converter> When the A/D converter is not used, the power supply terminals for the analog system should be connected as shown below. AVDD VDD AVSS VSS AVREF VSS SC8F36 TECHNICAL MANUAL EPSON 55

168 8 SUMMARY OF NOTES <Arrangement of Signal Lines> In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit and analog input unit. When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction. Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit and analog input unit. Prohibited pattern Large current signal line High-speed signal line P4 (AD4) Large current signal line High-speed signal line OSC4 OSC3 VSS <Output Terminals> When an output terminal is used to drive an external component that consumes a large amount of current, the operation of the external component affects the built-in power supply circuit of this IC and the output voltage may vary. When driving a bipolar transistor by a periodic signal such as the BZ or timer output in particular, it may cause variations in the voltage output from the LCD system voltage circuit that affects the contrast of the LCD display. To prevent this, separate the traces on the printed circuit board. Put one between the power supply and the IC's VDD and VSS terminals, and another between the power supply and the external component that consumes the large amount of current. Furthermore, use an external component with as low a current consumption as possible. <Precautions for Visible Radiation (when bare chip is mounted)> Visible radiation causes semiconductor devices to change electrical characteristics. It may cause the IC to malfunction or the nonvolatile memory data to be erased. When developing products, consider the following precautions to prevent malfunctions caused by visible radiation. () Design the product and bond the IC on the board so that it is shielded from visible radiation in actual use. (2) The inspection process of the product needs an environment that shields the IC from visible radiation. (3) Shield not only the face of the IC but the back and side as well. (4) After the shielded package has been opened, the IC chip should be bonded on the board within one week. If the IC chip must be stored after the package has been opened, be sure to shield the IC from visible radiation. (5) If there is a possibility that heat stress exceeding the reflow soldering condition is applied to the IC in the bonding process, perform enough evaluation of data stored in the nonvolatile memory before the product is shipped. Example: Buzzer output circuit BZ VDD VSS + CP Piezo 56 EPSON SC8F36 TECHNICAL MANUAL

169 9 BASIC EXTERNAL WIRING DIAGRAM 9 BASIC EXTERNAL WIRING DIAGRAM Normal operation mode LCD panel 5 x 32 VDD AVDD AVREF MCU/MPU TEST SPRG SEG SEG5 COM COM3 Open VDF + - CP Open CLKW Open SCLK Open TXD Open RXD Cres RESET AVSS KK7 K, K Input CG CG2 C X'tal X'tal2 CD2 Rf VSS VOSC OSC OSC2 OSC3 OSC4 SC8F36 [The potential of the substrate (back of the chip) is VSS.] PP7 PP7 RR7 RR7 R2R27 R3R37 R5, R5 I/O Output C VD R C2 VC C3 VC2 C4 VC3 C5 VC4 C6 VC5 CA C7 CB C8 CC CD C9 CE Recommended values for external parts Symbol X'tal X'tal2 Rf CG CG2 CD2 Name Crystal oscillator Crystal oscillator Feedback resistor Trimmer capacitor Gate capacitor Drain capacitor Recommended value khz, CI (Max.) = 35 kω MHz MΩ 525 pf 53 pf 53 pf C Capacitor between VSS and VD. µf C2 Capacitor between VSS and VC. µf Symbol C3 C4 C5 C6 C7C9 C CP Cres Name Capacitor between VSS and VC2 Capacitor between VSS and VC3 Capacitor between VSS and VC4 Capacitor between VSS and VC5 Booster capacitors Capacitor between VSS and VOSC Capacitor for power supply Capacitor for RESET terminal Recommended value. µf. µf. µf. µf. µf. µf 3.3 µf.47 µf R Load resistor between VSS and VC 5 kω Note: The above table is simply an example, and is not guaranteed to work. SC8F36 TECHNICAL MANUAL EPSON 57

170 9 BASIC EXTERNAL WIRING DIAGRAM Serial programming mode LCD panel 5 x 32 Exclusive cable VDDF 2 VDD 3 CLK 4 VSS + - CP VDF VDD CLKW MCU/MPU TEST SEG SEG5 COM COM3 5 SCLK 6 VSS SCLK 7 RXD 8 VSS RXD AVDD 9 TXD VSS TXD AVREF RESET 2 VSS 3 SPRG 4 VSS 5 Reserved 6 SRDY The wiring for the programming terminals is changed according to the PROM writer to be used. Refer to Appendix A for details. C CG X'tal CG2 X'tal2 CD2 Cres Rf RESET SPRG VSS VOSC OSC OSC2 OSC3 OSC4 SC8F36 [The potential of the substrate (back of the chip) is VSS.] KK7 K, K PP7 PP7 RR7 RR7 R2R27 R3R37 R5, R5 Input I/O Output C VD R C2 VC C3 VC2 C4 VC3 C5 VC4 C6 VC5 CA C7 CB C8 CC CD C9 CE Recommended values for external parts Symbol X'tal X'tal2 Rf CG CG2 CD2 Name Crystal oscillator Crystal oscillator Feedback resistor Trimmer capacitor Gate capacitor Drain capacitor Recommended value khz, CI (Max.) = 35 kω MHz MΩ 525 pf 53 pf 53 pf C Capacitor between VSS and VD. µf C2 Capacitor between VSS and VC. µf Symbol C3 C4 C5 C6 C7C9 C CP Cres Name Capacitor between VSS and VC2 Capacitor between VSS and VC3 Capacitor between VSS and VC4 Capacitor between VSS and VC5 Booster capacitors Capacitor between VSS and VOSC Capacitor for power supply Capacitor for RESET terminal Recommended value. µf. µf. µf. µf. µf. µf 3.3 µf.47 µf R Load resistor between VSS and VC 5 kω Note: The above table is simply an example, and is not guaranteed to work. 58 EPSON SC8F36 TECHNICAL MANUAL

171 ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS Note: The electrical characteristics of the SC8F36 are different from those of the SC883xx/SC888xx. The following characteristics should be used as reference values when using the SC8F36 as a development tool.. Absolute Maximum Rating (VSS = V) Item Symbol Condition Rated value Unit Note Power voltage Liquid crystal power voltage Input voltage Output voltage High level output current Low level output current VDD VC5 VI VO IOH IOL terminal Total of all terminals terminal Total of all terminals -.3 to to to VDD to VDD V V V V ma ma ma ma Permitted loss Operating temperature Storage temperature PD Topr Tstg 2-2 to to +5 mw C C 2 Flash EEPROM write/erase temperature Twe +5 to +4 C Note) 2 In case of plastic package. This rated value cannot unsure the PROM data holding function..2 Recommended Operating Conditions Item Symbol Condition Min. Typ. Max. Unit Operating power voltage (Normal mode) Operating power voltage (High speed mode) Operating power voltage (Low power mode) Operating frequency (Normal mode) VDD = 2.4 to 5.5 V Operating frequency (High speed mode) VDD = 3.5 to 5.5 V Liquid crystal power voltage Capacitor between VD and VSS Capacitor between VC and VSS Capacitor between VC2 and VSS Capacitor between VC3 and VSS Capacitor between VC4 and VSS Capacitor between VC5 and VSS Capacitor between CA and CB Capacitor between CA and CC Capacitor between CD and CE Capacitor between VOSC and VSS Resistor between VC and VSS VDD VDD VDD fosc fosc3 fosc fosc3 VC5 C C2 C3 C4 C5 C6 C7 C8 C9 C R Crystal oscillation Crystal/ceramic oscillation CR oscillation Crystal oscillation Crystal/ceramic oscillation CR oscillation * 3 7. V V V khz MHz MHz khz MHz MHz V µf µf µf µf µf µf µf µf µf µf kω Note) When LCD drive power is not used, the capacitor is not necessary. In this case, do not connect anything to VC to VC5 and CA to CE terminals. 2 It is necessary when the panel load is large and for /32 duty driving. The resistance value should be decided by connecting it to the actual panel to be used. 3 The value with * may change without notice. It will affect the related characteristics. Note 3 2 SC8F36 TECHNICAL MANUAL EPSON 59

172 ELECTRICAL CHARACTERISTICS.3 DC Characteristics Unless otherwise specified: VDD = 2. to 5.5 V, VSS = V, Ta = 25 C Item Symbol Condition Min. Typ. Max. Unit High level input voltage Low level input voltage High level schmitt input voltage Low level schmitt input voltage High level output current Low level output current Input leak current Output leak current Input pull-up resistance Input terminal capacitance Segment/Common output current VIH VIL VT+ VT- IOH IOL ILI ILO RIN CIN ISEGH ISEGL Kxx, Pxx, SPRG, RXD, SCLK, CLKW, MCU/MPU Kxx, Pxx, SPRG, RXD, SCLK, CLKW, MCU/MPU RESET RESET Pxx, Rxx, TXD, VOH =.9 VDD Pxx, Rxx, TXD, VOL =. VDD Kxx, Pxx, SPRG, RXD, SCLK, CLKW, RESET, MCU/MPU Pxx, Rxx, TXD Kxx, Pxx, SPRG, RXD, SCLK, CLKW, RESET, MCU/MPU Kxx, Pxx, SPRG, RXD, SCLK, CLKW SEGxx, COMxx, VSEGH = VC5-. V SEGxx, COMxx, VSEGL =. V.8VDD.5VDD.VDD VDD.2VDD.9VDD.5VDD V V V V ma ma µa µa kω pf µa µa Note VDD VOUT (V) VT- VT+ VDD VIN (V) 6 EPSON SC8F36 TECHNICAL MANUAL

173 ELECTRICAL CHARACTERISTICS.4 Analog Circuit Characteristics LCD drive circuit Unless otherwise specified: VDD = 2. to 5.5 V, VSS = V, Ta = 25 C, CC =. µf Item Symbol Condition Min. Typ. Max. Unit LCD drive voltage VC VC2 VC3 VC4 * *2 *3 *4.8VC5.39VC5.57VC5.78VC5.22VC5.43VC5.62VC5.83VC5 V V V V VC5 TYPE A (4.5V) *5 LCx = H LCx = H LCx = 2H LCx = 3H LCx = 4H LCx = 5H LCx = 6H V V V V V V V LCx = 7H LCx = 8H LCx = 9H LCx = AH LCx = BH LCx = CH LCx = DH LCx = EH LCx = FH Typ Typ.6 V V V V V V V V V VC5 TYPE B (5.5V) *5 LCx = H LCx = H LCx = 2H LCx = 3H LCx = 4H LCx = 5H LCx = 6H V V V V V V V LCx = 7H LCx = 8H LCx = 9H LCx = AH LCx = BH LCx = CH LCx = DH LCx = EH LCx = FH Typ Typ.6 V V V V V V V V V * Connects MΩ load resistor between VSS and VC. (without panel load) *2 Connects MΩ load resistor between VSS and VC2. (without panel load) *3 Connects MΩ load resistor between VSS and VC3. (without panel load) *4 Connects MΩ load resistor between VSS and VC4. (without panel load) *5 Connects MΩ load resistor between VSS and VC5. (without panel load) Note Note: The LCD drive voltage levels of the SC8F36 are not exactly the same as those of the SC883xx/ SC888xx due to circuit characteristic differences. SC8F36 TECHNICAL MANUAL EPSON 6

174 ELECTRICAL CHARACTERISTICS SVD circuit Unless otherwise specified: VDD = 2. to 5.5 V, VSS = V, Ta = 25 C Item Symbol Condition Min. Typ. Max. Unit Note SVD voltage VSVD Level Level Level 2 Level Level 3 Level 2 Level 4 Level 3 Level 5 Level 4 Level 6 Level V V V V V V 2 2 Level 7 Level V 2 Typ.92 Typ.8 Level 8 Level 7 3. V 2 Level 9 Level 8 Level Level 9 Level Level Level 2 Level Level 3 Level 2 Level 4 Level 3 Level 5 Level V V V V V V V VSVD (Level ) < VSVD (Level ) < VSVD (Level 2) < VSVD (Level 3) < VSVD (Level 4) < VSVD (Level 5) < VSVD (Level 6) < VSVD (Level 7) < VSVD (Level 8) < VSVD (Level 9) < VSVD (Level ) < VSVD (Level ) < VSVD (Level 2) < VSVD (Level 3) < VSVD (Level 4) < VSVD (Level 5) Note) 2 3 Note: Low power operating mode only Low power operating mode or Normal operating mode Normal operating mode or High speed operating mode The SVD voltage levels of the SC8F36 differ from those of the SC883xx/SC888xx. Analog comparator circuit Unless otherwise specified: VDD = 2.4 to 5.5 V, VSS = V, Ta = 25 C Item Symbol Condition Min. Typ. Max. Unit Analog comparator operating voltage input range Analog comparator offset voltage Analog comparator stability time Analog comparator response time VCMIP VCMIM VCMOF tcmp tcmp2 Non-inverted input (CMPP) Inverted input (CMPM) VCMIP =.9 V to VDD -.9 V VCMIM =.9 V to VDD -.9 V VCMIP =.9 V to VDD -.9 V VCMIM =.9 V to VDD -.9 V VCMIP = VCMIM ±.25 V.9.9 VDD -.9 VDD V V mv ms ms Note) 2 Stability time is the time from turning the circuit ON until the circuit is stabilized. Response time is the time that the output result responds to the input signal. Note 2 62 EPSON SC8F36 TECHNICAL MANUAL

175 ELECTRICAL CHARACTERISTICS A/D converter circuit Unless otherwise specified: VDD = AVDD = AVREF = 5. V, VSS = AVSS = V, fosc = khz, fosc3 = 4. MHz, Ta = 25 C Item Symbol Condition Min. Typ. Max. Unit Note Zero-scale error Full-scale error Non-linearity error Total error Ezs Efs El Et VDD = AVDD = AVREF = 2.4 to 5.5 V, ADCLK = MHz, Ta = 25 C LSB LSB LSB LSB A/D converter current consumption IAD VDD = AVDD = AVREF = 3. V, ADCLK = MHz, Ta = 25 C AVREF and ADCLK divider current not included VDD = AVDD = AVREF = 5. V, ADCLK = MHz, Ta = 25 C AVREF and ADCLK divider current not included ma ma A/D conversion clock f VDD = AVDD = AVREF = 2.4 to 5.5 V, Ta = 25 C.3 MHz Zero-scale error: Full-scale error: Non-linearity error: Total error: Ezs = deviation from the ideal value at zero point Efs = deviation from the ideal value at the full scale point El = deviation of the real conversion curve from the end point line Et = max (Ezs, Efs, Eabs), Eabs = deviation from the ideal line (including quantization error) Note) See Table in "5.5 A/D Converter" for setting the A/D conversion clock. Flash EEPROM write/erase characteristics Unless otherwise specified: VDD = AVDD = AVREF = 5. V, VSS = AVSS = V, fosc = khz, fosc3 = 4. MHz, Ta = 25 C Item Symbol Condition Min. Typ. Max. Unit Note Write/erase temperature range Write/erase voltage range Twe Vwe C V Write current Erase current Number of program cycles Ifw Ife Ncyc 2 2 ma ma Times The SC8F36 has a built-in high-voltage generator. SC8F36 TECHNICAL MANUAL EPSON 63

176 ELECTRICAL CHARACTERISTICS.5 Power Current Consumption Unless otherwise specified: VDD = Within the operating voltage in each operating mode, VSS = V, Ta = 25 C, OSC = khz crystal oscillation, CG = 25 pf, Non heavy load protection mode, CC =. µf, No panel load Item Symbol Condition Min. Typ. Max. Unit Power current (Normal mode) Power current (High speed mode) Power current (Low power mode) LCD drive circuit current SVD circuit current Analog comparator circuit current IDD IDD2 IDD3 IDD4 IHVL IDD IDD2 IDD3 IDD4 IHVL IDD IDD2 IDD3 IHVL ILCDN ILCDH ISVDN ISVDH ICMP ICMP2 In SLEEP status In HALT status CPU is in operating (VDD = 5.5 V, khz) CPU is in operating (VDD = 5.5 V, MHz) In heavy load protection mode In SLEEP status In HALT status CPU is in operating (VDD = 5.5 V, khz) CPU is in operating (VDD = 5.5 V, MHz) In heavy load protection mode In SLEEP status In HALT status CPU is in operating (VDD = 3.5 V, khz) In heavy load protection mode VDD = 5.5 V In heavy load protection mode VDD = 5.5 V In heavy load protection mode CMPXDT = "" CMPXDT = "" * *2 *3 *4 * *2 *3 *4 * *2 * µa µa µa ma µa µa µa µa ma µa µa µa µa µa µa µa µa µa µa µa Note) * OSC: Stop, OSC3: Stop, CPU, ROM, RAM: SLEEP status, Clock timer: Stop, Others: Stop status *2 OSC: Oscillating, OSC3: Stop, CPU, ROM, RAM: HALT status, Clock timer: Operating, Others: Stop status *3 OSC: Oscillating, OSC3: Stop, CPU, ROM, RAM: Operating in khz, Clock timer: Operating, Others: Stop status *4 OSC: Oscillating, OSC3: Oscillating, CPU, ROM, RAM: Operating in MHz, Clock timer: Operating, Others: Stop status It is the value of current which flows in the heavy load protection circuit when in the heavy load protection mode (OSC3 ON or buzzer ON). 2 # The value in x V can be found by the following expression: ISVDN (VDD = x V) = (x 6) - 5 (Max. value) In the SC8F36, CR option cannot be selected for the OSC oscillation circuit. Note 2 64 EPSON SC8F36 TECHNICAL MANUAL

177 ELECTRICAL CHARACTERISTICS.6 AC Characteristics External memory access Read cycle (Normal operating mode) Condition: VDD = 2.4 to 5.5 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VIH2 =.6 V, VIL2 =.6 V, VOH =.8VDD, VOL =.2VDD, CL = pf (load capacitance) Item Symbol Min. Typ. Max. Unit Address set-up time in read cycle Address hold time in read cycle Read signal pulse width Data input set-up time in read cycle Data input hold time in read cycle tras trah trp trds trdh tc+tl-+n tc/2 th-8 tc-2+n tc/2 3 ns ns ns ns ns Note) 2 Substitute the number of states for wait insertion in n. Insert a wait cycle if the connected device does not satisfy the trds condition. (See Section 3.6.5, "WAIT control".) Read cycle (High speed operating mode) Condition: VDD = 3.5 to 5.5 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VIH2 = 2.4 V, VIL2 =.9 V, VOH =.8VDD, VOL =.2VDD, CL = pf (load capacitance) Item Symbol Min. Typ. Max. Unit Address set-up time in read cycle Address hold time in read cycle Read signal pulse width Data input set-up time in read cycle Data input hold time in read cycle tras trah trp trds trdh tc+tl-5+n tc/2 th-4 tc-+n tc/2 5 ns ns ns ns ns Note) Substitute the number of states for wait insertion in n. 2 Insert a wait cycle if the connected device does not satisfy the trds condition. (See Section 3.6.5, "WAIT control".) Read cycle (Low power operating mode) Condition: VDD = 2. to 3.5 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VIH2 =. V, VIL2 =.3 V, VOH =.8VDD, VOL =.2VDD, CL = pf (load capacitance) Item Symbol Min. Typ. Max. Unit Address set-up time in read cycle Address hold time in read cycle Read signal pulse width Data input set-up time in read cycle Data input hold time in read cycle tras trah trp trds trdh 5 5 µs µs µs µs µs Write cycle (Normal operating mode) Condition: VDD = 2.4 to 5.5 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VIH2 =.6 V, VIL2 =.6 V, VOH =.8VDD, VOL =.2VDD, CL = pf (load capacitance) Item Symbol Min. Typ. Max. Unit Address set-up time in write cycle Address hold time in write cycle Write signal pulse width Data output set-up time in write cycle Data output hold time in write cycle twas twah twp twds twdh tc-8 th-8 tl-4+n tc/2 tc-8+n tc/2 th-8 th+8 ns ns ns ns ns Note) Substitute the number of states for wait insertion in n. Write cycle (High speed operating mode) Condition: VDD = 3.5 to 5.5 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VIH2 = 2.4 V, VIL2 =.9 V, VOH =.8VDD, VOL =.2VDD, CL = pf (load capacitance) Item Symbol Min. Typ. Max. Unit Address set-up time in write cycle Address hold time in write cycle Write signal pulse width Data output set-up time in write cycle Data output hold time in write cycle twas twah twp twds twdh tc-9 th-4 tl-2+n tc/2 tc-9+n tc/2 th-4 th+4 ns ns ns ns ns Note) Substitute the number of states for wait insertion in n. Note 2 Note 2 Note Note Note SC8F36 TECHNICAL MANUAL EPSON 65

178 ELECTRICAL CHARACTERISTICS Write cycle (Low power operating mode) Condition: VDD = 2. to 3.5 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VIH2 =. V, VIL2 =.3 V, VOH =.8VDD, VOL =.2VDD, CL = pf (load capacitance) Item Symbol Min. Typ. Max. Unit Address set-up time in write cycle Address hold time in write cycle Write signal pulse width Data output set-up time in write cycle Data output hold time in write cycle twas twah twp twds twdh µs µs µs µs µs Note tc* ICLK VIH2 VIL2 th* tl* AA8 CE VOH VOL RD VOH VOL tras trah DIN trp VIH VIL trds trdh AA8 CE VOH VOL WR DOUT twas VIH VIL VOH VOL twp twds twah twdh * In the case of crystal oscillation and ceramic oscillation: th =.5tc ±.5tc, tl = tc - th (/tc: oscillation frequency) * In the case of CR oscillation: th =.5tc ±.tc, tl = tc - th (/tc: oscillation frequency) 66 EPSON SC8F36 TECHNICAL MANUAL

179 ELECTRICAL CHARACTERISTICS Serial interface Clock synchronous master mode (Normal operating mode) Condition: VDD = 2.4 to 5.5 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VOH =.8VDD, VOL =.2VDD Item Symbol Min. Typ. Max. Unit Transmitting data output delay time Receiving data input set-up time Receiving data input hold time tsmd tsms tsmh ns ns ns Note Clock synchronous master mode (High speed operating mode) Condition: VDD = 3.5 to 5.5 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VOH =.8VDD, VOL =.2VDD Item Symbol Min. Typ. Max. Unit Transmitting data output delay time Receiving data input set-up time Receiving data input hold time tsmd tsms tsmh 25 ns ns ns Note Clock synchronous master mode (Low power operating mode) Condition: VDD = 2. to 3.5 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VOH =.8VDD, VOL =.2VDD Item Symbol Min. Typ. Max. Unit Transmitting data output delay time Receiving data input set-up time Receiving data input hold time tsmd tsms tsmh 5 µs µs µs Note Clock synchronous slave mode (Normal operating mode) Condition: VDD = 2.4 to 5.5 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VOH =.8VDD, VOL =.2VDD Item Symbol Min. Typ. Max. Unit Transmitting data output delay time Receiving data input set-up time Receiving data input hold time tssd tsss tssh ns ns ns Note Clock synchronous slave mode (High speed operating mode) Condition: VDD = 3.5 to 5.5 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VOH =.8VDD, VOL =.2VDD Item Symbol Min. Typ. Max. Unit Transmitting data output delay time Receiving data input set-up time Receiving data input hold time tssd tsss tssh 25 ns ns ns Note Clock synchronous slave mode (Low power operating mode) Condition: VDD = 2. to 3.5 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VOH =.8VDD, VOL =.2VDD Item Symbol Min. Typ. Max. Unit Transmitting data output delay time Receiving data input set-up time Receiving data input hold time tssd tsss tssh 5 5 µs µs µs Note SC8F36 TECHNICAL MANUAL EPSON 67

180 ELECTRICAL CHARACTERISTICS Asynchronous system (All operating mode) Condition: VDD = 2. to 5.5 V, VSS = V, Ta = 25 C Item Symbol Min. Typ. Max. Unit Note Start bit detection error time Erroneous start bit detection range time tsa tsa2 9t/6 t/6 t/6 s s 2 Note) 2 Start bit detection error time is a logical delay time from inputting the start bit until internal sampling begins operating. (Time as far as AC is excluded.) Erroneous start bit detection range time is a logical range to detect whether a LOW level (start bit) has been input again after a start bit has been detected and the internal sampling clock has started. When a HIGH level is detected, the start bit detection circuit is reset and goes into a wait status until the next start bit. (Time as far as AC is excluded.) SCLK OUT VOL VOH SOUT tsmd VOH VOL SIN VIH VIL tsms tsmh SCLK IN VIL VIH SOUT VOH VOL tssd SIN VIH VIL tsss tssh Start bit Stop bit SIN Sampling clock tsa Erroneous start bit detection signal tsa2 t 68 EPSON SC8F36 TECHNICAL MANUAL

181 ELECTRICAL CHARACTERISTICS Input clock SCLK, EVIN input clock (Normal operating mode) Condition: VDD = 2.4 to 5.5 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD Item Symbol Min. Typ. Max. Unit SCLK input clock time EVIN input clock time (With noise rejector) EVIN input clock time (Without noise rejector) Cycle time "H" pulse width "L" pulse width Cycle time "H" pulse width "L" pulse width Cycle time "H" pulse width "L" pulse width tsccy tsch tscl tevcy tevh tevl tevcy tevh tevl / fosc 32 / fosc 32 / fosc µs µs µs s s s µs µs µs Input clock rising time Input clock falling time tckr tckf ns ns Note SCLK, EVIN input clock (High speed operating mode) Condition: VDD = 3.5 to 5.5 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD Item Symbol Min. Typ. Max. Unit SCLK input clock time Cycle time "H" pulse width "L" pulse width tsccy tsch tscl 2 µs µs µs EVIN input clock time Cycle time tevcy 64 / fosc s (With noise rejector) "H" pulse width tevh 32 / fosc s EVIN input clock time (Without noise rejector) "L" pulse width Cycle time "H" pulse width "L" pulse width tevl tevcy tevh tevl 32 / fosc 2 s µs µs µs Input clock rising time Input clock falling time tckr tckf ns ns Note SCLK, EVIN input clock (Low power operating mode) Condition: VDD = 2. to 3.5 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD Item Symbol Min. Typ. Max. Unit SCLK input clock time EVIN input clock time (With noise rejector) EVIN input clock time (Without noise rejector) Cycle time "H" pulse width "L" pulse width Cycle time "H" pulse width "L" pulse width Cycle time "H" pulse width "L" pulse width tsccy tsch tscl tevcy tevh tevl tevcy tevh tevl / fosc 32 / fosc 32 / fosc 5 5 µs µs µs s s s µs µs µs Input clock rising time Input clock falling time tckr tckf ns ns Note tsccy tckf tckr SCLK VIH VIL tscl tsch tevcy tckf tckr EVIN VIH VIL tevl tevh SC8F36 TECHNICAL MANUAL EPSON 69

182 ELECTRICAL CHARACTERISTICS RESET input clock (All operating mode) Condition: VDD = 2. to 5.5 V, VSS = V, Ta = 25 C, VIH =.5VDD, VIL =.VDD Item Symbol Min. Typ. Max. Unit RESET input time tsr µs Note tsr RESET VIL VIH Power ON reset Condition: VDD = 2. to 5.5 V, VSS = V, Ta = 25 C Item Symbol Min. Typ. Max. Unit Operating power voltage RESET input time Vsr tpsr 2.4 V ms Note VDD Vsr tpsr RESET Power ON.VDD.5VDD * *2 VDD RESET VSS * When the built-in pull up resistor is not used. (The commercial samples always contain a pull-up resistor.) *2 Because the potential of the RESET terminal not reached VDD level or higher. Operating mode switching Condition: VDD = 2. to 5.5 V, VSS = V, Ta = 25 C Item Symbol Min. Typ. Max. Unit Note Stabilization time tvdc 5 ms Note) Stabilization time is the time from switching on the operating mode until operating mode is stabilized. For example, when turning the OSC3 oscillation circuit on, stabilization time is needed after the operating mode is switched on. 7 EPSON SC8F36 TECHNICAL MANUAL

183 .7 Oscillation Characteristics ELECTRICAL CHARACTERISTICS Oscillation characteristics change depending on conditions (board pattern, components used, etc.). Use the following characteristics as reference values. In particular, when a ceramic oscillator is used for OSC3, use the oscillator manufacturer s recommended values for constants such as capacitance and resistance. The oscillation start time is important because it becomes the wait time when OSC3 clock is used. (If OSC3 is used as CPU clock before oscillation stabilizes, the CPU may malfunction.) OSC (Crystal) Unless otherwise specified: VDD = Within the operating voltage in each operating mode, VSS = V, Ta = 25 C, Crystal oscillator = Q2C2*, CG = 25 pf, CD = Built-in Item Symbol Condition Min. Typ. Max. Unit Oscillation start time External gate capacitance Built-in gate capacitance Built-in drain capacitance Frequency/IC deviation Frequency/power voltage deviation Frequency adjustment range Frequency/operating mode deviation tsta CG CG CD f/ IC f/ V f/ CG f/ MD Including board capacitance In case of the chip In case of the chip VDD = constant VDD = constant, CG = 5 to 25 pf VDD = constant s pf pf pf ppm ppm/v ppm ppm * Q2C2 Made by Seiko Epson corporation Note) The SC8F36 supports a crystal oscillation circuit only. 2 The SC8F36 has no built-in gate capacitance. Note 2 OSC3 (Crystal) Unless otherwise specified: VDD = Within the operating voltage in each operating mode, VSS = V, Ta = 25 C, Crystal oscillator = Q2CA3xxx*, RF = MΩ, CG2 = CD2 = 5 pf Item Symbol Condition Min. Typ. Max. Unit Oscillation start time (Normal mode) tsta 4. MHz crystal oscillator 2 ms Oscillation start time (High speed mode) tsta 8. MHz crystal oscillator 2 ms * Q2CA3xxx Made by Seiko Epson corporation Note) The crystal oscillation start time changes by the crystal oscillator to be used, CG2 and CD2. OSC3 (Ceramic) Unless otherwise specified: VDD = Within the operating voltage in each operating mode, VSS = V, Ta = 25 C, Ceramic oscillator = CSA4.MG / CSA8.MTZ*, RF = MΩ, CG2 = CD2 = 3 pf Item Symbol Condition Min. Typ. Max. Unit Oscillation start time (Normal mode) tsta 4. MHz ceramic oscillator 5 ms Oscillation start time (High speed mode) tsta 8. MHz ceramic oscillator 5 ms * CSA4.MG / CSA8.MTZ Made by Murata Mfg. corporation Note) The ceramic oscillation start time changes by the ceramic oscillator to be used, CG2 and CD2. OSC3 (CR) Unless otherwise specified: VDD = Within the operating voltage in each operating mode, VSS = V, Ta = 25 C Item Symbol Condition Min. Typ. Max. Unit Oscillation start time (Normal mode) Oscillation start time (High speed mode) Frequency/IC deviation (Normal mode) Frequency/IC deviation (High speed mode) tsta tsta f/ IC f/ IC RCR = constant RCR = constant ms ms % % Note Note Note SC8F36 TECHNICAL MANUAL EPSON 7

184 ELECTRICAL CHARACTERISTICS.8 Characteristics Curves (reference value) High level output current-voltage characteristic Ta = 85 C Max. value VDD - VOH [V] VDD =.8 V VDD = 2.4 V -4-6 IOH [ma] VDD = 3.5 V -8 - Low level output current-voltage characteristic 4 2 Ta = 85 C Min. value VDD = 3.5 V IOL [ma] VDD = 2.4 V VDD =.8 V VOL [V] EPSON SC8F36 TECHNICAL MANUAL

185 ELECTRICAL CHARACTERISTICS LCD drive voltage-ambient temperature characteristic.2vc5.9vc5 Typ. value TYPE A TYPE B.6VC5.3VC5 VC5 [V] VC5.97VC5.94VC5.9VC5.88VC Ta [ C] LCD drive voltage-supply voltage characteristic 7. Ta = 25 C Typ. value TYPE B (LCX = FH) VC5 [V] TYPE A (LCX = FH) TYPE B (LCX = H) TYPE A (LCX = H) VDD [V] SC8F36 TECHNICAL MANUAL EPSON 73

186 ELECTRICAL CHARACTERISTICS LCD drive voltage-load characteristic 6. Ta = 25 C Typ. value VC5 [V] TYPE B (LCX = 8H) TYPE A (LCX = 8H) IVC5 [µa] SVD voltage-ambient temperature characteristic.8vsvd Typ. value.6vsvd.4vsvd.2vsvd VSVD [V] VSVD.98VSVD.96VSVD.94VSVD.92VSVD.9VSVD Ta [ C] 74 EPSON SC8F36 TECHNICAL MANUAL

187 ELECTRICAL CHARACTERISTICS Power current (During operation with OSC3) 4.5 <Crystal/ceramic oscillation> Ta = 25 C IDD4 [ma] High-speed mode (Typ.) Normal mode (Typ.) fosc3 [MHz] Power current (During operation with OSC3) 5 <CR oscillation> Ta = 25 C 4 IDD4 [ma] 3 2 High-speed mode (Max.) High-speed mode (Typ.) Normal mode (Max.) Normal mode (Typ.) RCR [kω] SC8F36 TECHNICAL MANUAL EPSON 75

188 ELECTRICAL CHARACTERISTICS Power current-ambient temperature characteristic (In HALT status) Typ. value IDD2 [µa] High-speed mode Normal mode Low-power mode Ta [ C] Power current-ambient temperature characteristic (CPU is under khz operation) Typ. value 2 8 High-speed mode 6 IDD3 [µa] Normal mode Low-power mode Ta [ C] 76 EPSON SC8F36 TECHNICAL MANUAL

189 ELECTRICAL CHARACTERISTICS Power current-ambient temperature characteristic (CPU is under MHz operation) Typ. value IDD4 [ma].2..8 High-speed mode Normal mode Ta [ C] SC8F36 TECHNICAL MANUAL EPSON 77

190 ELECTRICAL CHARACTERISTICS CR oscillation frequency characteristic Note: Oscillation frequency changes depending on the conditions (components used, board pattern, etc.). In particular, the OSC3 oscillation frequency changes extensively depending on the product form (chip, plastic package or ceramic package) and board capacitance. Therefore, use the following charts for reference only and select the resistance value after evaluating the actual product. (The resistance value should be set to RCR 5 kω.) Oscillation frequency-resistor characteristic Ta = 25 C Typ. value fosc3 [khz] High-speed mode Normal mode RCR [kω] CR oscillation frequency-ambient temperature characteristic RCR = 2 kω fosc3 [MHz] High-speed mode Normal mode Ta [ C] 78 EPSON SC8F36 TECHNICAL MANUAL

191 PACKAGE PACKAGE. Plastic Package QFP2-76pin 26 ±.4 24 ±. (Unit: mm) ±. 26 ±.4 INDEX max.4 ± ± SC8F36 TECHNICAL MANUAL EPSON 79

192 PACKAGE PFBGA-8pin Top View A Corner D Index E S A y S A Bottom View e SD ZD A Corner P N M L K J H G F E D C B A ZE SE e φ b φ M Symbol D E A A e b X Y SD SE ZD ZE Dimension in Millimeters Min Nom Max EPSON SC8F36 TECHNICAL MANUAL

193 2 PAD LAYOUT 2 PAD LAYOUT 2. Diagram of Pad Layout Die No Y X (, ) mm mm Chip thickness: 4 µm Pad opening: 95 µm SC8F36 TECHNICAL MANUAL EPSON 8

194 82 EPSON SC8F36 TECHNICAL MANUAL 2 PAD LAYOUT 2.2 Pad Coordinates Table 2.2. Pad coordinates (Unit: µm) No Name OSC OSC2 TEST RESET MCU/MPU K/BREQ K/EVIN K7 K6 K5 K4 K3 K2 K K P7/CMPM/AD7 P6/CMPP/AD6 P5/CMPM/AD5 P4/CMPP/AD4 P3/SRDY P2/SCLK P/SOUT P/SIN AVDD AVSS AVREF VDD P7/D7 P6/D6 P5/D5 P4/D4 P3/D3 P2/D2 P/D P/D R/A R/A R2/A2 R3/A3 R4/A4 R5/A5 R6/A6 R7/A7 R/A8 R/A9 R2/A R3/A R4/A2 R5/A3 R6/A4 R7/A5 R2/A6 R2/A7 R22/A8 R23/RD R24/WR R25/CL R26/FR/TOUT R27/TOUT X 2,533 2,47 2,32 2,86 2,59,943,828,72,597,48,366,25,35, ,3 -,28 -,334 -,449 -,565 -,68 -,796 -,9-2,27-2,42-2,258-2,373-2,489-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896 Y 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,578 2,463 2,347 2,232 2,6 2,,885,77,654,539,423,38,92,77 96 Pad Coordinate No Name R3/CE R3/CE R32/CE2 R33/CE3 R34/FOUT R35 R36 R37 VSS R5/BZ R5/BACK/BZ COM COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM COM COM2 COM3 COM4 COM5 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG2 SEG2 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG3 SEG3 X -2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,6-2,484-2,358-2,242-2,6-2, -,874 -,758 -,63 -,56 -,389 -,274 -,47 -, Y ,48 -,63 -,279 -,394 -,5 -,625 -,74 -,856 -,972-2,87-2,23-2,339-2,455-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896 Pad Coordinate No Name SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG4 SEG4 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG5 COM3/SEG5 COM3/SEG52 COM29/SEG53 COM28/SEG54 COM27/SEG55 COM26/SEG56 COM25/SEG57 COM24/SEG58 COM23/SEG59 COM22/SEG6 COM2/SEG6 COM2/SEG62 COM9/SEG63 COM8/SEG64 COM7/SEG65 COM6/SEG66 VDF SPRG CLKW VEPEXT RXD SCLK TXD CE CD CC CB CA VC5 VC4 VC3 VC2 VC OSC3 OSC4 VD VDD VSS VOSC X,32,47,274,389,56,63,758,874 2, 2,6 2,242 2,358 2,484 2,6 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 2,896 Y -2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,896-2,456-2,34-2,24-2,99 -,976 -,845 -,73 -,64 -,499 -,383 -,268 -,52 -, ,93,29,324,44,555,67,786,92 2,7 2,33 2,248 2,364 2,479 2,595 Pad Coordinate

195 APPENDIX A PROM PROGRAMMING APPENDIX A PROM PROGRAMMING A. Outline of Writing Tools The following tools are provided for writing user data to the Flash EEPROM built into the SC8F36. Select one according to the development environment. () Serial Programming (On Board Writer) This PROM writer features smaller size and weight as well as supporting DC power supply (5. V battery, etc.), this makes it possible to simply configure an on-board PROM programming environment. USB interface type USB-Serial On Board Writer (product name: S5UC88W4) On Board Writer Control Software (OBPW88.EXE, RW8F36.INI) USB-Serial conversion driver Operating voltage: 5. V ±.5 V (The power supply for the target can be used.) PC interface: USB Ver.. RS-232C interface type On Board Writer (product name: S5UC88W3) On Board Writer Control Software (OBPW88.EXE, RW8F36.INI) Operating voltage: 5. V ±.5 V (The power supply for the target can be used.) PC interface: EIA-RS-232C (2) Serial Programming (Universal Writer) These tools support the clock synchronous serial programming method and the asynchronous serial programming method allowing high-speed on-board programming. Universal Writer (product name: S5UC88W) SC88/SC63 Serial Connector (product name: S5UC88X) Control Software (RW88F36.EXE, 88F36.FRM) (3) Parallel Programming These tools allows high-speed programming for packaged devices before mounting on boards. Universal Writer (product name: S5UC88W) SC8F36 Adapter Socket (product name: S5UC8836X) Control Software (RW88F36.EXE, 88F36.FRM) The following explanations use the appellations listed below instead of the product names. S5UC88W4 USB-Serial On Board Writer S5UC88W3 On Board Writer S5UC88W Universal Writer S5UC88X SC88/SC63 Serial Connector S5UC8836X SC8F36 Adapter Socket Each software listed above are included in the SC88 Family Integrated Tool Package (S5UC88C). The USB-Serial conversion driver for the On Board Writer Control Software are included in the SC88 Family Integrated Tool Package (S5UC88C) Ver. 6 or later. The On Board Writer Control Software (OBPW88.EXE, RW8F36.INI) supports both USB interface type and RS-232C interface type PROM writers. SC8F36 TECHNICAL MANUAL EPSON 83

196 APPENDIX A PROM PROGRAMMING A.2 Serial Programming (On Board Writer) A.2. Serial programming environment (On Board Writer) Prepare a personal computer system as a host computer, the PROM programming tools and the data for programming the SC8F36. () Personal computer IBM-PC/AT or compatible with a USB port or RS-232C port (2) OS Windows 2/XP English or Japanese version (3) PROM programming tools S5UC88W4 (USB interface type) package or S5UC88W3 (RS-232C interface type) package On Board Writer Control Software (OBPW88.EXE, RW8F36.INI) USB-Serial conversion driver (required only when the USB-Serial On Board Writer is used) (4) User data (ROM data HEX file) Execute the FIL8F36 to create the built-in ROM data HEX data file (C8F36xxx.PSA) from the program data HEX file (C8F36xxx.SA). Refer to the S5UC88C Manual for details of the FIL8F36. c8f36xxx.sa Program data HEX file (Motorola S2 format) fil8f36 Extract built-in ROM data and fill unused area with FF c8f36xxx.psa Built-in ROM data HEX file (Motorola S2 format) Fig. A.2.. FIL8F36 execution flow 84 EPSON SC8F36 TECHNICAL MANUAL

197 A.2.2 System connection for serial programming (On Board Writer) APPENDIX A PROM PROGRAMMING Below shows connection diagrams between the PC and the USB-Serial On Board Writer (S5UC88W4) with a target, and between the PC and the On Board Writer (S5UC88W3) with a target. When the USB-Serial On Board Writer (S5UC88W4) is used USB S5UC88W4 (USB-Serial On Board Writer) Target VDD VSS + 5. V power supply - USB interface cable SIO cable Fig. A.2.2. PROM programming system connection diagram (USB interface type) Note: When using a USB hub to connect the USB-Serial On Board Writer to the PC, the USB hub should be driven with an external power supply. So use a USB hub that operates with an external power supply. When the On Board Writer (S5UC88W3) is used COMx S5UC88W3 (On Board Writer) Target VDD VSS + 5. V power supply - RS-232C interface cable SIO cable Fig. A PROM programming system connection diagram (RS-232C interface type) The system should be connected according to the following procedure. () Make sure the power for the personal computer is switched off. (2) As shown in the above figures, connect between the USB-Serial On Board Writer (S5UC88W4) or On Board Writer (S5UC88W3) and the PC using the interface cable included with the package. Notes: Turn the personal computer off before connecting and disconnecting the On Board Writer (S5UC88W3). The USB-Serial On Board Writer (S5UC88W4) can be connected after the PC is turned on. Secure the RS-232C cable with the connector screws to prevent malfunction. SC8F36 TECHNICAL MANUAL EPSON 85

198 APPENDIX A PROM PROGRAMMING A.2.3 Serial programming procedure (On Board Writer) The SC88 Family Integrated Tool Package (S5UC88C) must be installed in the personal computer to be used before starting serial programming. Refer to the S5UC88C Manual for the installation. () Connecting the system Connect the system as shown in Section A.2.2, "System connection for serial programming (On Board Writer)". (2) Power on Turn the personal computer on. (3) Checking the serial port assignment (Required only when the On Board Writer is used) Check the serial port assignment on the personal computer. The On Board Writer uses the COM port by default setting. (4) Installing the USB-Serial conversion driver (Required only when the USB-Serial On Board Writer is used) When the USB-Serial On Board Writer (S5UC88W4) is connected for the first time, a dialog box appears on the PC screen to prompt the user to install the driver. Install the USB-Serial conversion driver by following the prompts. The USB-Serial conversion driver was copied in the "\EPSON\SC88\writer\driver" folder when the SC88 Family Integrated Tool Package (S5UC88C Ver. 6 or later) was installed. Specify this folder as the driver location. (5) Checking the serial port assignment (Required only when the USB-Serial On Board Writer is used) Open the Windows [Control Panel] [System] [Hardware] tab [Device Manager] to check the COM port to which the USB-Serial port is assigned. The USB-Serial conversion driver assigns a logical COM port to the physical USB port and transfers the COM port input/output to the USB input/output. Thus the On Board Writer Control Software can control the USB-Serial On Board Writer connected to the USB port through the assigned COM port. (6) Preparing the On Board Writer Control Software The On Board Writer Control Software was copied in the "\EPSON\SC88\writer\OBPW" folder when the SC88 Family Integrated Tool Package (S5UC88C Ver. 4 or later) was installed. When using the On Board Writer Control Software in another folder, the following two files should be copied from the OBPW folder. OBPW88.EXE RW8F36.INI (7) Connecting the target board to the USB-Serial On Board Writer or On Board Writer As Figure A.2.2. or A shows, connect the target board to the USB-Serial On Board Writer (S5UC88W4) or On Board Writer (S5UC88W3) using the supplied SIO cable. (8) Connecting the power supply for PROM programming Connect the power supply for PROM programming (5. V) to the target board. Notes: Turn off the power of the target board except for the PROM programming power supply. Since PROM programming uses a 5.-V power source, be careful of the voltage ratings of the parts on the target board. (9) Turning the PROM programming power on Turn the PROM programming power on. This also supplies the power to the USB-Serial On Board Writer (S5UC88W4) or On Board Writer (S5UC88W3) through the SIO cable. 86 EPSON SC8F36 TECHNICAL MANUAL

199 APPENDIX A PROM PROGRAMMING () Starting up the On Board Writer Control Software Double-click the OBPW88.EXE icon. The [Initial File] dialog box shown below appears when the On Board Writer Control Software starts up. Select the initial file with the same name as the microcomputer model. RW8fxxx.ini 8fxxx: microcomputer model name (e.g. 8f36 for the SC8F36) After an initial file is selected, the window shown below appears. Command window Output window SC8F36 TECHNICAL MANUAL EPSON 87

200 APPENDIX A PROM PROGRAMMING () Selecting a serial port Click the [Setting] button (or choose [Setting] from the [Option] menu) to display the [Settings] dialog box. [Setting] button Click the [Com] tab to open the page shown below. When USB-Serial On Board Writer (USB interface type) is used, select the COM port that was determined in Step (5). When the On Board Writer (RS- 232C interface type) is used, select the COM port to which the RS-232C cable has been connected. (2) Loading user data to the personal computer Click the [Load] button (or choose [Load] from the [Command] menu) to display the [Select file] dialog box. [Load] button Choose the PSA file to be written to the PROM using the [Browse] button and then click [OK]. [Browse] button When data is loaded normally, "Complete" is displayed in the output window. (3) Erasing PROM data Click the [Erase] button (or choose [Erase] from the [Command] menu) to display an information dialog box. Clicking the [OK] button starts erasing the PROM data. [Erase] button When the PROM is erased normally, "Complete" is displayed in the output window. Notes: The microcomputer in the serial programming mode outputs a 37.2 khz clock from the R27 port when it communicates with the On Board Writer (at Steps 3, 4, 5 and 6). Inspection data is written to the PROM at shipment, so erase it once to initialize the contents. The PROM is protected against a read out when user data is written at Seiko Epson s factory. The protection is released after the contents have been erased by executing "Erasing PROM data". (4) Blank check after erasing Click the [Blank] button (or choose [Blank Check] from the [Command] menu) starts process that checks if the PROM is completely erased. [Blank] button When the blank check is finished normally, "Complete" is displayed in the output window. 88 EPSON SC8F36 TECHNICAL MANUAL

201 APPENDIX A PROM PROGRAMMING (5) Writing user data Click the [Program] button (or choose [Program] from the [Command] menu) to display an information dialog box. Clicking the [OK] button starts writing the loaded data to the PROM. [Program] button When writing is finished normally, "Complete" is displayed in the output window. Note: Do not send the writer control window behind any other applications as it may cause a communication error. (6) Verifying user data after writing Click the [Verify] button (or choose [Verify] from the [Command] menu) starts verification of the PROM. [Verify] button When verification is finished without any error, "Complete" is displayed in the output window. (7) Turning the PROM programming power off Turn the PROM programming power off. (8) Disconnecting the target board Disconnect the target board after checking that writing has finished normally. Note: Make sure that the PROM programming power is off before disconnecting and connecting the target board. (9) Terminating the On Board Writer Control Software Choose [Exit] from the [File] menu of the On Board Writer control window or click the close box to terminate the On Board Writer Control Software. To continue writing, repeat from step (7) to step (9). (2) Power off Turn the personal computer off. SC8F36 TECHNICAL MANUAL EPSON 89

202 APPENDIX A PROM PROGRAMMING A.2.4 Connection diagram for serial programming (when On Board Writer is used) The figures and tables below show the connection diagram on the target board and the signal specifications. USB interface type: when the USB-Serial On Board Writer (S5UC88W4) is used To On Board Writer On Board Writer (S5UC88W4) interface connector VDDF VDD CLK VSS RXD TXD RESET SPRG VSS SPRG V Microcomputer on target board VDF VDD CLKW RXD TXD RESET SPRG VSS Fig. A.2.4. Connection diagram for on-board programming (USB interface type) Connector pin No Table A.2.4. Signal specifications (USB interface type) Signal name Description VDDF VDD CLK System clock output VSS RXD TXD RESET SPRG VSS Programming power supply pin Power supply pin Ground pin Serial I/F data input Serial I/F data output Initial reset output Programming mode setup output (for negative polarity I/O models) Ground pin SPRG Programming mode setup output (for positive polarity I/O models) Microcomputer pin to be connected VDF pin VDD pin CLKW pin VSS pin TXD pin RXD pin RESET pin SPRG pin VSS pin N.C. Table A Connectors for connecting On Board Writer (USB interface type) Name Box header (male) [target side] Model name LCPL (3M) or equivalent Socket connector (female) Socket connector 79-B5FL (3M) [SIO cable side] Strain relief (3M) or equivalent 9 EPSON SC8F36 TECHNICAL MANUAL

203 APPENDIX A PROM PROGRAMMING RS-232C interface type: when the On Board Writer (S5UC88W3) is used To On Board Writer On Board Writer (S5UC88W3) interface connector VDDF VDD CLK VSS SCLK VSS RXD VSS TXD VSS RESET VSS SPRG VSS SPRG SRDY V Microcomputer on target board VDF VDD CLKW RXD TXD RESET SPRG VSS Fig. A Connection diagram for on-board programming (RS-232C interface type) Connector pin No , 6, 8,, 2, 4 Table A Signal specifications (RS-232C interface type) Signal name Description VDDF VDD CLK SCLK RXD TXD RESET SPRG SPRG SRDY VSS Programming power supply pin Power supply pin System clock output Serial I/F clock output Serial I/F data input Serial I/F data output Initial reset output Programming mode setup output (for negative polarity I/O models) Programming mode setup output (for positive polarity I/O models) Reserved Ground pin Microcomputer pin to be connected VDF pin VDD pin CLKW pin N.C. TXD pin RXD pin RESET pin SPRG pin N.C. N.C. VSS pin Table A Connectors for connecting On Board Writer (RS-232C interface type) Name Box header (male) [target side] Model name LCFL (3M) or equivalent Socket connector (female) Socket connector 796-B5FL (3M) [SIO cable side] Strain relief (3M) or equivalent Notes: Prepare a 5.-V power supply for PROM programming, since the power (5. V) of the On Board Writer must be supplied from the target board. Since PROM programming uses a 5.-V power source, be careful of the voltage ratings of the parts on the target board. When the On Board Writer is connected, the ports other than above are placed in the initial status. SC8F36 TECHNICAL MANUAL EPSON 9

204 APPENDIX A PROM PROGRAMMING A.2.5 On Board Writer Control Software A.2.5. Starting up Double-click the OBPW88.EXE icon to start up the On Board Writer system. The dialog box shown below appears when the On Board Writer Control Software starts up. Select the initial file with the same name as the microcomputer model. RW8fxxx.ini 8fxxx: microcomputer model name (e.g. 8f36 for the SC8F36) After an initial file is selected, the window shown below appears. Command window Accepts the commands input from the keyboard. Output window Displays the execution results. 92 EPSON SC8F36 TECHNICAL MANUAL

205 APPENDIX A PROM PROGRAMMING A Setup Click the [Setting] button (or choose [Setting] from the [Option] menu) to display the [Settings] dialog box. [Setting] button Selecting a serial port ([Com] tab) When USB-Serial On Board Writer (USB interface type) is used, select the COM port that was assigned to the USB-Serial port (see Step (5) in Section A.2.3). When the On Board Writer (RS-232C interface type) is used, select the COM port to which the RS-232C cable has been connected. Specifying the log file ([Folder] tab) When saving the execution results to a log file, enter (or choose) the log file name and place a check in the [Create Log] check box. To disable logging, remove the check from the check box. Specifying the editor path ([Editor] tab) Specify the path to the editor used to open a log file from the On Board Writer Control Software. "notepad.exe" is used as the default editor unless specified. SC8F36 TECHNICAL MANUAL EPSON 93

206 APPENDIX A PROM PROGRAMMING A Operating method All the On Board Writer commands such as PROM writing can be executed using the buttons on the window. This section explains the commands individually in the following manner. Function: Shows the command function. Usage: Button Menu Keyboard [Command] menu - [Program] >FW Description: Shows the button, menu command and typing command line to execute the command. Describes the operation and display contents after executing the command. If "A progress window appears to show progress of the process." is described here, a progress window is displayed while the command is executing and the [Cancel] button on the window allows termination of the command being executed. Note: Describes precautions. 94 EPSON SC8F36 TECHNICAL MANUAL

207 APPENDIX A PROM PROGRAMMING LOAD (PSA file) Function: Usage: Loads user data files for PROM (xxxxxx.psa) to the memory on the personal computer. Button Menu [Command] menu - [Load] Keyboard >L drive:\folder\file name (drive:\folder\file name: PSA file name) Description: () The [Select file] dialog box appears. [Browse] button (2) Clicking the [Browse] button displays the Windows standard file select dialog box. Choose the file to be loaded from the dialog box. Then click the [OK] button. (3) When data is loaded normally, "Complete" is displayed in the output window. Note: This command can load files in Motorola S2 format only. 2 ERASE Function: Usage: Erases PROM data. Button Menu Keyboard [Command] menu - [Erase] >FERS Description: Note: () An information dialog box appears. (2) Clicking the [OK] button starts erasing the PROM. (3) A progress window appears to show progress of the process while the command is executing. Clicking the [Cancel] button terminates the process. (4) When the PROM is erased normally, "Complete" is displayed in the output window. When the process is terminated, the PROM must be erased before data can be written. SC8F36 TECHNICAL MANUAL EPSON 95

208 APPENDIX A PROM PROGRAMMING 3 BLANK CHECK Function: Usage: Checks whether the PROM is completely erased or not. Button Menu Keyboard [Command] menu - [Blank Check] >FE Description: Note: () Starts a blank check. (2) A progress window appears to show progress of the process. Clicking the [Cancel] button terminates the process. (3) When the check is finished without finding any address that is not erased, "Complete" is displayed in the output window. (4) If error addresses that have not been erased are found, the address and data are displayed. Example: Address READ 2 3 : : When an erase error is detected, the PROM must be erased before data can be written. 4 PROGRAM Function: Usage: Writes the data loaded by the [Load] command to the PROM. Button Menu Keyboard [Command] menu - [Program] >FW Description: Note: () An information dialog box appears. (2) Clicking the [OK] button starts write process. (3) A progress window appears to show progress of the process. Clicking the [Cancel] button terminates the process. (4) When writing is finished normally, "Complete" is displayed in the output window. Do not send the writer control window behind any other applications as it may cause a communication error. 96 EPSON SC8F36 TECHNICAL MANUAL

209 APPENDIX A PROM PROGRAMMING 5 VERIFY Function: Usage: Compares the data loaded by the [Load] command and the data read from the PROM. Button Menu Keyboard [Command] menu - [Verify] >FV Description: () Starts verification process. (2) A progress window appears to show progress of the process. Clicking the [Cancel] button terminates the process. (3) When both data are the same, "Complete" is displayed in the output window. (4) When a verify error is detected, the error address and data are displayed. 6 READ Function: Usage: Reads the PROM data to the memory on the personal computer. Button Menu Keyboard [Command] menu - [Read] >FR Description: Note: () An information dialog box appears. (2) Clicking the [OK] button starts read process. (3) A progress window appears to show progress of the process. Clicking the [Cancel] button terminates the process. (4) When data is read normally, "Complete" is displayed in the output window. The memory data on the personal computer is overwritten with the read data. 7 PROTECT Function: Usage: Protects the PROM from read out. Button Menu Keyboard [Command] menu - [Protect] >FPROTECT Description: Note: () An information dialog box appears. (2) Clicking the [OK] button starts protect process. (3) When the process is finished normally, "Complete" is displayed in the output window. When the PROM is protected, execution of all the commands except "Erase" are disabled. SC8F36 TECHNICAL MANUAL EPSON 97

210 APPENDIX A PROM PROGRAMMING 8 MACRO Function: Usage: Successively executes the commands described in a macro file. Button Menu Keyboard [Command] menu - [Macro] None Description: Macro file: () A file-select dialog box appears. (2) Select a macro file and then click the [OK] button. The macro file will be loaded and the described commands will be executed. Use a text editor to create macro files. ".CMD" is recommended for the file extension. Write the commands in order of execution and save as a text file. The command should be written one line by one line in the command line format listed at Usage: Keyboard. Any words following a ";" are regarded as a comment. Example: Macro file <TEST.CMD> L D:\WORK\C8Fxxx.PSA Load PROM HEX file FERS Erase PROM data FE PROM blank check FW Program PROM FV PROM verify check ;--- PROTECT--- Comment FPROTECT Read protect 98 EPSON SC8F36 TECHNICAL MANUAL

211 APPENDIX A PROM PROGRAMMING 9 DUMP Function: Displays the contents of the PC memory PROM area in hexadecimal numbers. The memory contents can be edited in the [Dump] window. Usage: Button [Dump] button Menu [Command] menu - [Dump] Keyboard >D address (address: Display start address; optional) Description: () The [Dump] window appears. Displays the last page. Displays the next page. Display start address is specified. Displays the previous page. Displays the top page. (2) To edit the memory contents, enter a value after placing the cursor on the address to be edited. SC8F36 TECHNICAL MANUAL EPSON 99