Transaction-Level Models for PowerPC and CoreConnect

Transcription

1 Transaction-Level Models for PowerPC and CoreConnect 11 th European SystemC Users Group Meeting Reinaldo Bergamaschi IBM T. J. Watson Research Center Yorktown Heights, NY, USA Copyright IBM Corporation 2005

2 Contents SystemC Modeling of IBM s CoreConnect Architecture POWER.ORG

3 Typical Applications EBC 405 CPU UIC DMA OPB Arbiter GPIO UART0 PLB Arbiter PLB 64 bit UART1 HSMC PM MAL PLB-OPB Bridge IIC GPT CLOCK/RESET GEN PLL Clocks / resets Private OPB RX FIFO EMAC TX FIFO OPB 32 bit

4 Typical Applications PWM 1284 Smart Cards I2C1 I2C2 Service MicroController UART1 UART2 GPIO TV/VCR Timers/ PWM 1284 Smart Card I/F 2 I C I/F SCP I/F SICC GPIO DENC OPB Bus Interrupt Controller OPB Bridge MPEG2 Video Decoder PLB-1 PLB-2 MPEG2/DVB Transport OSD 4K- I Cache 401 CPU 2K- D Cache OCM Memory DVB Descram MPEG2 Audio Decoder DMA Controller C R O S S - B A R S W I T C H PLB PLB P M O Y W T E E R SDRAM I/F PLL-System PLL-Audio Clock Gen. EDO DRAM SRAM I/F F 1 L M A B S H S 2 D M R B A M D R A M EGV Port Ext. DENC NIM To 1394 Audio D/As L R VCXO

5 Transaction-Level Modeling Abstractions? Algorithmic level (AL)? Architecture/implementation independent, e.g., Matlab, UML? Programmers View (PV)? Bit-true representation of the HW, register accurate, no detailed timing? Programmers View + Timing (PVT)? Same as PV plus detailed timing and synchronization (Cycle approximate in most cases, accurate in a few cases)? Cycle Accurate (CA)? Clocked abstraction, interfaces and transactions? RTL? Clocked abstraction, actual chip signals De-facto implementations? Mixed of PVT and CA. CA for communication, PVT for computation

6 Transaction-Level Modeling Abstractions Courtesy of SpiraTech Ltd., UK (

7 SystemC Modeling of IBM s CoreConnect Architecture Transactions:? High-level functional transactions: CA for communication, PVT for computation.? Information is passed via special request structures? APIs:? blocking_read (plb_request *p), blocking_write (plb_request *p)? non_blocking_read ( ), non_blocking_write ( )? direct_read ( ), direct_write ( )? All protocol handshaking hidden inside these APIs? Users do not need to know how protocol works Goal? Run application code at reasonable speeds (e.g., 100K c/s)? Analyze latencies, throughput, bus contention? Architectural trade-offs

8 SystemC Modeling of IBM s CoreConnect Architecture DCR Arbiter DCR Bus dcr_arbiter_if dcr_bus_if PLB Master PLB Master intrpt_ctr_if UIC intrpt_req_if plb_bus_if dcr_slave_if PLB_OPB Bridge OPB Slave plb_arbiter_if PLB Bus plb_slave_if plb_bus_if OPB_PLB Bridge OPB Bus opb_slave_if opb_bus_if OPB Master PLB Arbiter PLB Slave DMA Controller opb_bus_if OPB Arbiter opb_arbiter_if

9 SystemC Modeling of IBM s CoreConnect Architecture ISS + SystemC Wrapper ICU plb_mp1 DCU plb_mp2 PLB Arbiter PLB Bus plb_arbiter_if plb_ap plb_sp1 PLB_OPB Bridge opb_mp1 OPB Bus opb_sp1 Memory Controller mem_p Address map: 0x6000 to 0x6FFF Memory Model #define Ext_Mem 0x6F00 main (..) { char *p = Ext_Mem; // ; *p = A + B; //.; } 1) Issw.plb_mp2->non_blocking_write (0x6F00, sum(a+b)) 2) plb_bus.plb_ap->arbitrate_request( ) 3) Plb queries its slaves and finds plb_opb_bridge mapped to address 0x6F00 4) plb_bus.plb_sp1->write(0x6f00, sum) 5) brg.opb_mp1->non_blocking_write (0x6F00, sum) 6) opb_bus.opb_sp1->write(0x6f00, sum) 7) mc.mem_p->write(0x6f00, sum) 8) Mem[0x6F00] = sum

10 SystemC Modeling of IBM s CoreConnect Architecture Blocking/Non-blocking and Burst/Single transfer? These are not the same thing!? Blocking/Non-blocking have nothing to do with the protocol? Burst/Single Transfer modes depend on the bus protocol PowerPC 405 can issue a max of 2 PLB requests at a time? Instruction fetch (ICU) and Data read/write (DCU)? Both of them can be burst or single transfer? But they must be non-blocking (otherwise they can t be issued concurrently) ISS + SystemC Wrapper ICU plb_mp1 plb_mp2 DCU PLB Arbiter PLB Bus plb_arbiter_if plb_ap

11 SystemC Modeling of IBM s CoreConnect Architecture Interrupt Transactions? Interrupt Slave issues interrupt requests through the intrpt_req_port? The Interrupt controller check whether the request is enabled/critical/non-critical, and passes the request to the CPU via the intrpt_ctr_if port ISS + SystemC Wrapper Intrpt_ctr_if Intrpt_req_port Interrupt Controller Interrupt Slave Interrupt Slave Interrupt Slave Intrpt_req_port

12 POWER.ORG Power.org is an open developer community and standards organization whose mission is to develop and enable specifications for the promotion and expansion of the Power Architecture solutions and ecosystem Members intend to define open Power Architecture specifications initially focusing on:? Bus Architecture specifications? Server platform specifications? Other workgroups may be defined in the future SystemC models will be made available to the Power.org community later this year

13 POWER.ORG Initial List of members:? AMCC? Bull? Cadence Design Systems? Chartered Semiconductor Manufacturing? Culturecom? IBM? Jabil Circuit? Novell? Red Hat? Sony? Shanghai Belling? Synopsys? Thales? Tundra Semiconductor? Wistron