FP_LVDS user guide V2.2 FP_LVDS. User Guide

Transcription

1 FP_LVDS User Guide 4DSP Inc. 955 S Virginia Street, Suite 214, Reno, NV 89502, USA 4DSP BV, Ondernemingsweg 66f, 2404 HN, Alphen a/d Rijn, Netherlands support@4dsp.com This document is the property of 4DSP and may not be copied nor communicated to a third party without the written permission of 4DSP. 4DSP Inc. 2009

2 Revision History Date Revision Version First release Updated table 1 to reflect the FMM482 user manual Updated the connector to be a Mictor type Removed the FPGA mapg form the table 1 since it was not supposed to be there Updated table 4 and 5. numbering was not right Updated figure and figure to show the dimensions for the mictor connector Modified the numbering of the Mictor connector (Tables 4 and 5) Minor modifications Added an image of the frontpanel June

3 Table of Contents 1 General description Installation Requirements and handling instructions Design Data connector ESD protection Encryption battery Front panel connector Environment Temperature Safety EMC Warranty...11 June

4 1 General description The FP_LVDS is a daughter card to be used in conjunction with the FM48x range of products. The FP_LVDS brings 36 differential LVDS I/Os to the front panel of the mother board using two MICTOR series connectors. These connectors easily mate with the PRECISION INTERCONNECT cable assemblies. Further also ESD protection diodes are used to provide protection against ESD pulses. A block diagram of the FP_LVDS is shown in Figure 1. Figure 1: FP_LVDS block diagram The daughter card will have a specific that allows it to fit within the CMC standard IO envelope. The following two figures depict how the daughter card would be mounted on the base card. Figure 2: FP_LVDS daughter card side view June

5 Figure 2 : FP_LVDS daughter card dimensions 2 Installation 2.1 Requirements and handling instructions The FP_LVDS must be installed on a motherboard compliant to the PMC daughter card specifications for FM48x series Do not flex the board Observe SSD precautions when handling the board to prevent electrostatic discharges. Do not install the FP_LVDS while the motherboard is powered up. June

6 3 Design 3.1 Data connector The daughter card interfaces to the PMC via a 120 connector (QSH F-D-DP-A). The data connector assignment is given in the tables below. Signal Name Signal name 1 NC NC 2 3 NC NC 4 5 NC NC 6 7 NC NC 8 9 P1_P0 P1_P P1_N0 P1_N P1_P2 P1_P P1_N2 P1_N P1_P4 P1_P P1_N4 P1_N NC P1_oCLKP NC P1_oCLKN P1_P6 P1_P P1_N6 P1_N P1_P8 P1_P P1_N8 P1_N NC P1_iCLKP (1) NC P1_iCLKN (1) NC NC NC NC 40 Table 1 : Front Panel IO daughter card assignment Bank A (1) Connected to a global clock on the FPGA. LVDS output not supported. (2) Connected to a regional clock on the FPGA. LVDS output not supported. June

7 Differential Differential 41 P1_P10 P1_P P1_N10 P1_N11 45 P1_P12 P1_P P1_N12 P1_N13 49 NC NC NC NC P1_P14 P1_P P1_N14 P1_N15 57 P2_P0 P2_P P2_N0 P2_N P2_P2 P2_P P2_N2 P2_N P2_P4 P2_P P2_N4 P2_N NC NC NC NC NC NC V/2.5V/1.8V Vbatt (3) V/2.5V/1.8V Reserved V/2.5V/1.8V 3.3V/2.5V/1.8V 80 Table 2 : Front Panel IO daughter card assignment Bank B (1) Connected to a global clock on the FPGA. LVDS output not supported. (2) Connected to a regional clock on the FPGA. LVDS output not supported June

8 Differential Differential 81 P2_P6 P2_P P2_N6 P2_N P2_P8 P2_P P2_N8 P2_N P2_P10 P2_P P2_N10 P2_N11 93 P2_P12 P2_P P2_N12 P2_N13 97 P2_iCLKP (1) P2_oCLKP P2_iCLKN (1) P2_oCLKN P2_P14 P2_P P2_N14 P2_N NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 120 Table 3 : Front Panel IO daughter card assignment Bank B and C (1) Connected to a global clock on the FPGA. LVDS output not supported. (2) Connected to a regional clock on the FPGA. LVDS output not supported. (3) Vbatt is connected to the FPGA Vbatt on the PMC 3.2 ESD protection In order to protect the sensitive FPGA IO s extra protection diodes are used on the FP_LVDS card. The protection is build using the MAX3208E. This is a low-capacitance, ±15kV ESD-protection diode array with an integrated transient voltage suppressor (TVS) clamp. The device protects against ESD pulses up to ±15kV Human Body Model, ±8kV Contact Discharge, and ±15kV Air-Gap Discharge, as specified in IEC An integrated TVS ensures that the voltage rise seen on VCC during an ESD event is clamped to a known voltage. A total of 18 devices are required to protect all 36 differential lines that are used on the FP_LVDS. June

9 3.3 Encryption battery The FP_LVDS also incorporates a small watch battery that connects to the Vbatt of the FPGAs on the motherboard. This power supply is required for the FPGA to retain its encryption key. This is only required when encryption is used. The battery holder is from Keystone (1061) and accepts one 20 mm battery. 3.4 Front panel connector All the LVDS signals from the data connector are routed to the two 18 pairs front panel connectors (MICTOR ). The front panel connector descriptions are given in the tables below. Figure 3: FP_LVDS front view Signal Name Signal name 1 P1_N0 P1_N1 2 3 P1_P0 P1_P1 4 5 P1_N2 P1_N3 6 7 P1_P2 P1_P3 8 9 P1_N4 P1_N P1_P4 P1_P P1_N6 P1_oCLKN P1_P6 P1_oCLKP P1_N7 P1_N P1_P7 P1_P P1_N9 P1_iCLKN P1_P9 P1_iCLKP P1_N10 P1_N P1_P10 P1_P P1_N12 P1_N P1_P12 P1_P P1_N14 P1_N15 34 June

10 35 P1_P14 P1_P n.c. n.c. 38 Table 4 : Front Panel IO assignment connector X3 Signal Name Signal name 1 P2_N0 P2_N1 2 3 P2_P0 P2_P1 4 5 P2_N2 P2_N3 6 7 P2_P2 P2_P3 8 9 P2_N4 P2_N P2_P4 P2_P P2_N6 P2_N P2_P6 P2_P P2_N8 P2_N P2_P8 P2_P P2_N10 P2_N P2_P10 P2_P P2_N12 P2_N P2_P12 P2_P P2_iCLKN P2_oCLKN P2_iCLKP P2_oCLKP P2_N14 P2_N P2_P14 P2_P n.c. n.c. 38 Table 5 : Front Panel IO assignment connector X4 The frontpanel connectors will mate with the highs speed MICTOR SB cable assemblies. The so-called BLUE RIBBON coax MICTOR SB cable assemblies deliver digital data at high speeds with low bit error rates. At the same time they are compact for high density applications, extremely flexible for easy routing and durable for repeated mate/demates. Figure 4: MICTOR SB cable assembly. June

11 Key Features Miniature ribbonized 38AWG 50 ohm (100 ohm differential) coax (UL style 2689) Ribbonized structure minimizes skew caused by conductor length differences Ribbonized configuration aligns with planar structure of circuit boards Compact for high density applications Flexible, robust and low profile BLUE RIBBON assemblies require minimal clearance Controlled impedance through the connectors, termination boards and miniature coax provide high signal integrity Available in both.5mm and.8mm versions Available in conductor lengths 0.1 to 10 meters 4 Environment 4.1 Temperature -40 C to +85 C Storage temperature: -40 C to +120 C 5 Safety This module presents no hazard to the user. 6 EMC This module is designed to operate from within an enclosed host system, which is build to provide EMC shielding. Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system. This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system. 7 Warranty Hardware Software/Firmware Basic Warranty (included) 1 Year from Date of Shipment 90 Days from Date of Shipment Extended Warranty (optional) 2 Years from Date of Shipment 1 Year from Date of Shipment June