CitrusCom CS0806U. Features. Applications. Mechanical Characteristics. Description. Circuit Diagram. Pin Configuration

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1 Features Transient protection for high-speed data lines IEC (ESD) ±1kV (Air) ±8kV (Contact) IEC (EFT) 0A (/0 ns) Cable Discharge Event (CDE) Small package (2.9mm 2.8mm 1.mm) Protects four data lines Low capacitance: 0.3pF Typical (I/O-I/O) Low leakage current: V RWM (Typical) Low clamping voltage Each I/O pin can withstand over 1000 ESD strikes for ±8kV contact discharge Description is an ultra-low capacitance Transient Voltage Suppressor (TVS) designed to provide electrostatic discharge (ESD) protection for high-speed data interfaces. With typical capacitance of 0.3pF only, is designed to protect parasitic-sensitive systems against over-voltage and over-current transient events. It complies with IEC (ESD), Level (±1kV air, ±8kV contact discharge), IEC (electrical fast transient - EFT) (0A, /0 ns), very fast charged device model (CDM) ESD and cable discharge event (CDE), etc. uses small SOT23-L package. Each device can protect four high-speed data lines. The combined features of low capacitance, small size and high ESD robustness make ideal for high-speed data ports and high-frequency lines (e.g., HDMI & DVI) applications. The low clamping voltage of the guarantees a minimum stress on the protected IC. Applications Serial ATA PCI Express Desktops, Servers and Notebooks MDDI Ports USB2.0 Power and Data Line Protection Display Ports High Definition Multi-Media Interface (HDMI) Digital Visual Interfaces (DVI) Mechanical Characteristics SOT23-L package Flammability Rating: UL 9V-0 Marking: Part number, Date Packaging: Tape and Reel Circuit Diagram I/O_2 VCC I/O_1 Pin Configuration I/O_ I/O_3 SOT23-L (Top View) Revision D 03/30/

2 Absolute Maximum Rating Symbol Parameter Value Units V ESD ESD per IEC (Air) ±17 kv ESD per IEC (Contact) ±12 T OPT Operating Temperature -/+12 C T STG Storage Temperature -/+10 C Electrical Characteristics (T = 2 C) Symbol V RWM I R Parameter Nominal Reverse Working Voltage Reverse Leakage V RWM Current I F V BR Reverse Breakdown I T I T V C I PP Test Current for Reverse Breakdown Clamping I PP Maximum Peak Pulse Current V RWM V BR V C I R IT V F Voltage C ESD Parasitic Capacitance V R Reverse Voltage f Small Signal Frequency I PP I F Forward Current V F Forward I F Uni-Directional TVS Symbol Test Condition Minimum Typical Maximum Units V RWM.0 V I R V BR V C C ESD C ESD V RWM = V, T = 2 C Between I/O and I T = 1mA Between I/O and I PP = 1A, t p = 8/20μs Between I/O and V R = 0V, f = 1MHz Between I/O and V R = 0V, f = 1MHz Between I/O and I/O μa V 12 V pf pf Revision D 03/30/

3 Clamping Voltage (V). Clamping Voltage (V). Capacitance (pf) Normalized Capacitance Current (A) Insertion Loss (db) CitrusCom Voltage Sweeping of I/O to Insertion Loss S21 of I/O to Voltage (V) E+0 1.0E E E E+10 Frequency (Hz) Capacitance vs. Voltage of I/O to (f = 1MHz) Capacitance vs. Reverse Voltage Normalized Capacitance vs. Reverse Voltage Reverse Voltage (V) Reverse Voltage (V) ESD Clamping of I/O to (+8kV Contact per IEC ) ESD Clamping of I/O to (-8kV Contact per IEC ) Time (ns) Time (ns) Revision D 03/30/

4 Application Information Pin Connection in PCB is capable to provide ESD protection for four data lines simultaneously. The pin connection is shown in Figure 1. Four parallel data lines, from inner IC to I/O port connector, could connect to four I/O pins directly. Pin 2 of is the negative reference pin, which should connect to the of PCB. The connection wires should be as short as possible in order to minimize the parasitic inductance. I/O1 To Connector To Inner IC I/O2 VCC PCB Layout Guidelines For optimum ESD protection and the whole circuit performance, the following PCB layout guidelines are recommended: pin to the PCB rail path should be as short as possible. It could reduce the ESD transient return path to. The vias connecting VCC & pins to the PCB VCC & should be wide. Place as close to the connector port as possible. It could reduce the parasitic inductance and restrict ESD coupling into adjacent traces. Avoid running critical signals near board edges. I/O3 To Connector To Inner IC I/O Figure 2 Layout Guideline Figure 1 pin connection in PCB Universal Serial Bus ESD Protection V BUS V BUS D+ D- USB Port1 USB Controller V BUS D+ D- USB Port2 Revision D 03/30/2012

5 Application Information (continued) TMDS_D2+ TMDS_D2+ TMDS_D2- TMDS_D2- TMDS_D1+ TMDS_D1+ TMDS_D1- TMDS_D1- HDMI RECEIVER TMDS_D0+ TMDS_D0- TMDS_CLK+ TMDS_D0+ TMDS_D0- TMDS_CLK+ HDMI CONNECTOR TMDS_CLK- TMDS_CLK- CEC CEC NC DDC_CLK DDC_DAT +V HOTPLUG_DET Layout Top View for HDMI Interface with Revision D 03/30/2012

6 Package Outline SOT23-L package A D e1 aaa C A-B D SEE VIEW A-A SECTION B-B b E1 E B c1 c B θ1 b1 B e N b ddd M C A-B D bbb C VIEW A-A A BASE METAL A A2 A1 ccc C GAUGE PLANE L2 θ L L1 C A3 SEATING PLANE Package Dimensions (Controlling dimensions are in millimeters) Symbol Dimensions (mm) Dimensions (Inches) Minimum Typical Maximum Minimum Typical Maximum A A A A A b b c c D 2.90 BSC 0.11 BSC e 0.9 BSC 37 BSC e BSC 7 BSC E 2.80 BSC BSC E1 1.0 BSC 3 BSC L L1 0 REF 2 REF L BSC 10 BSC θ θ aaa bbb ccc ddd Revision D 03/30/2012

7 Marking Codes Ordering Information UYWW Part Number Working Voltage Quantity Per Reel Reel Size V 3,000 7 Inch Note: (1) U is part number, fixed. (2) YWW is date code. Y is the assembly year (2011 is 1 ); while WW is the assembly week in a year. Revision D 03/30/