TVW MSOP 04 AD0 Engineering Specification

Transcription

1 TVW MSOP 4 AD 1 Scope TVW MSOP 4 AD s are TVS arrays designed to protect power/control lines and high-speed signal lines from overvoltage hazard of Electrostatic Discharge (ESD), Electrical Fast Transients (EFT) and Lightning. These interfaces can be used for high definition multi-media interface (HDMI) at 1.65 Gb/s and up to 3.2 Gb/s, digital visual interface (DVI), US2. power and data lines protection, notebook and personal computers, monitors and flat panel displays, IEEE 1394 Firewire Ports, etc. TVW MSOP 4 AD incorporates a pair of rail-to-rail diodes with low capacitance for each of four I/O channels. Additional Zener diode is employed to minimize the influence of supply voltage. The ESD protection of TVS arrays meets the immunity standard of IEC , level 4 (±15kV air, ±8kV contact discharge). 2 Explanation of Part Number TV W MSOP 4 AD (1) (2) (3) (4) (5) (1) Product Type:TV=TVS Diode (2) Capacitance Code:W=Ultra Low Capacitance (3) Package Size Code (4) Channel Code:4=4 Channels (5) Specialized Specification Code 3. Circuit Diagram /Pin Configuration MSOP-1L (Top View) SPEC REV.: A1 Page 1 of 1

2 4. Specifications 4.1 ASOLUTE MAXIMUM RATINGS PARAMETER PARAMETER RATING UNITS Operating Supply Voltage (VDD-GND) V DC 6 V ESD per IEC (Air) (I/O pins) 19 V ESD per IEC (Contact) (I/O pins) ESD_IO 12 kv Lead Soldering Temperature T SOL 26 (1 sec.) o C Operating Temperature T OP -55 to +85 o C Storage Temperature T STO -55 to +15 o C DC Voltage at any I/O pin V IO (GND.5) to (VDD +.5) V 4.2 ELECTRICAL CHARACTERISTICS PARAMETER SYMOL CONDITIONS MIN TYP MAX UNITS Reverse Stand-Off Voltage V RWM Pin 3 to pin 8, T=25 o C 5 V Reverse Leakage Current I Leak V RWM = 5V, T=25 o C, Pin 3 to pin 8 5 μa Channel Leakage Current I CH-Leak V Pin 3 = 5V, V Pin8 = V, T=25 o C 1 μa Reverse reakdown Voltage V V I V = 1mA, T=25 o C, Pin 3 to Pin V Forward Voltage V F I F = 15mA, T=25 o C, Pin 8 to Pin V IEC kV, T=25 o C, ESD Clamping V Voltage I/O clamping-io Contact mode, Any Channel pin to Ground 12.5 V Capacitance -1 Capacitance - 2 Channel to Channel Input Capacitance -1 Channel to Channel Input Capacitance -2 Variation of Capacitance -1 Variation of Capacitance -2 C IN-1 C IN-2 C CROSS-1 C CROSS-2 C IN-1 C IN-2 V pin3 = 5V, V pin8 = V, V IN = 2.5V, f = 1MHz, T=25 o C, Any Channel pin to Ground V pin3 = floated, V pin8 = V, V IN = 2.5V, f = 1MHz, T=25 o C, Any Channel pin to Ground V pin3 = 5V, V pin8 = V, V IN = 2.5V, f = 1MHz, T=25 o C, etween Channel pins V pin3 = floated, V pin8 = V, V IN = 2.5V, f = 1MHz, T=25 o C, etween Channel pins V pin3 = 5V, V pin8 = V, V IN = 2.5V, f = 1MHz, T=25 o C, Channel_x pin to Ground - Channel_y pin to Ground V pin3 = floated, V pin8 = V, V IN = 2.5V, f = 1MHz, T=25 o C, Channel_x pin to Ground - Channel_y pin to Ground pf.7.8 pf.8.9 pf.1.11 pf.4.6 pf.5.8 pf SPEC REV.: A1 Page 2 of 2

3 4.3 TYPICAL CHARACTERISTICS Typical Variation of C IN vs. V IN VDD = 5V, GND = V, f = 1MHz, T=25 o C, Typical Variation of C IN vs. V IN VDD = floated, GND = V, f = 1MHz, T=25 o C, Typical Variation of C IO-to-IO vs. V IN VDD = 5V, GND = V, f = 1MHz, T=25 o C, Typical Variation of C IO-to-IO vs. V IN VDD = floated, GND = V, f = 1MHz, T=25 o C, Insertion Loss (d) Insertion Loss S21 (I/O-to-GND) VDD = 5V 3GHz : -.455d 3.45GHz : -3d Insertion Loss (d) Insertion Loss S21 (I/O-to-GND) VDD = floated 2.9GHz : -3d SPEC REV.: A1 Page 3 of 3

4 Analog Cross Talk (d) Analog Cross Talk VDD = 5V Analog Cross Talk (d) Analog Cross Talk VDD = floated LAND LAYOUT D A E F Dimensions Index Millimeter Inches A C.5.2 D.3.11 E F C Notes: This LAND LAYOUT is for reference purposes only. Please consult your manufacturing partners to ensure your company s PC design guidelines are met. SPEC REV.: A1 Page 4 of 4

5 6. Application information The ESD protection scheme for system I/O connector is shown in the Fig. 1. In Fig. 1, the diodes D1 and D2 are general used to protect data line from ESD stress pulse. The diode D3 is a back-drive protection design, which blocks the DC back-drive current when the potential of I/O pin is greater than that of VDD pin. If the power-rail ESD clamping circuit is not placed between VDD and GND rails, the positive pulse ESD current (I ESD1 ) will pass through the ESD current path1. Thus, the ESD clamping voltage V CL of data line can be described as follow: V CL = Fwd voltage drop of D1 + reakdown voltage drop of D3 + supply voltage of VDD rail + L 1 d(i ESD1 )/dt + L 2 d(i ESD1 )/dt Where L 1 is the parasitic inductance of data line, and L 2 is the parasitic inductance of VDD rail. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC standard results in a current pulse that rises from zero to 3A in 1ns. Here d(i ESD1 )/dt can be approximated by ΔI ESD1 /Δt, or 3/(1x1-9 ). So just 1nH of total parasitic inductance (L 1 and L 2 combined) will lead to over 3V increment in V CL! esides, the ESD pulse current which is directed into the VDD rail may potentially damage any components that are attached to that rail. Moreover, it is common for the forward voltage drop of discrete diodes to exceed the damage threshold of the protected IC. This is due to the relatively small junction area of typical discrete components. Of course, the discrete diode is also possible to be destroyed due to its power dissipation capability is exceeded. The TVW MSOP 4 AD has an integrated power-rail ESD clamped circuit between VDD and GND rails. It can successfully overcome previous disadvantages. During an ESD event, the positive ESD pulse current (I ESD2 ) will be directed through the integrated power-rail ESD clamped circuit to GND rail (ESD current path2). The clamping voltage V CL on the data line is small and protected IC will not be damaged because power-rail ESD clamped circuit offer a low impedance path to discharge ESD pulse current. p ower-rail ESD clamp ing circuit TVWMSOP4AD D3 L 2 VDD rail + Vp _ I ESD2 D1 D2 I ESD1 L 1 data line VESD + V CL _ Protected IC GND rail ESD current path 1 (I ESD1) ESD current path 2 (I ESD2) SPEC REV.: A1 Page 5 of 5

6 7. MARKING CODE: Marking Code: 145QU 145QU= Device Code YWXX= Date Code Z= G means Green Part 145QU YWXXZ 8. Mechanical Details PACKAGE DIAGRAMS PACKAGE DIMENSIONS TOP VIEW SIDE VIEW Symbol Millimeters Inches min max min max A A1.2.8 A b C D e.5 SC.2 SC E Taping Quantity: 8pcs/ Tube E L θ 8 8 L SPEC REV.: A1 Page 6 of 6